Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	489	1			T539	3		T531	1		T540	1
all_values[1]	462	1			T539	2		T540	1		T536	3
all_values[2]	465	1			T539	4		T531	2		T540	1
all_values[3]	498	1			T539	4		T531	1		T536	2
all_values[4]	461	1			T539	3		T531	1		T544	2
all_values[5]	496	1			T539	2		T531	2		T536	5
all_values[6]	497	1			T539	4		T531	2		T536	2
all_values[7]	426	1			T539	1		T531	4		T552	1
all_values[8]	486	1			T539	5		T531	1		T536	1
all_values[9]	487	1			T539	2		T536	2		T846	1
all_values[10]	468	1			T539	1		T531	2		T552	2
all_values[11]	468	1			T539	7		T544	3		T694	1
all_values[12]	458	1			T539	3		T540	1		T536	3
all_values[13]	462	1			T539	3		T536	1		T544	1
all_values[14]	436	1			T531	1		T536	1		T544	3
all_values[15]	442	1			T539	1		T531	2		T540	1
all_values[16]	452	1			T539	1		T531	1		T536	2
all_values[17]	478	1			T539	4		T531	2		T536	1
all_values[18]	497	1			T539	2		T540	1		T536	1
all_values[19]	465	1			T539	4		T531	1		T536	5
all_values[20]	439	1			T539	1		T531	1		T540	2
all_values[21]	464	1			T539	3		T536	3		T544	2
all_values[22]	476	1			T539	3		T531	3		T552	2
all_values[23]	470	1			T539	3		T552	2		T846	1
all_values[24]	473	1			T539	1		T531	1		T536	3
all_values[25]	467	1			T539	4		T531	2		T552	1
all_values[26]	465	1			T539	3		T531	2		T536	1
all_values[27]	462	1			T539	2		T531	3		T536	2
all_values[28]	453	1			T539	2		T531	2		T536	2
all_values[29]	471	1			T539	1		T531	1		T536	3
all_values[30]	421	1			T539	3		T531	1		T552	1
all_values[31]	471	1			T235	1		T539	3		T540	1
all_values[32]	499	1			T539	2		T540	1		T536	1
all_values[33]	458	1			T531	1		T536	1		T544	3
all_values[34]	495	1			T539	6		T531	3		T538	1
all_values[35]	489	1			T539	2		T531	2		T540	1
all_values[36]	502	1			T539	1		T531	1		T552	2
all_values[37]	518	1			T539	2		T531	1		T536	1
all_values[38]	499	1			T539	3		T531	2		T536	3
all_values[39]	478	1			T235	1		T531	2		T536	3
all_values[40]	483	1			T539	3		T531	2		T552	2
all_values[41]	469	1			T539	1		T531	1		T540	1
all_values[42]	479	1			T235	1		T531	2		T544	3
all_values[43]	491	1			T539	3		T531	1		T540	1
all_values[44]	435	1			T539	2		T552	1		T536	1
all_values[45]	457	1			T531	2		T540	1		T538	1
all_values[46]	457	1			T539	2		T531	1		T536	2
all_values[47]	457	1			T539	5		T531	1		T538	1
all_values[48]	440	1			T539	5		T531	2		T536	2
all_values[49]	437	1			T539	3		T552	3		T536	3