Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
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Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv



Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 64 0 64 100.00


Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dev 64 0 64 100.00 100 1 1 0


Summary for Variable cp_dev

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 64 0 64 100.00


User Defined Bins for cp_dev

Excluded/Illegal bins
NAMECOUNTSTATUS
bin_others 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 3789 1 T539 23 T531 17 T536 12
all_values[1] 3712 1 T539 15 T531 9 T536 15
all_values[2] 3699 1 T539 13 T531 11 T536 12
all_values[3] 3648 1 T539 12 T531 10 T536 13
all_values[4] 3650 1 T539 25 T531 7 T536 10
all_values[5] 3651 1 T539 10 T531 5 T536 11
all_values[6] 3576 1 T539 10 T531 14 T536 8
all_values[7] 3619 1 T539 21 T531 12 T536 11
all_values[8] 3766 1 T539 13 T531 11 T536 13
all_values[9] 3620 1 T539 16 T531 14 T536 15
all_values[10] 3627 1 T539 19 T531 13 T536 6
all_values[11] 3589 1 T539 14 T531 7 T536 6
all_values[12] 3833 1 T539 20 T531 16 T536 15
all_values[13] 3771 1 T539 16 T531 17 T536 13
all_values[14] 3721 1 T539 14 T531 13 T536 13
all_values[15] 3622 1 T539 21 T531 15 T536 17
all_values[16] 3659 1 T539 16 T531 14 T536 9
all_values[17] 3678 1 T539 11 T531 12 T536 13
all_values[18] 3609 1 T539 9 T531 10 T536 11
all_values[19] 3640 1 T539 17 T531 11 T536 14
all_values[20] 3608 1 T539 17 T531 13 T536 7
all_values[21] 3648 1 T539 16 T531 7 T536 9
all_values[22] 3636 1 T539 18 T531 16 T536 14
all_values[23] 3578 1 T539 10 T531 10 T536 16
all_values[24] 3677 1 T539 12 T531 8 T536 11
all_values[25] 3611 1 T539 12 T531 16 T536 11
all_values[26] 3605 1 T539 8 T531 16 T536 12
all_values[27] 3748 1 T539 16 T531 7 T536 15
all_values[28] 3724 1 T539 15 T531 10 T536 12
all_values[29] 3686 1 T539 20 T531 11 T536 10
all_values[30] 3577 1 T539 19 T531 12 T536 9
all_values[31] 3659 1 T539 15 T531 16 T536 16
all_values[32] 3672 1 T539 14 T531 13 T536 8
all_values[33] 3688 1 T539 12 T531 7 T536 12
all_values[34] 3615 1 T539 16 T531 14 T536 9
all_values[35] 3669 1 T539 14 T531 16 T536 14
all_values[36] 3763 1 T539 18 T531 11 T536 12
all_values[37] 3698 1 T539 12 T531 6 T536 14
all_values[38] 3859 1 T539 20 T531 13 T536 16
all_values[39] 3579 1 T539 26 T531 7 T536 13
all_values[40] 3711 1 T539 10 T531 12 T536 10
all_values[41] 3730 1 T539 18 T531 6 T536 10
all_values[42] 3626 1 T539 15 T531 10 T536 14
all_values[43] 3692 1 T539 19 T531 13 T536 12
all_values[44] 3722 1 T539 9 T531 9 T536 9
all_values[45] 3715 1 T539 19 T531 8 T536 14
all_values[46] 3662 1 T539 19 T531 11 T536 11
all_values[47] 3640 1 T539 21 T531 14 T536 12
all_values[48] 3546 1 T539 15 T531 12 T536 13
all_values[49] 3710 1 T539 16 T531 7 T536 14
all_values[50] 3696 1 T539 9 T531 13 T536 12
all_values[51] 3667 1 T539 13 T531 12 T536 15
all_values[52] 3606 1 T539 15 T531 15 T536 16
all_values[53] 3668 1 T539 12 T531 15 T536 2
all_values[54] 3590 1 T539 16 T531 15 T536 8
all_values[55] 3739 1 T539 23 T531 18 T536 9
all_values[56] 3681 1 T539 17 T531 11 T536 10
all_values[57] 3512 1 T539 10 T531 14 T536 11
all_values[58] 3657 1 T539 18 T531 11 T536 14
all_values[59] 3795 1 T539 18 T531 13 T536 15
all_values[60] 3586 1 T539 5 T531 15 T536 7
all_values[61] 3713 1 T539 14 T531 11 T536 11
all_values[62] 3687 1 T539 15 T531 9 T536 12
all_values[63] 3589 1 T539 14 T531 11 T536 12

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