Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.alert_handler_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150512	1			T85	1193		T87	101		T124	648
values[2]	10453	1			T85	178		T87	4		T124	7
values[3]	3991	1			T85	42		T87	2		T124	7
values[4]	2242	1			T85	11		T124	11		T552	8
values[5]	1463	1			T85	5		T124	10		T552	1
values[6]	1007	1			T124	5		T552	2		T489	9
values[7]	762	1			T124	13		T552	2		T489	18
values[8]	589	1			T124	12		T552	2		T489	8
values[9]	572	1			T124	16		T552	2		T489	16
values[10]	477	1			T124	3		T552	2		T489	12
values[11]	405	1			T124	5		T552	2		T489	14
values[12]	366	1			T124	11		T552	1		T489	15
values[13]	402	1			T124	7		T552	5		T489	12
values[14]	332	1			T124	7		T552	1		T489	6
values[15]	317	1			T124	4		T552	1		T489	6
values[16]	292	1			T124	5		T552	2		T489	15
values[17]	304	1			T124	5		T552	1		T489	8
values[18]	322	1			T124	7		T552	6		T489	4
values[19]	319	1			T124	4		T552	7		T489	5
values[20]	323	1			T124	4		T552	8		T489	6
values[21]	327	1			T124	8		T552	3		T489	4
values[22]	306	1			T124	3		T552	2		T489	4
values[23]	266	1			T124	4		T552	2		T489	7
values[24]	301	1			T124	8		T552	3		T489	5
values[25]	302	1			T124	8		T552	2		T489	9
values[26]	380	1			T124	19		T552	3		T489	9
values[27]	326	1			T124	4		T552	7		T489	7
values[28]	279	1			T124	10		T552	1		T489	6
values[29]	285	1			T124	4		T552	3		T489	9
values[30]	331	1			T124	6		T552	2		T489	11
values[31]	320	1			T124	3		T552	9		T489	8
values[32]	317	1			T124	15		T552	3		T489	7
values[33]	316	1			T124	10		T552	2		T489	4
values[34]	297	1			T124	12		T552	5		T489	3
values[35]	296	1			T124	7		T552	3		T489	4
values[36]	361	1			T124	15		T552	2		T489	3
values[37]	373	1			T124	12		T552	3		T489	5
values[38]	341	1			T124	4		T552	2		T489	11
values[39]	333	1			T124	5		T552	4		T489	21
values[40]	325	1			T124	4		T552	2		T489	7
values[41]	334	1			T124	7		T552	3		T489	13
values[42]	329	1			T124	6		T552	4		T489	7
values[43]	357	1			T124	14		T552	5		T716	3
values[44]	326	1			T124	8		T552	3		T716	5
values[45]	278	1			T124	4		T552	1		T716	3
values[46]	300	1			T124	11		T552	1		T716	3
values[47]	272	1			T124	12		T552	2		T716	6
values[48]	269	1			T124	7		T552	3		T716	16
values[49]	272	1			T124	4		T552	4		T716	6
values[50]	246	1			T124	4		T552	1		T716	7
values[51]	278	1			T124	8		T552	3		T716	6
values[52]	249	1			T124	9		T552	2		T716	11
values[53]	312	1			T124	4		T552	2		T716	12
values[54]	293	1			T124	6		T552	9		T716	5
values[55]	203	1			T124	2		T552	5		T716	4
values[56]	330	1			T552	6		T716	4		T863	1
values[57]	269	1			T552	4		T716	4		T863	1
values[58]	275	1			T552	2		T716	8		T863	1
values[59]	249	1			T716	3		T863	1		T864	2
values[60]	242	1			T716	3		T863	1		T864	1
values[61]	231	1			T716	13		T863	1		T864	1
values[62]	206	1			T716	6		T863	1		T864	2
values[63]	216	1			T716	10		T863	1		T864	1
values[64]	220	1			T716	3		T863	1		T864	2
values[65]	211	1			T716	6		T863	1		T864	3
values[66]	199	1			T716	6		T863	1		T864	3
values[67]	162	1			T716	5		T863	1		T864	2
values[68]	142	1			T716	4		T863	1		T864	7
values[69]	119	1			T716	13		T863	1		T864	3
values[70]	148	1			T716	18		T863	1		T864	3
values[71]	108	1			T716	7		T863	1		T864	2
values[72]	95	1			T716	5		T863	1		T864	3
values[73]	97	1			T716	9		T863	1		T864	1
values[74]	103	1			T716	9		T863	1		T864	3
values[75]	100	1			T716	4		T863	1		T864	2
values[76]	121	1			T716	11		T863	1		T864	7
values[77]	82	1			T863	1		T864	5		T865	1
values[78]	92	1			T863	1		T864	12		T865	2
values[79]	99	1			T863	1		T864	3		T865	1
values[80]	90	1			T863	1		T864	6		T865	2
values[81]	82	1			T863	1		T864	3		T865	3
values[82]	86	1			T863	1		T864	6		T865	7
values[83]	75	1			T863	1		T864	3		T865	4
values[84]	86	1			T863	1		T864	2		T865	7
values[85]	88	1			T863	1		T864	2		T865	11
values[86]	96	1			T863	1		T864	4		T865	3
values[87]	81	1			T863	1		T864	4		T865	2
values[88]	73	1			T863	1		T864	3		T865	1
values[89]	86	1			T863	1		T864	11		T865	2
values[90]	89	1			T863	2		T864	7		T865	1
values[91]	76	1			T863	2		T864	5		T865	1
values[92]	101	1			T863	2		T864	18		T865	2
values[93]	89	1			T863	8		T864	4		T865	7
values[94]	104	1			T863	2		T864	12		T865	2
values[95]	84	1			T863	4		T864	8		T865	5
values[96]	77	1			T863	1		T864	4		T865	4
values[97]	81	1			T863	2		T864	8		T865	10
values[98]	78	1			T863	5		T864	17		T865	1
values[99]	85	1			T863	4		T864	14		T865	1
values[100]	95	1			T863	2		T864	12		T865	2
values[101]	79	1			T863	2		T864	5		T865	3
values[102]	75	1			T863	3		T864	7		T865	2
values[103]	63	1			T863	4		T864	10		T865	1
values[104]	65	1			T863	3		T864	10		T865	1
values[105]	63	1			T863	3		T864	2		T865	7
values[106]	73	1			T863	1		T864	4		T865	14
values[107]	82	1			T863	3		T864	6		T865	9
values[108]	48	1			T863	3		T864	7		T865	1
values[109]	53	1			T863	1		T864	4		T865	1
values[110]	52	1			T863	3		T864	3		T865	1
values[111]	49	1			T863	3		T864	1		T865	2
values[112]	40	1			T863	2		T864	1		T865	1
values[113]	51	1			T863	1		T864	1		T865	3
values[114]	62	1			T863	2		T864	3		T865	6
values[115]	50	1			T863	1		T864	1		T865	7
values[116]	49	1			T863	4		T864	2		T865	4
values[117]	60	1			T863	3		T864	10		T865	7
values[118]	54	1			T863	2		T864	2		T865	8
values[119]	58	1			T863	3		T864	1		T865	6
values[120]	55	1			T863	2		T865	13		T520	3
values[121]	43	1			T863	1		T865	7		T520	4
values[122]	47	1			T863	4		T865	3		T520	3
values[123]	51	1			T863	2		T865	2		T520	2
values[124]	43	1			T863	2		T865	1		T520	5
values[125]	61	1			T863	1		T865	1		T520	4
values[126]	174	1			T863	3		T865	7		T520	11
values[127]	654	1			T863	24		T865	4		T520	53
values[128]	5029	1			T863	320		T520	611		T866	307

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	167417	1			T85	1404		T87	114		T124	1553
values[2]	4243	1			T87	4		T564	2		T478	2
values[3]	1814	1			T564	1		T552	6		T717	1
values[4]	1186	1			T552	15		T514	1		T867	1
values[5]	828	1			T552	10		T514	1		T867	1
values[6]	598	1			T552	13		T514	1		T867	1
values[7]	557	1			T552	8		T514	1		T867	1
values[8]	521	1			T552	8		T514	1		T867	1
values[9]	517	1			T552	21		T514	1		T867	1
values[10]	476	1			T552	16		T514	1		T867	1
values[11]	468	1			T552	28		T514	1		T867	1
values[12]	424	1			T552	7		T514	1		T867	1
values[13]	386	1			T552	12		T514	1		T867	1
values[14]	328	1			T552	34		T514	1		T867	1
values[15]	328	1			T552	28		T514	1		T867	1
values[16]	282	1			T552	14		T514	1		T867	1
values[17]	273	1			T552	9		T514	1		T867	1
values[18]	254	1			T552	20		T514	1		T867	1
values[19]	228	1			T552	24		T514	1		T867	1
values[20]	214	1			T552	17		T514	1		T867	1
values[21]	200	1			T552	27		T514	1		T867	1
values[22]	156	1			T552	25		T514	1		T867	1
values[23]	153	1			T552	21		T514	1		T867	1
values[24]	148	1			T552	22		T514	1		T867	1
values[25]	125	1			T552	29		T514	1		T867	1
values[26]	96	1			T552	22		T514	1		T867	1
values[27]	108	1			T552	30		T514	1		T867	1
values[28]	91	1			T552	23		T514	1		T867	1
values[29]	102	1			T552	14		T514	1		T867	1
values[30]	99	1			T552	2		T514	1		T867	1
values[31]	96	1			T514	1		T867	1		T868	2
values[32]	90	1			T514	1		T867	1		T868	2
values[33]	84	1			T514	1		T867	1		T868	2
values[34]	89	1			T514	1		T867	1		T868	2
values[35]	90	1			T514	1		T867	1		T868	2
values[36]	107	1			T514	1		T867	1		T868	2
values[37]	128	1			T514	1		T867	1		T868	2
values[38]	101	1			T514	1		T867	1		T868	2
values[39]	130	1			T514	1		T867	1		T868	2
values[40]	103	1			T514	1		T867	1		T868	2
values[41]	81	1			T514	1		T867	1		T868	2
values[42]	72	1			T514	1		T867	1		T868	2
values[43]	67	1			T514	2		T867	1		T868	2
values[44]	75	1			T514	1		T867	1		T868	2
values[45]	77	1			T514	1		T867	1		T868	2
values[46]	66	1			T514	1		T867	1		T868	2
values[47]	62	1			T514	1		T867	1		T868	2
values[48]	64	1			T514	1		T867	1		T868	2
values[49]	79	1			T514	1		T867	1		T868	2
values[50]	80	1			T514	1		T867	1		T868	2
values[51]	77	1			T514	1		T867	1		T868	2
values[52]	77	1			T514	1		T867	1		T868	2
values[53]	96	1			T514	1		T867	1		T868	2
values[54]	96	1			T514	1		T867	1		T868	2
values[55]	76	1			T514	1		T867	1		T868	2
values[56]	81	1			T514	1		T867	1		T868	2
values[57]	78	1			T514	1		T867	2		T868	2
values[58]	85	1			T514	1		T867	1		T868	2
values[59]	73	1			T514	1		T867	1		T868	2
values[60]	72	1			T514	1		T867	1		T868	2
values[61]	69	1			T514	1		T867	1		T868	2
values[62]	49	1			T514	1		T867	1		T868	2
values[63]	55	1			T514	1		T867	1		T868	2
values[64]	57	1			T514	1		T867	1		T868	2
values[65]	61	1			T514	1		T867	1		T868	2
values[66]	66	1			T514	1		T867	1		T868	2
values[67]	61	1			T514	1		T867	1		T868	2
values[68]	68	1			T514	1		T867	1		T868	3
values[69]	59	1			T514	1		T867	1		T868	2
values[70]	62	1			T514	1		T867	1		T868	2
values[71]	61	1			T514	1		T867	1		T868	2
values[72]	57	1			T514	1		T867	1		T868	2
values[73]	53	1			T514	1		T867	1		T868	2
values[74]	71	1			T514	1		T867	1		T868	2
values[75]	60	1			T514	1		T867	1		T868	2
values[76]	51	1			T514	1		T867	1		T868	2
values[77]	66	1			T514	2		T867	1		T868	2
values[78]	65	1			T514	1		T867	1		T868	2
values[79]	72	1			T514	1		T867	1		T868	2
values[80]	80	1			T514	1		T867	1		T868	2
values[81]	81	1			T514	1		T867	1		T868	2
values[82]	72	1			T514	1		T867	1		T868	2
values[83]	73	1			T514	1		T867	1		T868	2
values[84]	71	1			T514	1		T867	1		T868	2
values[85]	81	1			T514	1		T867	1		T868	2
values[86]	74	1			T514	1		T867	1		T868	2
values[87]	67	1			T514	1		T867	1		T868	2
values[88]	73	1			T514	1		T867	1		T868	2
values[89]	84	1			T514	1		T867	1		T868	4
values[90]	96	1			T514	1		T867	1		T868	6
values[91]	82	1			T514	1		T867	1		T868	8
values[92]	60	1			T514	1		T867	1		T868	4
values[93]	80	1			T514	1		T867	1		T868	3
values[94]	73	1			T514	1		T867	1		T868	5
values[95]	81	1			T514	1		T867	1		T868	3
values[96]	94	1			T514	1		T867	1		T868	3
values[97]	97	1			T514	1		T867	1		T868	4
values[98]	90	1			T514	1		T867	1		T868	2
values[99]	100	1			T514	1		T867	1		T868	4
values[100]	112	1			T514	1		T867	1		T868	6
values[101]	94	1			T514	1		T867	1		T868	2
values[102]	77	1			T514	1		T867	1		T868	2
values[103]	95	1			T514	1		T867	1		T868	4
values[104]	110	1			T514	1		T867	1		T868	4
values[105]	100	1			T514	1		T867	1		T868	2
values[106]	122	1			T514	1		T867	1		T868	2
values[107]	100	1			T514	1		T867	1		T868	2
values[108]	114	1			T514	1		T867	1		T868	3
values[109]	93	1			T514	1		T867	1		T868	3
values[110]	98	1			T514	1		T867	1		T868	4
values[111]	92	1			T514	1		T867	1		T868	2
values[112]	137	1			T514	1		T867	1		T868	3
values[113]	118	1			T514	1		T867	1		T868	5
values[114]	89	1			T514	1		T867	1		T868	6
values[115]	93	1			T514	1		T867	1		T868	2
values[116]	98	1			T514	1		T867	1		T868	2
values[117]	93	1			T514	2		T867	1		T868	4
values[118]	82	1			T514	1		T867	1		T868	2
values[119]	105	1			T514	1		T867	2		T868	3
values[120]	106	1			T514	2		T867	2		T868	2
values[121]	97	1			T514	1		T867	2		T868	2
values[122]	101	1			T514	2		T867	1		T868	3
values[123]	105	1			T514	1		T867	1		T868	3
values[124]	194	1			T514	2		T867	1		T868	2
values[125]	362	1			T514	3		T867	1		T868	3
values[126]	725	1			T514	9		T867	13		T868	14
values[127]	2984	1			T514	106		T867	91		T868	185
values[128]	5797	1			T514	279		T867	187		T868	431

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146553	1			T85	374		T87	88		T124	612
values[2]	9190	1			T85	1		T87	2		T124	7
values[3]	3184	1			T124	2		T554	1		T553	16
values[4]	1964	1			T124	16		T554	1		T553	12
values[5]	1342	1			T124	3		T554	1		T553	4
values[6]	947	1			T124	8		T554	1		T553	14
values[7]	684	1			T124	7		T554	1		T553	5
values[8]	526	1			T124	8		T554	1		T553	3
values[9]	488	1			T124	13		T554	1		T553	6
values[10]	435	1			T124	5		T554	1		T489	13
values[11]	369	1			T124	4		T554	1		T489	4
values[12]	377	1			T124	9		T554	1		T489	10
values[13]	332	1			T124	4		T554	1		T489	8
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