Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.37 95.57 94.64 95.35 95.55 97.53 99.59


Total tests in report: 2931
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
39.59 39.59 44.96 44.96 42.99 42.99 31.89 31.89 57.86 57.86 59.44 59.44 0.39 0.39 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1306625303
49.04 9.45 50.71 5.75 58.47 15.48 32.47 0.58 68.27 10.41 82.52 23.08 1.81 1.42 /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.4261827518
57.61 8.57 63.12 12.42 62.39 3.92 40.61 8.15 69.61 1.34 82.52 0.00 27.42 25.61 /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.186055431
62.35 4.73 73.29 10.17 69.00 6.61 43.19 2.58 78.48 8.88 82.69 0.17 27.42 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_10.1229286000
66.12 3.78 73.29 0.00 69.13 0.13 43.19 0.00 78.50 0.02 82.69 0.00 49.92 22.50 /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1200241610
69.25 3.13 78.63 5.34 73.10 3.97 46.84 3.65 80.28 1.78 86.71 4.02 49.92 0.00 /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3733926912
71.84 2.59 78.63 0.00 73.15 0.04 46.84 0.00 80.28 0.00 86.71 0.00 65.43 15.51 /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2368928937
74.27 2.43 78.64 0.01 73.17 0.03 61.20 14.35 80.30 0.02 86.89 0.17 65.43 0.00 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3317646799
76.43 2.16 78.65 0.01 73.76 0.58 61.20 0.00 80.54 0.24 86.89 0.00 77.56 12.13 /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3709392808
78.45 2.02 80.51 1.86 76.20 2.44 67.05 5.85 82.31 1.77 87.06 0.17 77.56 0.00 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.369586908
80.28 1.83 82.74 2.24 78.50 2.30 68.38 1.33 84.19 1.87 90.21 3.15 77.65 0.09 /workspace/coverage/default/0.chip_jtag_csr_rw.1849884320
81.69 1.41 84.90 2.16 80.42 1.92 70.46 2.08 86.47 2.29 90.21 0.00 77.65 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.288230208
83.01 1.33 85.19 0.29 80.57 0.15 77.62 7.16 86.65 0.18 90.38 0.17 77.65 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2356719230
84.22 1.21 85.19 0.00 80.57 0.00 77.62 0.00 86.65 0.00 90.38 0.00 84.93 7.27 /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.472287850
85.30 1.08 87.20 2.02 81.66 1.09 79.22 1.60 87.37 0.71 91.43 1.05 84.93 0.00 /workspace/coverage/default/1.chip_sw_power_virus.3121878940
86.28 0.98 87.78 0.58 82.42 0.76 81.25 2.03 87.89 0.52 91.43 0.00 86.90 1.97 /workspace/coverage/default/1.chip_sw_alert_test.841152808
86.99 0.71 88.02 0.24 82.52 0.09 81.26 0.01 87.98 0.09 95.28 3.85 86.90 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2800501273
87.70 0.70 88.02 0.00 82.53 0.01 81.26 0.00 87.98 0.00 95.28 0.00 91.11 4.21 /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.826970398
88.38 0.69 88.80 0.78 83.99 1.47 81.36 0.10 89.77 1.79 95.28 0.00 91.11 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.754233730
89.04 0.65 90.04 1.24 84.96 0.97 81.90 0.54 90.94 1.17 95.28 0.00 91.11 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.1854109000
89.64 0.60 90.99 0.95 85.81 0.84 82.23 0.33 91.92 0.98 95.80 0.52 91.11 0.00 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1953609812
90.22 0.58 90.99 0.00 85.81 0.00 85.68 3.46 91.92 0.00 95.80 0.00 91.11 0.00 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2987732390
90.75 0.54 91.78 0.79 86.36 0.55 86.71 1.02 92.75 0.84 95.80 0.00 91.12 0.01 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2333595227
91.23 0.47 92.90 1.12 87.09 0.73 87.19 0.49 93.25 0.49 95.80 0.00 91.12 0.00 /workspace/coverage/default/2.chip_sw_gpio.3173607169
91.67 0.44 92.90 0.00 87.09 0.00 87.19 0.00 93.25 0.00 95.80 0.00 93.76 2.64 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3777557129
92.04 0.38 92.90 0.00 87.11 0.02 87.19 0.00 93.25 0.00 95.80 0.00 95.99 2.23 /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2197921964
92.34 0.29 92.95 0.04 87.14 0.03 88.88 1.69 93.25 0.00 95.80 0.00 95.99 0.00 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4233885428
92.60 0.26 92.96 0.01 88.55 1.41 88.88 0.00 93.25 0.00 95.80 0.00 96.13 0.14 /workspace/coverage/cover_reg_top/24.chip_tl_errors.1343607656
92.79 0.19 92.96 0.00 88.55 0.00 90.04 1.16 93.25 0.00 95.80 0.00 96.13 0.00 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2722711749
92.98 0.19 93.15 0.19 89.48 0.93 90.05 0.01 93.25 0.00 95.80 0.00 96.13 0.00 /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.2528721445
93.16 0.18 93.45 0.31 89.64 0.16 90.41 0.36 93.52 0.27 95.80 0.00 96.13 0.00 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1676208984
93.31 0.15 93.66 0.21 89.96 0.32 90.76 0.35 93.52 0.00 95.80 0.00 96.13 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1663618328
93.45 0.14 94.06 0.40 90.16 0.20 90.84 0.07 93.69 0.17 95.80 0.00 96.15 0.01 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904612141
93.59 0.14 94.09 0.03 90.51 0.35 90.85 0.01 94.09 0.40 95.80 0.00 96.18 0.04 /workspace/coverage/default/1.chip_jtag_csr_rw.845033165
93.72 0.13 94.09 0.00 90.52 0.01 90.85 0.00 94.09 0.00 95.80 0.00 96.96 0.78 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.4226987870
93.84 0.12 94.09 0.00 90.55 0.03 90.85 0.00 94.09 0.00 95.80 0.00 97.65 0.69 /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.2461112712
93.96 0.12 94.09 0.00 91.26 0.71 90.85 0.00 94.09 0.00 95.80 0.00 97.65 0.00 /workspace/coverage/cover_reg_top/4.chip_tl_errors.1874650946
94.07 0.12 94.10 0.01 91.26 0.01 91.52 0.67 94.09 0.00 95.80 0.00 97.65 0.00 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3607446661
94.18 0.11 94.10 0.00 91.38 0.12 91.53 0.01 94.12 0.03 96.33 0.52 97.65 0.00 /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3440488605
94.29 0.11 94.11 0.01 91.68 0.30 91.54 0.01 94.46 0.34 96.33 0.00 97.65 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.1697843367
94.40 0.11 94.20 0.09 91.71 0.02 92.07 0.53 94.47 0.01 96.33 0.00 97.65 0.00 /workspace/coverage/default/0.chip_jtag_mem_access.263899210
94.50 0.09 94.25 0.05 91.79 0.08 92.30 0.23 94.51 0.04 96.50 0.17 97.65 0.00 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1145087368
94.59 0.09 94.43 0.18 91.92 0.13 92.42 0.12 94.63 0.12 96.50 0.00 97.65 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.30311029
94.67 0.08 94.45 0.02 92.14 0.22 92.42 0.00 94.89 0.26 96.50 0.00 97.65 0.00 /workspace/coverage/default/2.chip_jtag_csr_rw.3166783971
94.76 0.08 94.45 0.00 92.22 0.08 92.42 0.00 94.92 0.03 96.50 0.00 98.03 0.38 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.3579044649
94.84 0.08 94.45 0.00 92.22 0.00 92.89 0.47 94.92 0.00 96.50 0.00 98.03 0.00 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3236029912
94.91 0.07 94.45 0.00 92.22 0.00 93.34 0.45 94.92 0.00 96.50 0.00 98.03 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3425693506
94.98 0.07 94.45 0.00 92.36 0.14 93.34 0.00 94.94 0.02 96.50 0.00 98.30 0.27 /workspace/coverage/cover_reg_top/12.xbar_stress_all.148173828
95.04 0.06 94.45 0.00 92.51 0.16 93.35 0.01 95.12 0.18 96.50 0.00 98.30 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1063447882
95.09 0.05 94.45 0.00 92.81 0.29 93.35 0.00 95.12 0.00 96.50 0.00 98.30 0.00 /workspace/coverage/cover_reg_top/2.chip_tl_errors.146106767
95.13 0.05 94.45 0.00 92.81 0.00 93.62 0.27 95.12 0.00 96.50 0.00 98.30 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2025298083
95.18 0.04 94.49 0.04 92.84 0.04 93.78 0.17 95.14 0.02 96.50 0.00 98.30 0.00 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4047609159
95.22 0.04 94.49 0.00 92.84 0.00 94.04 0.26 95.14 0.00 96.50 0.00 98.30 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2609469950
95.26 0.04 94.52 0.03 92.85 0.01 94.07 0.03 95.15 0.01 96.68 0.17 98.31 0.01 /workspace/coverage/default/34.chip_sw_all_escalation_resets.1650997135
95.30 0.04 94.52 0.00 92.91 0.06 94.07 0.00 95.15 0.00 96.68 0.00 98.48 0.18 /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.632756921
95.34 0.04 94.53 0.01 92.92 0.01 94.07 0.00 95.17 0.02 96.85 0.17 98.50 0.01 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3485708318
95.38 0.04 94.57 0.04 93.03 0.10 94.07 0.00 95.25 0.07 96.85 0.00 98.50 0.00 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.1627335529
95.41 0.04 94.57 0.01 93.04 0.01 94.07 0.01 95.25 0.01 97.03 0.17 98.51 0.01 /workspace/coverage/default/22.chip_sw_all_escalation_resets.501754251
95.45 0.04 94.58 0.01 93.05 0.01 94.07 0.00 95.26 0.01 97.20 0.17 98.52 0.01 /workspace/coverage/default/19.chip_sw_all_escalation_resets.224785518
95.48 0.04 94.58 0.01 93.06 0.01 94.08 0.01 95.27 0.01 97.38 0.17 98.53 0.01 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1052935063
95.52 0.03 94.59 0.01 93.10 0.04 94.22 0.14 95.28 0.01 97.38 0.00 98.53 0.00 /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1175970340
95.55 0.03 94.59 0.00 93.10 0.01 94.23 0.01 95.28 0.00 97.55 0.17 98.53 0.00 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4089177382
95.58 0.03 94.59 0.00 93.28 0.18 94.23 0.00 95.28 0.00 97.55 0.00 98.53 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.1506769989
95.61 0.03 94.63 0.03 93.30 0.01 94.33 0.10 95.29 0.01 97.55 0.00 98.54 0.01 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2590188383
95.63 0.03 94.70 0.07 93.33 0.03 94.33 0.01 95.33 0.05 97.55 0.00 98.54 0.00 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1025277811
95.65 0.02 94.70 0.00 93.41 0.08 94.33 0.00 95.35 0.02 97.55 0.00 98.58 0.04 /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.535049802
95.68 0.02 94.71 0.01 93.47 0.06 94.37 0.04 95.38 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3333442603
95.70 0.02 94.73 0.02 93.48 0.01 94.45 0.08 95.40 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.2863950941
95.72 0.02 94.73 0.00 93.48 0.00 94.58 0.13 95.40 0.00 97.55 0.00 98.58 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4289141452
95.74 0.02 94.78 0.05 93.53 0.05 94.58 0.00 95.42 0.02 97.55 0.00 98.58 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3571784179
95.76 0.02 94.85 0.07 93.53 0.00 94.62 0.04 95.43 0.01 97.55 0.00 98.58 0.00 /workspace/coverage/default/4.chip_tap_straps_rma.1441576750
95.78 0.02 94.85 0.00 93.60 0.07 94.62 0.00 95.45 0.02 97.55 0.00 98.61 0.04 /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2976898825
95.80 0.02 94.85 0.00 93.60 0.00 94.74 0.12 95.45 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.399462595
95.82 0.02 94.85 0.00 93.71 0.11 94.74 0.00 95.45 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/cover_reg_top/6.chip_tl_errors.1712448850
95.84 0.02 94.86 0.01 93.72 0.01 94.83 0.09 95.45 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2795144638
95.86 0.02 94.87 0.01 93.80 0.08 94.83 0.00 95.46 0.02 97.55 0.00 98.61 0.00 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.3513102455
95.87 0.02 94.87 0.00 93.90 0.10 94.83 0.00 95.46 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.110331953
95.89 0.02 94.88 0.01 93.93 0.03 94.89 0.06 95.46 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1149565425
95.90 0.01 94.88 0.00 94.00 0.07 94.89 0.00 95.46 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.3734805263
95.91 0.01 94.88 0.00 94.04 0.04 94.89 0.00 95.46 0.00 97.55 0.00 98.64 0.02 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.48166992
95.92 0.01 94.88 0.00 94.08 0.04 94.89 0.01 95.49 0.02 97.55 0.00 98.64 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1485555549
95.93 0.01 94.91 0.03 94.10 0.02 94.89 0.00 95.50 0.01 97.55 0.00 98.64 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.2319119214
95.94 0.01 94.91 0.00 94.10 0.00 94.95 0.05 95.50 0.00 97.55 0.00 98.64 0.00 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3176811824
95.95 0.01 94.91 0.00 94.14 0.04 94.95 0.00 95.50 0.00 97.55 0.00 98.65 0.01 /workspace/coverage/cover_reg_top/21.chip_tl_errors.2187533597
95.96 0.01 94.91 0.00 94.14 0.01 94.95 0.00 95.50 0.00 97.55 0.00 98.70 0.05 /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.863631748
95.97 0.01 94.94 0.02 94.15 0.01 94.95 0.01 95.51 0.02 97.55 0.00 98.70 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4252932154
95.97 0.01 94.96 0.02 94.16 0.01 94.95 0.01 95.53 0.02 97.55 0.00 98.70 0.00 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3234057114
95.98 0.01 94.96 0.00 94.16 0.00 94.95 0.00 95.53 0.00 97.55 0.00 98.74 0.05 /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1941824516
95.99 0.01 94.96 0.00 94.20 0.05 94.95 0.00 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/cover_reg_top/68.xbar_stress_all.561727190
96.00 0.01 94.96 0.00 94.25 0.04 94.95 0.00 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.3701901698
96.00 0.01 94.96 0.00 94.25 0.00 94.99 0.04 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3793052398
96.01 0.01 94.96 0.00 94.29 0.04 94.99 0.00 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.2636130449
96.02 0.01 94.96 0.00 94.29 0.00 95.03 0.04 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.847085343
96.02 0.01 94.96 0.00 94.29 0.00 95.07 0.04 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/2.chip_tap_straps_dev.611816596
96.03 0.01 94.96 0.00 94.29 0.00 95.10 0.03 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.159123687
96.03 0.01 94.96 0.00 94.32 0.03 95.10 0.00 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/cover_reg_top/25.chip_tl_errors.1811898132
96.04 0.01 94.96 0.01 94.34 0.02 95.11 0.01 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.61470266
96.04 0.01 94.96 0.00 94.36 0.03 95.11 0.00 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.468472943
96.05 0.01 94.96 0.00 94.39 0.03 95.11 0.00 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.774414137
96.05 0.01 94.96 0.00 94.39 0.00 95.14 0.03 95.53 0.00 97.55 0.00 98.74 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2980310174
96.06 0.01 94.96 0.00 94.39 0.00 95.15 0.02 95.53 0.00 97.55 0.00 98.75 0.01 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3160380803
96.06 0.01 94.96 0.00 94.41 0.01 95.15 0.00 95.53 0.00 97.55 0.00 98.77 0.01 /workspace/coverage/cover_reg_top/13.xbar_stress_all.1637978484
96.07 0.01 94.96 0.00 94.41 0.00 95.15 0.00 95.53 0.00 97.55 0.00 98.79 0.02 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.1368834475
96.07 0.01 94.97 0.01 94.42 0.01 95.16 0.01 95.53 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3197533733
96.07 0.01 94.97 0.00 94.44 0.02 95.16 0.00 95.53 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/cover_reg_top/23.xbar_stress_all.2732466538
96.08 0.01 94.97 0.00 94.44 0.00 95.18 0.02 95.53 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3023593464
96.08 0.01 94.97 0.00 94.45 0.01 95.18 0.00 95.53 0.00 97.55 0.00 98.80 0.01 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.4030775644
96.08 0.01 94.97 0.00 94.46 0.01 95.18 0.00 95.53 0.00 97.55 0.00 98.81 0.01 /workspace/coverage/cover_reg_top/7.chip_tl_errors.2946900180
96.09 0.01 94.97 0.00 94.46 0.01 95.18 0.00 95.53 0.00 97.55 0.00 98.83 0.01 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.1877249204
96.09 0.01 94.97 0.00 94.46 0.00 95.20 0.02 95.53 0.00 97.55 0.00 98.83 0.00 /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.238795854
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96.28 0.01 94.99 0.00 94.64 0.00 95.34 0.01 95.55 0.00 97.55 0.00 99.59 0.00 /workspace/coverage/default/1.chip_tap_straps_rma.1404994457
96.28 0.01 94.99 0.00 94.64 0.00 95.34 0.01 95.55 0.00 97.55 0.00 99.59 0.00 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3906968217
96.28 0.01 94.99 0.00 94.64 0.00 95.34 0.01 95.55 0.00 97.55 0.00 99.59 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2635858874
96.28 0.01 94.99 0.00 94.64 0.00 95.34 0.01 95.55 0.00 97.55 0.00 99.59 0.00 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.1683785726
96.28 0.01 94.99 0.00 94.64 0.00 95.35 0.01 95.55 0.00 97.55 0.00 99.59 0.00 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1277006676


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.89508103
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1700278541
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2828546982
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.3060227849
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2720359068
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.686999632
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4136044272
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1754475825
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.880790102
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2167510355
/workspace/coverage/cover_reg_top/0.xbar_error_random.198315643
/workspace/coverage/cover_reg_top/0.xbar_random.2141394078
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2705263158
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.164432871
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2353113320
/workspace/coverage/cover_reg_top/0.xbar_same_source.1810183849
/workspace/coverage/cover_reg_top/0.xbar_smoke.3372866300
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3622692052
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1787400854
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2525636126
/workspace/coverage/cover_reg_top/0.xbar_stress_all.734860837
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.1723474611
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.247034982
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2191038096
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3481860736
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3258631736
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1123290490
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.769322537
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1140104443
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1413072931
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1450387766
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3365448029
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.4120795648
/workspace/coverage/cover_reg_top/1.chip_tl_errors.834246526
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.992939052
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2203635848
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2551966027
/workspace/coverage/cover_reg_top/1.xbar_error_random.980641693
/workspace/coverage/cover_reg_top/1.xbar_random.3152532992
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.371446763
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.3237560776
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3908331344
/workspace/coverage/cover_reg_top/1.xbar_same_source.1679277725
/workspace/coverage/cover_reg_top/1.xbar_smoke.3082698713
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1067006294
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.450722102
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2189938033
/workspace/coverage/cover_reg_top/1.xbar_stress_all.806548810
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.800062710
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.760071220
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.896866367
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1708084079
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2169554969
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3163623427
/workspace/coverage/cover_reg_top/10.chip_tl_errors.1803736213
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3410983833
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3091920418
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.998904759
/workspace/coverage/cover_reg_top/10.xbar_error_random.1836862378
/workspace/coverage/cover_reg_top/10.xbar_random.1663516334
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.4163987494
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.833557262
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.680121807
/workspace/coverage/cover_reg_top/10.xbar_same_source.2119418985
/workspace/coverage/cover_reg_top/10.xbar_smoke.2073292105
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.54014778
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.2078403915
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3490737216
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.2690418188
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3060268812
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3454254098
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3406144252
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1003175485
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3612673998
/workspace/coverage/cover_reg_top/11.chip_tl_errors.3792214153
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.615131731
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1539258714
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3012752270
/workspace/coverage/cover_reg_top/11.xbar_error_random.689571969
/workspace/coverage/cover_reg_top/11.xbar_random.3079051234
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.58220631
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3761922160
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2373949237
/workspace/coverage/cover_reg_top/11.xbar_same_source.2560611123
/workspace/coverage/cover_reg_top/11.xbar_smoke.2108692801
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.586337537
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.805660668
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.705429184
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2843434336
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1213823843
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3675074165
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2330560381
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3106282507
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3001720655
/workspace/coverage/cover_reg_top/12.chip_csr_rw.1267533248
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3687966696
/workspace/coverage/cover_reg_top/12.chip_tl_errors.568488444
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1211832563
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.495330630
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2858018505
/workspace/coverage/cover_reg_top/12.xbar_error_random.2503527575
/workspace/coverage/cover_reg_top/12.xbar_random.1452192085
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.4069447555
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1362150545
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1399619862
/workspace/coverage/cover_reg_top/12.xbar_same_source.503267286
/workspace/coverage/cover_reg_top/12.xbar_smoke.2259055917
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3087301739
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1276875475
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2735023577
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3721324921
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.752551528
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1616178958
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1078916231
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3899955654
/workspace/coverage/cover_reg_top/13.chip_csr_rw.1494160989
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.686549321
/workspace/coverage/cover_reg_top/13.chip_tl_errors.560649469
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.951978604
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3930173672
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.813571464
/workspace/coverage/cover_reg_top/13.xbar_random.443089015
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.420510713
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2343783646
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1891776749
/workspace/coverage/cover_reg_top/13.xbar_same_source.2306905642
/workspace/coverage/cover_reg_top/13.xbar_smoke.1087049488
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2205101510
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1401981149
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1287710588
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.2845512361
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2046892361
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1476911437
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1480110214
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.4242290275
/workspace/coverage/cover_reg_top/14.chip_csr_rw.1803736297
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.581984120
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3676803927
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2973952105
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3717158212
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3482993147
/workspace/coverage/cover_reg_top/14.xbar_error_random.3405208485
/workspace/coverage/cover_reg_top/14.xbar_random.2066978813
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.669883142
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2059663523
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3377354913
/workspace/coverage/cover_reg_top/14.xbar_same_source.1023626387
/workspace/coverage/cover_reg_top/14.xbar_smoke.934218708
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3649559500
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.192731138
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.2724024167
/workspace/coverage/cover_reg_top/14.xbar_stress_all.3513170234
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1385999536
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.2141402049
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.3492337578
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.1247151241
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3229628963
/workspace/coverage/cover_reg_top/15.chip_tl_errors.2060567075
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.2227017226
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.556360517
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.4071101193
/workspace/coverage/cover_reg_top/15.xbar_error_random.1117750967
/workspace/coverage/cover_reg_top/15.xbar_random.2129936483
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3502236791
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.2026350036
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.661473909
/workspace/coverage/cover_reg_top/15.xbar_same_source.1994792724
/workspace/coverage/cover_reg_top/15.xbar_smoke.1870196204
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.1008685424
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.2825085489
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2799378178
/workspace/coverage/cover_reg_top/15.xbar_stress_all.1067749584
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.3643942803
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2812704346
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1109241437
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.380401515
/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3801334173
/workspace/coverage/cover_reg_top/16.chip_csr_rw.157251100
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.3664268930
/workspace/coverage/cover_reg_top/16.chip_tl_errors.1865951247
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.461340267
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.3300973766
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.1579182103
/workspace/coverage/cover_reg_top/16.xbar_error_random.853942356
/workspace/coverage/cover_reg_top/16.xbar_random.4056163318
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.51596199
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.730870943
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.1061626811
/workspace/coverage/cover_reg_top/16.xbar_same_source.1899451560
/workspace/coverage/cover_reg_top/16.xbar_smoke.3003070404
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2673418589
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1285199043
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.1410129420
/workspace/coverage/cover_reg_top/16.xbar_stress_all.1478948353
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3061769223
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.3879302737
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.1577323556
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1504975723
/workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2155334196
/workspace/coverage/cover_reg_top/17.chip_csr_rw.2704523793
/workspace/coverage/cover_reg_top/17.chip_tl_errors.1364807829
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.4089840223
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.812348590
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.2074084624
/workspace/coverage/cover_reg_top/17.xbar_error_random.2429128115
/workspace/coverage/cover_reg_top/17.xbar_random.3500643937
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.2318755593
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2226577205
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.617110158
/workspace/coverage/cover_reg_top/17.xbar_same_source.1400406454
/workspace/coverage/cover_reg_top/17.xbar_smoke.3322948505
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2100663214
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1943842270
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.3499174628
/workspace/coverage/cover_reg_top/17.xbar_stress_all.4195231858
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.4187383216
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.15633079
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2497011663
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.8153830
/workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.4004236889
/workspace/coverage/cover_reg_top/18.chip_csr_rw.2641140201
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3600427288
/workspace/coverage/cover_reg_top/18.chip_tl_errors.899319883
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.4113400638
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.3065196063
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.214387609
/workspace/coverage/cover_reg_top/18.xbar_error_random.2556617005
/workspace/coverage/cover_reg_top/18.xbar_random.3546829023
/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.78380191
/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1336977672
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.257523574
/workspace/coverage/cover_reg_top/18.xbar_same_source.276999542
/workspace/coverage/cover_reg_top/18.xbar_smoke.145104747
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.1832525258
/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.657457609
/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1164154821
/workspace/coverage/cover_reg_top/18.xbar_stress_all.3435042176
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1680792700
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.2200687438
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.4006812621
/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3860248988
/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2186440479
/workspace/coverage/cover_reg_top/19.chip_csr_rw.1678944301
/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2912962391
/workspace/coverage/cover_reg_top/19.chip_tl_errors.2125382129
/workspace/coverage/cover_reg_top/19.xbar_access_same_device.3622132499
/workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.953089275
/workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.4140215409
/workspace/coverage/cover_reg_top/19.xbar_error_random.1667005796
/workspace/coverage/cover_reg_top/19.xbar_random.2458175268
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3499360994
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3715886023
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3101629506
/workspace/coverage/default/4.chip_tap_straps_dev.3754448605
/workspace/coverage/default/4.chip_tap_straps_prod.2186375656
/workspace/coverage/default/4.chip_tap_straps_testunlock0.3724430956
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.420527758
/workspace/coverage/default/40.chip_sw_all_escalation_resets.273271840
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2307080457
/workspace/coverage/default/41.chip_sw_all_escalation_resets.453670031
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2675214580
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.173934336
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3598757848
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2345945698
/workspace/coverage/default/45.chip_sw_all_escalation_resets.2268600982
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672231308
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1074020937
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3675058023
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1576509934
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1446175338
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4090602139
/workspace/coverage/default/5.chip_sw_all_escalation_resets.954200568
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1457508883
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.451283128
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.121536833
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3575381136
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1153287781
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4022439959
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2705729541
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2943267613
/workspace/coverage/default/55.chip_sw_all_escalation_resets.915473112
/workspace/coverage/default/56.chip_sw_all_escalation_resets.3049490498
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155475832
/workspace/coverage/default/57.chip_sw_all_escalation_resets.757720944
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.4285811724
/workspace/coverage/default/58.chip_sw_all_escalation_resets.3745142320
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174305160
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.918874576
/workspace/coverage/default/6.chip_sw_all_escalation_resets.637640804
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.3306577575
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2826085410
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1493535846
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.4071020253
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3640357779
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3292681612
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3571275148
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1621707459
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1818667961
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.145711599
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3143374839
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.15916613
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3381514371
/workspace/coverage/default/68.chip_sw_all_escalation_resets.935632181
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775209875
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2699091671
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1793731954
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1162656254
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3947345056
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2387929347
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2374086917
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797677478
/workspace/coverage/default/72.chip_sw_all_escalation_resets.235178519
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2202569065
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2633612530
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.837939794
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2397335387
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399622969
/workspace/coverage/default/75.chip_sw_all_escalation_resets.805635778
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2161577863
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1315022409
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.425981766
/workspace/coverage/default/78.chip_sw_all_escalation_resets.1452204781
/workspace/coverage/default/79.chip_sw_all_escalation_resets.3855087630
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2415142742
/workspace/coverage/default/8.chip_sw_all_escalation_resets.830194478
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1904378172
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3702081437
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964293014
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1034522258
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830000774
/workspace/coverage/default/81.chip_sw_all_escalation_resets.805911875
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3675042461
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1057451156
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3799380375
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2796006103
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.288450195
/workspace/coverage/default/85.chip_sw_all_escalation_resets.775486969
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1479800292
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.685006764
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2474414871
/workspace/coverage/default/88.chip_sw_all_escalation_resets.585382326
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2625414694
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2995518494
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.290020731
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3216765743
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1507264575
/workspace/coverage/default/90.chip_sw_all_escalation_resets.4067623288
/workspace/coverage/default/91.chip_sw_all_escalation_resets.62930847
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1183224063
/workspace/coverage/default/93.chip_sw_all_escalation_resets.681721865
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1505860469
/workspace/coverage/default/95.chip_sw_all_escalation_resets.17722909
/workspace/coverage/default/96.chip_sw_all_escalation_resets.891035824
/workspace/coverage/default/97.chip_sw_all_escalation_resets.470528804
/workspace/coverage/default/98.chip_sw_all_escalation_resets.265820525
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3381088067
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.241269224
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.21651967
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.233123665
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2523071507
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.417587248
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.774603622
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4058339183




Total test records in report: 2931
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1133423540 Jul 27 07:55:04 PM PDT 24 Jul 27 08:06:08 PM PDT 24 3935483858 ps
T2 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1485555549 Jul 27 07:52:19 PM PDT 24 Jul 27 07:57:43 PM PDT 24 4173848616 ps
T3 /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.123925515 Jul 27 07:52:42 PM PDT 24 Jul 27 07:59:38 PM PDT 24 6600291805 ps
T94 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2635858874 Jul 27 07:54:18 PM PDT 24 Jul 27 08:03:24 PM PDT 24 3149968584 ps
T4 /workspace/coverage/default/89.chip_sw_all_escalation_resets.2590188383 Jul 27 08:29:11 PM PDT 24 Jul 27 08:40:32 PM PDT 24 4934545800 ps
T28 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3176811824 Jul 27 08:05:14 PM PDT 24 Jul 27 08:15:48 PM PDT 24 8632144240 ps
T42 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.369586908 Jul 27 08:13:47 PM PDT 24 Jul 27 09:02:21 PM PDT 24 11736632141 ps
T70 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1306625303 Jul 27 08:27:09 PM PDT 24 Jul 27 08:34:30 PM PDT 24 4899289400 ps
T95 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3623610418 Jul 27 07:57:42 PM PDT 24 Jul 27 08:02:44 PM PDT 24 2604089408 ps
T96 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.1640584362 Jul 27 07:52:45 PM PDT 24 Jul 27 08:13:14 PM PDT 24 7858372850 ps
T47 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2988968210 Jul 27 08:10:51 PM PDT 24 Jul 27 08:24:09 PM PDT 24 4924965700 ps
T193 /workspace/coverage/default/1.chip_sw_aon_timer_irq.841017194 Jul 27 08:02:11 PM PDT 24 Jul 27 08:10:48 PM PDT 24 4087774168 ps
T121 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.4233885428 Jul 27 07:56:18 PM PDT 24 Jul 27 08:16:01 PM PDT 24 5890178184 ps
T459 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2668937339 Jul 27 08:17:35 PM PDT 24 Jul 27 08:23:12 PM PDT 24 2994047820 ps
T211 /workspace/coverage/default/1.chip_sw_pattgen_ios.290631504 Jul 27 07:52:42 PM PDT 24 Jul 27 07:56:26 PM PDT 24 2884325920 ps
T125 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1204956177 Jul 27 07:59:21 PM PDT 24 Jul 27 08:06:33 PM PDT 24 4445874785 ps
T145 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3333442603 Jul 27 08:21:09 PM PDT 24 Jul 27 08:54:15 PM PDT 24 9048120960 ps
T123 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.3317646799 Jul 27 08:14:00 PM PDT 24 Jul 27 08:53:45 PM PDT 24 12058388240 ps
T71 /workspace/coverage/default/45.chip_sw_all_escalation_resets.2268600982 Jul 27 08:25:30 PM PDT 24 Jul 27 08:34:45 PM PDT 24 5139748296 ps
T152 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.4047609159 Jul 27 08:10:32 PM PDT 24 Jul 27 08:40:05 PM PDT 24 12466777712 ps
T5 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2333595227 Jul 27 07:54:49 PM PDT 24 Jul 28 12:03:56 AM PDT 24 77769986388 ps
T380 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1904612141 Jul 27 08:29:52 PM PDT 24 Jul 27 08:35:36 PM PDT 24 3715017324 ps
T43 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2433099814 Jul 27 08:01:23 PM PDT 24 Jul 27 09:07:18 PM PDT 24 13954529870 ps
T369 /workspace/coverage/default/69.chip_sw_all_escalation_resets.1407585142 Jul 27 08:27:45 PM PDT 24 Jul 27 08:42:45 PM PDT 24 4904005160 ps
T245 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2418288257 Jul 27 08:12:17 PM PDT 24 Jul 27 08:18:26 PM PDT 24 4141775550 ps
T6 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1676208984 Jul 27 08:09:48 PM PDT 24 Jul 27 09:19:15 PM PDT 24 13928841694 ps
T394 /workspace/coverage/default/1.chip_sw_aes_idle.1386648373 Jul 27 08:00:34 PM PDT 24 Jul 27 08:03:52 PM PDT 24 2601360290 ps
T13 /workspace/coverage/default/1.chip_sw_gpio_smoketest.515383254 Jul 27 08:08:25 PM PDT 24 Jul 27 08:11:39 PM PDT 24 2433115790 ps
T395 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2387812804 Jul 27 07:52:58 PM PDT 24 Jul 27 08:32:14 PM PDT 24 9992781596 ps
T146 /workspace/coverage/default/0.chip_sw_otbn_smoketest.483440772 Jul 27 07:54:34 PM PDT 24 Jul 27 08:09:33 PM PDT 24 5196969400 ps
T115 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1948121976 Jul 27 08:16:32 PM PDT 24 Jul 27 08:27:44 PM PDT 24 5641466052 ps
T69 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.406792522 Jul 27 07:55:47 PM PDT 24 Jul 27 08:04:03 PM PDT 24 5600517050 ps
T396 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830000774 Jul 27 08:28:55 PM PDT 24 Jul 27 08:37:49 PM PDT 24 4541330688 ps
T397 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174305160 Jul 27 08:25:31 PM PDT 24 Jul 27 08:33:38 PM PDT 24 3967168048 ps
T346 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.468472943 Jul 27 07:51:07 PM PDT 24 Jul 27 08:02:08 PM PDT 24 4218029244 ps
T327 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3381514371 Jul 27 08:27:24 PM PDT 24 Jul 27 08:34:40 PM PDT 24 4123809824 ps
T431 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1621707459 Jul 27 08:27:14 PM PDT 24 Jul 27 08:33:06 PM PDT 24 3221981160 ps
T749 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.3477836271 Jul 27 08:14:13 PM PDT 24 Jul 27 08:24:53 PM PDT 24 5010142136 ps
T217 /workspace/coverage/default/91.chip_sw_all_escalation_resets.62930847 Jul 27 08:29:37 PM PDT 24 Jul 27 08:38:07 PM PDT 24 4575882636 ps
T344 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.395808023 Jul 27 08:22:17 PM PDT 24 Jul 27 08:32:42 PM PDT 24 4151473476 ps
T206 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.417188423 Jul 27 08:09:44 PM PDT 24 Jul 27 08:13:32 PM PDT 24 2980011392 ps
T256 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1904378172 Jul 27 08:23:22 PM PDT 24 Jul 27 09:59:16 PM PDT 24 25821256864 ps
T458 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1662657262 Jul 27 07:53:17 PM PDT 24 Jul 27 08:10:46 PM PDT 24 5536315570 ps
T276 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.4137817798 Jul 27 07:53:44 PM PDT 24 Jul 27 08:00:20 PM PDT 24 9945473244 ps
T169 /workspace/coverage/default/2.rom_e2e_static_critical.3113740529 Jul 27 08:20:12 PM PDT 24 Jul 27 09:29:10 PM PDT 24 17028069124 ps
T65 /workspace/coverage/default/1.chip_sw_alert_test.841152808 Jul 27 07:59:53 PM PDT 24 Jul 27 08:04:35 PM PDT 24 2813676880 ps
T48 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3732800854 Jul 27 07:54:04 PM PDT 24 Jul 27 08:04:15 PM PDT 24 4298953650 ps
T240 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1145087368 Jul 27 07:51:47 PM PDT 24 Jul 27 08:05:09 PM PDT 24 5298060996 ps
T218 /workspace/coverage/default/75.chip_sw_all_escalation_resets.805635778 Jul 27 08:29:26 PM PDT 24 Jul 27 08:41:19 PM PDT 24 5316892210 ps
T294 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3586918822 Jul 27 08:18:17 PM PDT 24 Jul 27 08:31:00 PM PDT 24 4236989992 ps
T295 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1616162346 Jul 27 08:22:01 PM PDT 24 Jul 27 09:00:08 PM PDT 24 13136612412 ps
T296 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.22246257 Jul 27 07:50:25 PM PDT 24 Jul 27 07:55:57 PM PDT 24 3075611064 ps
T122 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1107783439 Jul 27 07:54:38 PM PDT 24 Jul 27 08:10:37 PM PDT 24 4353233528 ps
T44 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2288419866 Jul 27 08:19:03 PM PDT 24 Jul 27 08:26:38 PM PDT 24 5273704391 ps
T257 /workspace/coverage/default/96.chip_sw_all_escalation_resets.891035824 Jul 27 08:28:49 PM PDT 24 Jul 27 08:40:08 PM PDT 24 5684633360 ps
T40 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3509974600 Jul 27 08:09:21 PM PDT 24 Jul 27 10:07:23 PM PDT 24 23879954484 ps
T297 /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.1336779245 Jul 27 08:11:04 PM PDT 24 Jul 27 08:17:47 PM PDT 24 3189759942 ps
T207 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.4213107381 Jul 27 08:15:09 PM PDT 24 Jul 27 08:39:10 PM PDT 24 7605676286 ps
T118 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1149565425 Jul 27 08:18:53 PM PDT 24 Jul 27 08:44:43 PM PDT 24 8049156451 ps
T710 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1132880303 Jul 27 08:29:34 PM PDT 24 Jul 27 08:35:22 PM PDT 24 3466967750 ps
T721 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340541021 Jul 27 08:25:29 PM PDT 24 Jul 27 08:32:10 PM PDT 24 3785593880 ps
T359 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3945729210 Jul 27 08:17:30 PM PDT 24 Jul 27 08:21:11 PM PDT 24 2117559590 ps
T119 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2055602797 Jul 27 08:06:39 PM PDT 24 Jul 27 08:18:08 PM PDT 24 3560571300 ps
T219 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1129082734 Jul 27 08:17:11 PM PDT 24 Jul 27 09:30:37 PM PDT 24 14422966036 ps
T41 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.860226940 Jul 27 07:59:15 PM PDT 24 Jul 27 09:29:00 PM PDT 24 22792542556 ps
T340 /workspace/coverage/default/33.chip_sw_all_escalation_resets.3160380803 Jul 27 08:23:22 PM PDT 24 Jul 27 08:32:55 PM PDT 24 4826796100 ps
T10 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.712023566 Jul 27 08:09:21 PM PDT 24 Jul 27 08:23:08 PM PDT 24 6779399862 ps
T921 /workspace/coverage/default/1.rom_e2e_static_critical.3221673616 Jul 27 08:12:37 PM PDT 24 Jul 27 09:28:03 PM PDT 24 16654762210 ps
T922 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.61470266 Jul 27 07:52:35 PM PDT 24 Jul 27 08:02:47 PM PDT 24 4226099310 ps
T120 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.4060036819 Jul 27 08:15:07 PM PDT 24 Jul 27 08:24:02 PM PDT 24 7880267866 ps
T215 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1507264575 Jul 27 08:22:40 PM PDT 24 Jul 27 08:34:34 PM PDT 24 4551304232 ps
T212 /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3796230845 Jul 27 08:10:11 PM PDT 24 Jul 27 08:18:23 PM PDT 24 3702083216 ps
T253 /workspace/coverage/default/0.chip_sw_aon_timer_irq.2856336214 Jul 27 07:52:40 PM PDT 24 Jul 27 07:57:21 PM PDT 24 3572447786 ps
T827 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.425981766 Jul 27 08:29:19 PM PDT 24 Jul 27 08:37:08 PM PDT 24 4589650828 ps
T14 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.1456482051 Jul 27 07:54:09 PM PDT 24 Jul 27 08:03:13 PM PDT 24 3227681166 ps
T209 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.62019118 Jul 27 07:56:39 PM PDT 24 Jul 27 08:07:29 PM PDT 24 3898427960 ps
T923 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2218801361 Jul 27 08:10:32 PM PDT 24 Jul 27 08:20:34 PM PDT 24 3873398810 ps
T126 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1663618328 Jul 27 07:53:43 PM PDT 24 Jul 27 08:02:46 PM PDT 24 5053886120 ps
T924 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.4000214972 Jul 27 07:56:26 PM PDT 24 Jul 27 08:06:52 PM PDT 24 4527355670 ps
T925 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3361034778 Jul 27 08:02:59 PM PDT 24 Jul 27 08:06:04 PM PDT 24 2249375290 ps
T45 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2356719230 Jul 27 07:56:50 PM PDT 24 Jul 27 08:40:24 PM PDT 24 30315222440 ps
T754 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2399622969 Jul 27 08:28:41 PM PDT 24 Jul 27 08:35:33 PM PDT 24 4412304436 ps
T216 /workspace/coverage/default/2.chip_sw_uart_tx_rx.1455032161 Jul 27 08:09:04 PM PDT 24 Jul 27 08:19:24 PM PDT 24 4178172850 ps
T46 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3128871410 Jul 27 07:55:56 PM PDT 24 Jul 27 09:21:58 PM PDT 24 48897196472 ps
T926 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.972501906 Jul 27 07:56:05 PM PDT 24 Jul 27 08:00:54 PM PDT 24 3599268310 ps
T15 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.560223844 Jul 27 08:08:33 PM PDT 24 Jul 27 08:15:36 PM PDT 24 6251451296 ps
T18 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.30311029 Jul 27 07:54:41 PM PDT 24 Jul 27 08:28:34 PM PDT 24 22835964986 ps
T774 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2202569065 Jul 27 08:28:13 PM PDT 24 Jul 27 08:34:02 PM PDT 24 4056268600 ps
T116 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.393557539 Jul 27 08:13:41 PM PDT 24 Jul 27 08:21:50 PM PDT 24 4580047172 ps
T927 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1533773665 Jul 27 07:55:20 PM PDT 24 Jul 27 08:00:43 PM PDT 24 3160907084 ps
T183 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3702081437 Jul 27 08:20:47 PM PDT 24 Jul 27 08:39:08 PM PDT 24 9278870024 ps
T16 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1953609812 Jul 27 08:14:58 PM PDT 24 Jul 27 08:21:41 PM PDT 24 7290274760 ps
T443 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233857879 Jul 27 08:30:43 PM PDT 24 Jul 27 08:37:46 PM PDT 24 3083125272 ps
T248 /workspace/coverage/default/0.chip_sw_plic_sw_irq.349462388 Jul 27 07:53:45 PM PDT 24 Jul 27 07:58:23 PM PDT 24 3520880760 ps
T444 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2584935698 Jul 27 08:17:50 PM PDT 24 Jul 27 08:23:28 PM PDT 24 3176391822 ps
T445 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.4214541688 Jul 27 07:56:09 PM PDT 24 Jul 27 08:14:25 PM PDT 24 6334772410 ps
T162 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.421780554 Jul 27 07:55:31 PM PDT 24 Jul 27 07:57:38 PM PDT 24 2450522457 ps
T446 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1574537193 Jul 27 08:12:57 PM PDT 24 Jul 27 09:27:59 PM PDT 24 17665017800 ps
T93 /workspace/coverage/default/1.chip_sw_inject_scramble_seed.1439876060 Jul 27 07:57:35 PM PDT 24 Jul 27 11:05:52 PM PDT 24 63184749492 ps
T447 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.15916613 Jul 27 08:28:31 PM PDT 24 Jul 27 08:34:56 PM PDT 24 4360689790 ps
T377 /workspace/coverage/default/93.chip_sw_all_escalation_resets.681721865 Jul 27 08:29:42 PM PDT 24 Jul 27 08:42:49 PM PDT 24 4836845966 ps
T408 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3441506865 Jul 27 07:55:50 PM PDT 24 Jul 27 09:38:54 PM PDT 24 22878758600 ps
T75 /workspace/coverage/default/0.chip_jtag_mem_access.263899210 Jul 27 07:44:30 PM PDT 24 Jul 27 08:12:42 PM PDT 24 13846915600 ps
T190 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2163285036 Jul 27 07:56:16 PM PDT 24 Jul 27 08:07:28 PM PDT 24 5342285280 ps
T210 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.733780322 Jul 27 07:53:20 PM PDT 24 Jul 27 08:12:14 PM PDT 24 8474795458 ps
T76 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3113251375 Jul 27 07:52:46 PM PDT 24 Jul 27 08:21:01 PM PDT 24 10665936435 ps
T928 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1658723285 Jul 27 08:14:31 PM PDT 24 Jul 27 08:28:13 PM PDT 24 5331195278 ps
T816 /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3176399169 Jul 27 08:26:23 PM PDT 24 Jul 27 08:32:59 PM PDT 24 3556824540 ps
T763 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1336279941 Jul 27 08:00:47 PM PDT 24 Jul 27 08:07:14 PM PDT 24 3616803016 ps
T184 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.4003444840 Jul 27 08:24:14 PM PDT 24 Jul 27 08:33:22 PM PDT 24 6493648251 ps
T167 /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2025298083 Jul 27 07:54:31 PM PDT 24 Jul 27 08:02:32 PM PDT 24 5386439487 ps
T929 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3101629506 Jul 27 08:19:12 PM PDT 24 Jul 27 08:28:41 PM PDT 24 4435734808 ps
T930 /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.2242760011 Jul 27 08:09:37 PM PDT 24 Jul 27 08:39:59 PM PDT 24 8267915050 ps
T153 /workspace/coverage/default/2.chip_plic_all_irqs_10.1229286000 Jul 27 08:13:52 PM PDT 24 Jul 27 08:23:36 PM PDT 24 4216481930 ps
T551 /workspace/coverage/default/2.chip_sw_all_escalation_resets.84578467 Jul 27 08:14:11 PM PDT 24 Jul 27 08:24:37 PM PDT 24 5929780078 ps
T931 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.846573585 Jul 27 08:04:35 PM PDT 24 Jul 27 08:13:03 PM PDT 24 5313659928 ps
T199 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.537232397 Jul 27 07:52:08 PM PDT 24 Jul 27 11:15:19 PM PDT 24 63784462064 ps
T932 /workspace/coverage/default/1.chip_sw_aes_entropy.2744740850 Jul 27 08:07:36 PM PDT 24 Jul 27 08:11:55 PM PDT 24 2454773508 ps
T762 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.449535389 Jul 27 08:24:27 PM PDT 24 Jul 27 08:32:13 PM PDT 24 3506327864 ps
T358 /workspace/coverage/default/0.chip_sw_otbn_randomness.102484597 Jul 27 07:56:59 PM PDT 24 Jul 27 08:13:49 PM PDT 24 5918786932 ps
T213 /workspace/coverage/default/2.chip_sw_pattgen_ios.3944047226 Jul 27 08:10:01 PM PDT 24 Jul 27 08:15:18 PM PDT 24 3424046000 ps
T392 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3014798398 Jul 27 08:00:34 PM PDT 24 Jul 27 09:16:16 PM PDT 24 15074568380 ps
T341 /workspace/coverage/default/58.chip_sw_all_escalation_resets.3745142320 Jul 27 08:27:54 PM PDT 24 Jul 27 08:36:03 PM PDT 24 5130575790 ps
T933 /workspace/coverage/default/1.chip_sw_csrng_kat_test.3417766921 Jul 27 08:02:33 PM PDT 24 Jul 27 08:06:30 PM PDT 24 2714636372 ps
T934 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1536637696 Jul 27 08:05:22 PM PDT 24 Jul 27 08:16:50 PM PDT 24 4254303358 ps
T117 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1070366541 Jul 27 07:53:31 PM PDT 24 Jul 27 08:11:28 PM PDT 24 5392717758 ps
T214 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3173350918 Jul 27 07:54:22 PM PDT 24 Jul 27 08:13:51 PM PDT 24 10178730872 ps
T935 /workspace/coverage/default/1.rom_e2e_smoke.3075248618 Jul 27 08:12:12 PM PDT 24 Jul 27 09:21:48 PM PDT 24 14718412292 ps
T936 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.840998899 Jul 27 08:08:43 PM PDT 24 Jul 27 08:14:34 PM PDT 24 2839937238 ps
T201 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.294296074 Jul 27 08:11:58 PM PDT 24 Jul 27 08:23:36 PM PDT 24 4220824533 ps
T170 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1470122737 Jul 27 07:56:52 PM PDT 24 Jul 27 08:01:29 PM PDT 24 4069027640 ps
T813 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.1818667961 Jul 27 08:26:56 PM PDT 24 Jul 27 08:33:02 PM PDT 24 3535597654 ps
T328 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2923145087 Jul 27 07:57:19 PM PDT 24 Jul 27 08:14:43 PM PDT 24 5437412904 ps
T77 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3311260363 Jul 27 07:52:01 PM PDT 24 Jul 27 08:41:37 PM PDT 24 25644381517 ps
T165 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3473054082 Jul 27 08:06:38 PM PDT 24 Jul 27 08:20:10 PM PDT 24 5966471060 ps
T937 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.878417432 Jul 27 08:05:54 PM PDT 24 Jul 27 08:16:03 PM PDT 24 3586648656 ps
T938 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2980310174 Jul 27 07:55:50 PM PDT 24 Jul 27 08:06:08 PM PDT 24 3559837020 ps
T939 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4088520153 Jul 27 08:20:07 PM PDT 24 Jul 27 08:28:38 PM PDT 24 4373805123 ps
T940 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3314422847 Jul 27 07:55:16 PM PDT 24 Jul 27 07:57:59 PM PDT 24 3039423592 ps
T469 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2689040097 Jul 27 08:12:12 PM PDT 24 Jul 27 08:37:40 PM PDT 24 17427914402 ps
T941 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1454671443 Jul 27 08:11:27 PM PDT 24 Jul 27 08:24:31 PM PDT 24 6182781774 ps
T761 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3155475832 Jul 27 08:26:15 PM PDT 24 Jul 27 08:33:13 PM PDT 24 4364706552 ps
T460 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3353811376 Jul 27 07:52:24 PM PDT 24 Jul 27 07:56:19 PM PDT 24 2719676905 ps
T89 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3607446661 Jul 27 08:12:40 PM PDT 24 Jul 27 08:39:37 PM PDT 24 13181425856 ps
T769 /workspace/coverage/default/6.chip_sw_all_escalation_resets.637640804 Jul 27 08:25:13 PM PDT 24 Jul 27 08:36:17 PM PDT 24 5074712020 ps
T942 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2399812587 Jul 27 08:12:23 PM PDT 24 Jul 27 08:15:48 PM PDT 24 2860569016 ps
T750 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2533723864 Jul 27 08:28:19 PM PDT 24 Jul 27 08:34:20 PM PDT 24 4221928806 ps
T220 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.955389789 Jul 27 08:11:01 PM PDT 24 Jul 27 08:23:05 PM PDT 24 5932050536 ps
T147 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1277006676 Jul 27 07:57:01 PM PDT 24 Jul 27 09:01:48 PM PDT 24 16761922540 ps
T223 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2791797871 Jul 27 08:10:55 PM PDT 24 Jul 27 08:30:00 PM PDT 24 8032309824 ps
T713 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1393086472 Jul 27 08:24:41 PM PDT 24 Jul 27 08:31:31 PM PDT 24 3261641320 ps
T851 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2496887032 Jul 27 08:25:56 PM PDT 24 Jul 27 08:30:49 PM PDT 24 3785372880 ps
T753 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.1506426872 Jul 27 07:53:56 PM PDT 24 Jul 27 08:03:17 PM PDT 24 6386987464 ps
T78 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.4111246665 Jul 27 07:57:26 PM PDT 24 Jul 27 08:06:56 PM PDT 24 5551121142 ps
T22 /workspace/coverage/default/2.chip_sw_gpio.3173607169 Jul 27 08:09:17 PM PDT 24 Jul 27 08:17:55 PM PDT 24 4626967412 ps
T164 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2722711749 Jul 27 07:53:46 PM PDT 24 Jul 27 09:37:46 PM PDT 24 47809993550 ps
T943 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.981649990 Jul 27 08:10:05 PM PDT 24 Jul 27 08:31:31 PM PDT 24 5348198053 ps
T944 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.803414255 Jul 27 07:53:30 PM PDT 24 Jul 27 08:01:14 PM PDT 24 5682621328 ps
T945 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.67492708 Jul 27 07:53:51 PM PDT 24 Jul 27 08:02:17 PM PDT 24 3048241552 ps
T722 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3158506547 Jul 27 07:59:22 PM PDT 24 Jul 27 08:25:28 PM PDT 24 10332948835 ps
T946 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.4066179113 Jul 27 08:10:56 PM PDT 24 Jul 27 08:28:29 PM PDT 24 5193507712 ps
T371 /workspace/coverage/default/37.chip_sw_all_escalation_resets.3928309604 Jul 27 08:24:02 PM PDT 24 Jul 27 08:36:04 PM PDT 24 4742519288 ps
T947 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2075097247 Jul 27 07:57:37 PM PDT 24 Jul 27 08:12:54 PM PDT 24 5181340890 ps
T179 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3236029912 Jul 27 08:12:17 PM PDT 24 Jul 27 08:26:15 PM PDT 24 6714793640 ps
T853 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1960836844 Jul 27 08:24:48 PM PDT 24 Jul 27 08:31:51 PM PDT 24 3601605558 ps
T171 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4289141452 Jul 27 07:53:02 PM PDT 24 Jul 27 07:58:26 PM PDT 24 3117451942 ps
T381 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.321863581 Jul 27 07:55:44 PM PDT 24 Jul 27 08:00:49 PM PDT 24 3146204856 ps
T139 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1050386766 Jul 27 08:06:52 PM PDT 24 Jul 27 08:15:33 PM PDT 24 6421855196 ps
T860 /workspace/coverage/default/17.chip_sw_all_escalation_resets.2734905771 Jul 27 08:23:19 PM PDT 24 Jul 27 08:34:12 PM PDT 24 5245975552 ps
T382 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2807687383 Jul 27 07:58:19 PM PDT 24 Jul 27 08:22:23 PM PDT 24 10173537139 ps
T393 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2504659545 Jul 27 07:58:02 PM PDT 24 Jul 27 09:04:10 PM PDT 24 15749277230 ps
T110 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2795144638 Jul 27 07:58:53 PM PDT 24 Jul 27 08:50:17 PM PDT 24 20236964978 ps
T736 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.502343261 Jul 27 07:54:22 PM PDT 24 Jul 27 07:58:37 PM PDT 24 3243889688 ps
T113 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2842282575 Jul 27 08:16:45 PM PDT 24 Jul 27 08:56:44 PM PDT 24 12340093260 ps
T241 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.4089177382 Jul 27 07:55:37 PM PDT 24 Jul 27 08:08:03 PM PDT 24 4847043594 ps
T280 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1387047945 Jul 27 07:53:21 PM PDT 24 Jul 27 08:52:56 PM PDT 24 34223450863 ps
T281 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2024929179 Jul 27 08:06:57 PM PDT 24 Jul 27 08:13:47 PM PDT 24 3260598738 ps
T282 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.4018484543 Jul 27 07:53:22 PM PDT 24 Jul 27 07:58:48 PM PDT 24 3269796250 ps
T259 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.685006764 Jul 27 08:30:43 PM PDT 24 Jul 27 08:39:17 PM PDT 24 4112064584 ps
T283 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2911693045 Jul 27 07:58:54 PM PDT 24 Jul 27 08:02:39 PM PDT 24 2652671368 ps
T168 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1941542900 Jul 27 07:55:38 PM PDT 24 Jul 27 08:03:10 PM PDT 24 4731705910 ps
T284 /workspace/coverage/default/0.chip_tap_straps_dev.1844490973 Jul 27 07:57:02 PM PDT 24 Jul 27 07:59:44 PM PDT 24 2646122884 ps
T285 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3445246335 Jul 27 08:08:00 PM PDT 24 Jul 27 08:11:57 PM PDT 24 3133911474 ps
T286 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.290459915 Jul 27 08:09:39 PM PDT 24 Jul 27 08:29:05 PM PDT 24 5718082096 ps
T948 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1385887310 Jul 27 07:58:14 PM PDT 24 Jul 27 09:14:44 PM PDT 24 15729143030 ps
T949 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2573665515 Jul 27 08:04:02 PM PDT 24 Jul 27 09:07:24 PM PDT 24 15755523040 ps
T756 /workspace/coverage/default/2.rom_e2e_self_hash.1934443380 Jul 27 08:21:51 PM PDT 24 Jul 27 10:03:47 PM PDT 24 26076524392 ps
T156 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2965275725 Jul 27 08:14:29 PM PDT 24 Jul 27 11:25:55 PM PDT 24 254412443130 ps
T950 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1885891730 Jul 27 08:18:06 PM PDT 24 Jul 27 08:24:00 PM PDT 24 2950692552 ps
T173 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2010918145 Jul 27 07:52:26 PM PDT 24 Jul 27 08:03:20 PM PDT 24 4801593180 ps
T951 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.450556442 Jul 27 07:52:43 PM PDT 24 Jul 27 08:01:15 PM PDT 24 3958177686 ps
T952 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1080158727 Jul 27 07:55:21 PM PDT 24 Jul 27 08:15:17 PM PDT 24 12669876495 ps
T366 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.1183901893 Jul 27 08:09:52 PM PDT 24 Jul 27 08:21:03 PM PDT 24 4255110148 ps
T757 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1758500863 Jul 27 08:08:41 PM PDT 24 Jul 27 08:14:29 PM PDT 24 3358041918 ps
T367 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1671766967 Jul 27 08:07:50 PM PDT 24 Jul 27 08:12:44 PM PDT 24 3806220999 ps
T737 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3242567497 Jul 27 07:58:18 PM PDT 24 Jul 27 08:02:42 PM PDT 24 3235327580 ps
T953 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.2019257610 Jul 27 08:19:32 PM PDT 24 Jul 27 08:23:42 PM PDT 24 2817172556 ps
T954 /workspace/coverage/default/2.chip_sw_hmac_oneshot.2458097451 Jul 27 08:12:40 PM PDT 24 Jul 27 08:18:18 PM PDT 24 2710647400 ps
T955 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3450475643 Jul 27 08:03:26 PM PDT 24 Jul 27 08:59:06 PM PDT 24 12219719660 ps
T956 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2328806942 Jul 27 08:22:39 PM PDT 24 Jul 27 08:31:39 PM PDT 24 5809145811 ps
T11 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1758413643 Jul 27 07:53:05 PM PDT 24 Jul 27 08:01:02 PM PDT 24 4121927248 ps
T49 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2659008167 Jul 27 07:56:26 PM PDT 24 Jul 27 08:04:35 PM PDT 24 8277146280 ps
T208 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.80487881 Jul 27 08:01:06 PM PDT 24 Jul 27 08:30:29 PM PDT 24 7733147158 ps
T356 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1686327624 Jul 27 07:56:42 PM PDT 24 Jul 27 08:06:03 PM PDT 24 4508625448 ps
T957 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.3263776884 Jul 27 08:04:26 PM PDT 24 Jul 27 08:13:33 PM PDT 24 7425551079 ps
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T221 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2987732390 Jul 27 08:15:54 PM PDT 24 Jul 27 08:41:18 PM PDT 24 9251696336 ps
T266 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2037488656 Jul 27 08:07:56 PM PDT 24 Jul 27 08:12:51 PM PDT 24 3633787484 ps
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T268 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1315022409 Jul 27 08:29:17 PM PDT 24 Jul 27 08:40:57 PM PDT 24 6147286040 ps
T269 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3539132354 Jul 27 07:56:09 PM PDT 24 Jul 27 07:59:52 PM PDT 24 3415143216 ps
T270 /workspace/coverage/default/0.chip_sw_kmac_smoketest.244778656 Jul 27 07:55:03 PM PDT 24 Jul 27 07:59:33 PM PDT 24 2684073056 ps
T271 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3195281788 Jul 27 08:13:10 PM PDT 24 Jul 27 09:20:34 PM PDT 24 15228978047 ps
T160 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.1622886385 Jul 27 07:54:19 PM PDT 24 Jul 27 07:57:41 PM PDT 24 2618022868 ps
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T964 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.490390004 Jul 27 08:05:44 PM PDT 24 Jul 27 08:18:10 PM PDT 24 9264990896 ps
T360 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3099215871 Jul 27 07:55:31 PM PDT 24 Jul 27 08:02:46 PM PDT 24 3703489728 ps
T92 /workspace/coverage/default/0.chip_sw_usbdev_vbus.3306219885 Jul 27 07:55:34 PM PDT 24 Jul 27 08:01:07 PM PDT 24 3085346174 ps
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