Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150427	1			T85	630		T87	115		T124	630
values[2]	11204	1			T85	99		T87	4		T124	1
values[3]	4265	1			T85	64		T554	1		T552	4
values[4]	2458	1			T85	49		T554	1		T552	5
values[5]	1555	1			T85	31		T554	1		T552	10
values[6]	1059	1			T85	17		T554	1		T552	3
values[7]	891	1			T85	22		T554	1		T552	2
values[8]	638	1			T85	23		T554	1		T552	2
values[9]	534	1			T85	29		T554	1		T552	2
values[10]	513	1			T85	13		T554	1		T552	2
values[11]	390	1			T85	11		T554	1		T552	4
values[12]	387	1			T85	9		T554	1		T552	7
values[13]	378	1			T85	7		T554	1		T552	15
values[14]	369	1			T85	5		T554	1		T552	9
values[15]	342	1			T85	15		T554	1		T552	13
values[16]	306	1			T85	22		T554	1		T552	2
values[17]	304	1			T85	5		T554	1		T552	4
values[18]	344	1			T85	6		T554	1		T552	3
values[19]	317	1			T85	5		T554	1		T552	5
values[20]	313	1			T85	6		T554	1		T552	5
values[21]	360	1			T85	13		T554	1		T552	2
values[22]	267	1			T85	6		T554	1		T552	3
values[23]	339	1			T85	15		T554	1		T552	2
values[24]	307	1			T85	7		T554	1		T552	4
values[25]	323	1			T85	6		T554	1		T552	4
values[26]	386	1			T85	4		T554	1		T552	2
values[27]	325	1			T85	18		T554	1		T552	2
values[28]	255	1			T85	10		T554	1		T552	1
values[29]	315	1			T85	10		T554	1		T552	5
values[30]	312	1			T85	8		T554	1		T552	9
values[31]	300	1			T85	5		T554	1		T552	10
values[32]	310	1			T85	3		T554	1		T552	4
values[33]	269	1			T85	5		T554	1		T552	1
values[34]	276	1			T85	3		T554	1		T552	2
values[35]	286	1			T85	9		T554	1		T552	1
values[36]	340	1			T85	7		T554	1		T552	4
values[37]	265	1			T85	6		T554	1		T552	3
values[38]	297	1			T85	9		T554	1		T552	1
values[39]	295	1			T85	7		T554	1		T552	3
values[40]	305	1			T85	14		T554	1		T552	1
values[41]	292	1			T85	3		T554	1		T552	1
values[42]	302	1			T85	8		T554	1		T552	3
values[43]	256	1			T85	7		T554	1		T552	2
values[44]	282	1			T85	5		T554	2		T552	7
values[45]	281	1			T85	10		T554	1		T552	8
values[46]	250	1			T85	15		T554	1		T552	2
values[47]	264	1			T85	7		T554	1		T552	1
values[48]	297	1			T85	6		T554	1		T552	2
values[49]	289	1			T85	5		T554	1		T552	1
values[50]	262	1			T85	9		T554	1		T552	1
values[51]	224	1			T85	9		T554	1		T552	4
values[52]	212	1			T85	4		T554	1		T552	2
values[53]	212	1			T85	2		T554	1		T552	5
values[54]	216	1			T85	4		T554	1		T552	2
values[55]	211	1			T85	7		T554	1		T552	1
values[56]	174	1			T85	6		T554	1		T552	4
values[57]	214	1			T85	13		T554	1		T552	2
values[58]	222	1			T85	9		T554	1		T552	1
values[59]	209	1			T85	6		T554	1		T552	3
values[60]	210	1			T85	6		T554	1		T552	4
values[61]	248	1			T85	13		T554	1		T552	6
values[62]	219	1			T85	19		T554	1		T552	2
values[63]	186	1			T85	9		T554	1		T552	1
values[64]	185	1			T85	3		T554	1		T552	5
values[65]	162	1			T85	3		T554	1		T552	2
values[66]	158	1			T85	7		T554	2		T552	1
values[67]	175	1			T85	4		T554	1		T552	3
values[68]	132	1			T554	1		T552	2		T489	5
values[69]	141	1			T554	1		T552	3		T489	3
values[70]	163	1			T554	1		T552	2		T489	10
values[71]	140	1			T554	1		T552	2		T489	13
values[72]	149	1			T554	1		T552	2		T489	10
values[73]	130	1			T554	1		T552	6		T489	13
values[74]	121	1			T554	1		T552	2		T489	3
values[75]	119	1			T554	1		T552	1		T883	1
values[76]	122	1			T554	1		T552	5		T883	1
values[77]	109	1			T554	1		T552	8		T883	1
values[78]	121	1			T554	1		T552	8		T883	1
values[79]	95	1			T554	1		T552	4		T883	1
values[80]	84	1			T554	1		T552	1		T883	2
values[81]	100	1			T554	1		T552	2		T883	1
values[82]	89	1			T554	1		T552	4		T883	1
values[83]	72	1			T554	1		T552	4		T883	1
values[84]	88	1			T554	1		T552	3		T883	1
values[85]	78	1			T554	1		T552	3		T883	1
values[86]	89	1			T554	1		T552	6		T883	1
values[87]	86	1			T554	1		T552	9		T883	1
values[88]	82	1			T554	1		T552	3		T883	1
values[89]	76	1			T554	1		T552	3		T883	1
values[90]	89	1			T554	1		T552	4		T883	1
values[91]	91	1			T554	1		T552	1		T883	1
values[92]	99	1			T554	1		T552	7		T883	1
values[93]	67	1			T554	1		T552	5		T883	1
values[94]	91	1			T554	1		T552	4		T883	1
values[95]	91	1			T554	1		T552	5		T883	1
values[96]	88	1			T554	1		T552	2		T883	1
values[97]	94	1			T554	3		T552	3		T883	1
values[98]	104	1			T554	1		T552	5		T883	1
values[99]	84	1			T554	2		T552	4		T883	1
values[100]	81	1			T554	2		T552	3		T883	1
values[101]	84	1			T554	2		T552	4		T883	1
values[102]	83	1			T554	1		T552	5		T883	1
values[103]	82	1			T554	10		T552	2		T883	1
values[104]	88	1			T554	1		T552	2		T883	2
values[105]	81	1			T554	1		T552	2		T883	6
values[106]	86	1			T554	1		T552	2		T883	1
values[107]	76	1			T554	2		T552	2		T883	2
values[108]	63	1			T554	1		T552	1		T883	1
values[109]	78	1			T554	1		T552	4		T883	4
values[110]	96	1			T554	7		T552	4		T883	2
values[111]	74	1			T554	1		T552	4		T883	2
values[112]	85	1			T554	2		T552	3		T883	1
values[113]	94	1			T554	3		T552	6		T883	2
values[114]	94	1			T554	1		T552	5		T883	3
values[115]	84	1			T554	3		T552	5		T883	3
values[116]	82	1			T554	1		T552	4		T883	2
values[117]	79	1			T554	1		T552	3		T883	2
values[118]	74	1			T554	2		T552	8		T883	2
values[119]	81	1			T554	3		T552	11		T883	1
values[120]	91	1			T554	1		T552	11		T883	8
values[121]	73	1			T554	1		T552	3		T883	2
values[122]	86	1			T554	1		T552	5		T883	2
values[123]	84	1			T554	1		T552	13		T883	1
values[124]	83	1			T554	2		T552	10		T883	1
values[125]	79	1			T554	2		T552	6		T883	3
values[126]	161	1			T554	1		T552	1		T883	3
values[127]	1022	1			T554	30		T883	36		T520	97
values[128]	8342	1			T554	258		T883	311		T520	862