Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.otp_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151051	1			T85	440		T86	1		T87	102
values[2]	10494	1			T85	8		T86	1		T87	1
values[3]	3883	1			T85	4		T86	1		T552	33
values[4]	2257	1			T85	12		T86	1		T552	29
values[5]	1448	1			T85	6		T86	1		T552	22
values[6]	904	1			T85	5		T86	1		T552	15
values[7]	684	1			T85	4		T86	1		T552	15
values[8]	555	1			T85	9		T86	1		T552	14
values[9]	500	1			T85	5		T86	1		T552	10
values[10]	440	1			T85	4		T86	1		T552	10
values[11]	362	1			T85	5		T86	1		T552	3
values[12]	310	1			T85	7		T86	1		T552	7
values[13]	276	1			T85	5		T86	1		T552	7
values[14]	282	1			T85	17		T86	1		T552	9
values[15]	294	1			T85	10		T86	1		T552	6
values[16]	296	1			T85	5		T86	1		T552	7
values[17]	286	1			T85	12		T86	1		T552	5
values[18]	276	1			T85	8		T86	1		T552	4
values[19]	271	1			T85	14		T86	1		T552	4
values[20]	264	1			T85	10		T86	1		T552	2
values[21]	285	1			T85	6		T86	1		T552	3
values[22]	310	1			T85	6		T86	1		T552	2
values[23]	267	1			T85	5		T86	1		T552	1
values[24]	248	1			T85	4		T86	1		T552	2
values[25]	276	1			T85	4		T86	1		T552	4
values[26]	333	1			T85	4		T86	1		T552	2
values[27]	276	1			T85	8		T86	1		T552	1
values[28]	267	1			T85	11		T86	1		T552	4
values[29]	243	1			T85	3		T86	1		T552	2
values[30]	238	1			T85	3		T86	1		T552	7
values[31]	207	1			T85	7		T86	1		T552	1
values[32]	246	1			T85	13		T86	1		T552	2
values[33]	236	1			T85	11		T86	1		T552	2
values[34]	279	1			T85	17		T86	1		T552	1
values[35]	261	1			T85	7		T86	1		T552	4
values[36]	249	1			T85	14		T86	1		T552	3
values[37]	244	1			T85	3		T86	1		T552	2
values[38]	256	1			T85	6		T86	1		T552	6
values[39]	273	1			T85	6		T86	1		T552	4
values[40]	224	1			T85	5		T86	1		T552	1
values[41]	249	1			T85	6		T86	1		T552	2
values[42]	238	1			T85	12		T86	1		T552	3
values[43]	237	1			T85	4		T86	1		T552	1
values[44]	200	1			T85	10		T86	1		T552	1
values[45]	275	1			T85	14		T86	1		T552	1
values[46]	250	1			T85	10		T86	1		T552	1
values[47]	262	1			T85	11		T86	1		T552	3
values[48]	259	1			T85	7		T86	1		T552	3
values[49]	253	1			T85	7		T86	1		T552	3
values[50]	298	1			T85	4		T86	1		T552	1
values[51]	260	1			T85	6		T86	1		T552	1
values[52]	211	1			T85	4		T86	1		T552	2
values[53]	199	1			T85	4		T86	1		T552	4
values[54]	216	1			T85	3		T86	1		T552	5
values[55]	225	1			T85	7		T86	1		T552	5
values[56]	255	1			T85	7		T86	1		T552	1
values[57]	257	1			T85	15		T86	1		T552	1
values[58]	234	1			T85	12		T86	1		T552	4
values[59]	211	1			T85	8		T86	1		T552	1
values[60]	208	1			T85	8		T86	1		T552	2
values[61]	192	1			T85	11		T86	1		T552	1
values[62]	190	1			T85	9		T86	1		T552	7
values[63]	207	1			T85	14		T86	1		T552	6
values[64]	168	1			T86	1		T552	9		T872	1
values[65]	146	1			T86	1		T552	5		T872	1
values[66]	127	1			T86	1		T552	1		T872	1
values[67]	165	1			T86	1		T552	2		T872	1
values[68]	135	1			T86	1		T552	1		T872	1
values[69]	144	1			T86	1		T552	1		T872	1
values[70]	175	1			T86	1		T552	6		T872	1
values[71]	184	1			T86	1		T552	3		T872	1
values[72]	138	1			T86	1		T552	5		T872	1
values[73]	167	1			T86	1		T552	7		T872	1
values[74]	153	1			T86	1		T552	9		T872	1
values[75]	120	1			T86	1		T552	12		T872	1
values[76]	123	1			T86	1		T552	7		T872	1
values[77]	126	1			T86	1		T552	2		T872	1
values[78]	104	1			T86	1		T552	7		T872	1
values[79]	111	1			T86	1		T552	9		T872	1
values[80]	104	1			T86	1		T552	8		T872	1
values[81]	100	1			T86	1		T552	6		T872	1
values[82]	107	1			T86	1		T552	6		T872	1
values[83]	109	1			T86	1		T552	5		T872	1
values[84]	97	1			T86	1		T552	9		T872	1
values[85]	102	1			T86	2		T552	4		T872	1
values[86]	98	1			T86	1		T552	6		T872	1
values[87]	103	1			T86	1		T552	3		T872	1
values[88]	113	1			T86	1		T552	1		T872	1
values[89]	108	1			T86	1		T552	4		T872	1
values[90]	98	1			T86	1		T552	6		T872	1
values[91]	102	1			T86	1		T552	5		T872	1
values[92]	93	1			T86	1		T552	8		T872	1
values[93]	81	1			T86	1		T552	7		T872	1
values[94]	132	1			T86	1		T552	4		T872	1
values[95]	103	1			T86	1		T552	10		T872	1
values[96]	114	1			T86	1		T552	5		T872	1
values[97]	98	1			T86	1		T552	3		T872	1
values[98]	88	1			T86	1		T552	4		T872	1
values[99]	100	1			T86	1		T552	5		T872	1
values[100]	88	1			T86	1		T552	5		T872	1
values[101]	112	1			T86	1		T552	10		T872	1
values[102]	101	1			T86	1		T552	10		T872	2
values[103]	89	1			T86	1		T552	7		T872	1
values[104]	85	1			T86	1		T552	2		T872	1
values[105]	85	1			T86	1		T552	2		T872	1
values[106]	85	1			T86	1		T552	2		T872	1
values[107]	76	1			T86	2		T552	6		T872	1
values[108]	91	1			T86	2		T552	2		T872	1
values[109]	90	1			T86	1		T552	3		T872	1
values[110]	79	1			T86	1		T552	3		T872	1
values[111]	66	1			T86	1		T552	1		T872	3
values[112]	68	1			T86	1		T552	4		T872	3
values[113]	96	1			T86	6		T552	6		T872	5
values[114]	83	1			T86	2		T552	3		T872	2
values[115]	78	1			T86	6		T552	2		T872	1
values[116]	61	1			T86	1		T552	2		T872	1
values[117]	88	1			T86	2		T552	4		T872	4
values[118]	72	1			T86	1		T552	3		T872	1
values[119]	82	1			T86	4		T552	4		T872	2
values[120]	77	1			T86	1		T552	2		T872	6
values[121]	72	1			T86	3		T552	4		T872	1
values[122]	79	1			T86	1		T552	1		T872	3
values[123]	73	1			T86	1		T552	3		T872	4
values[124]	91	1			T86	1		T552	7		T872	1
values[125]	94	1			T86	1		T552	4		T872	1
values[126]	138	1			T86	1		T552	5		T872	4
values[127]	916	1			T86	42		T552	9		T872	41
values[128]	7747	1			T86	330		T552	10		T872	377