Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.pwrmgr_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150693	1			T85	708		T87	101		T124	1044
values[2]	10661	1			T85	86		T87	5		T124	34
values[3]	3864	1			T85	45		T124	5		T554	1
values[4]	2206	1			T85	8		T554	1		T716	5
values[5]	1293	1			T85	10		T554	1		T716	6
values[6]	1009	1			T85	11		T554	1		T716	11
values[7]	689	1			T85	7		T554	1		T716	5
values[8]	465	1			T85	7		T554	1		T716	12
values[9]	354	1			T85	6		T554	1		T716	6
values[10]	370	1			T85	6		T554	1		T716	3
values[11]	321	1			T85	3		T554	1		T716	9
values[12]	289	1			T554	1		T716	7		T863	3
values[13]	286	1			T554	1		T716	7		T863	1
values[14]	316	1			T554	1		T716	6		T863	1
values[15]	271	1			T554	1		T716	5		T863	1
values[16]	305	1			T554	1		T716	16		T863	1
values[17]	308	1			T554	1		T716	9		T863	1
values[18]	311	1			T554	1		T716	4		T863	1
values[19]	266	1			T554	2		T716	3		T863	1
values[20]	262	1			T554	1		T716	9		T863	1
values[21]	291	1			T554	1		T716	7		T863	1
values[22]	249	1			T554	1		T716	10		T863	1
values[23]	232	1			T554	1		T716	11		T863	1
values[24]	249	1			T554	1		T716	7		T863	1
values[25]	211	1			T554	1		T716	3		T863	1
values[26]	256	1			T554	1		T716	5		T863	1
values[27]	262	1			T554	1		T716	5		T863	1
values[28]	245	1			T554	1		T716	3		T863	1
values[29]	292	1			T554	1		T716	5		T863	1
values[30]	255	1			T554	1		T716	19		T863	1
values[31]	233	1			T554	1		T716	14		T863	1
values[32]	245	1			T554	1		T716	10		T863	1
values[33]	221	1			T554	1		T716	7		T863	1
values[34]	215	1			T554	1		T716	10		T863	1
values[35]	261	1			T554	1		T716	3		T863	1
values[36]	224	1			T554	1		T716	6		T863	1
values[37]	223	1			T554	1		T716	4		T863	1
values[38]	222	1			T554	1		T716	3		T863	1
values[39]	223	1			T554	1		T716	5		T863	1
values[40]	211	1			T554	1		T716	5		T863	1
values[41]	202	1			T554	1		T716	4		T863	1
values[42]	239	1			T554	1		T716	5		T863	1
values[43]	246	1			T554	1		T716	2		T863	1
values[44]	222	1			T554	1		T716	12		T863	1
values[45]	216	1			T554	1		T716	15		T863	1
values[46]	169	1			T554	1		T716	10		T863	1
values[47]	208	1			T554	1		T716	9		T863	1
values[48]	231	1			T554	1		T716	11		T863	1
values[49]	189	1			T554	1		T716	5		T863	1
values[50]	173	1			T554	1		T716	5		T863	1
values[51]	205	1			T554	1		T716	3		T863	1
values[52]	181	1			T554	1		T716	5		T863	1
values[53]	182	1			T554	1		T716	11		T863	1
values[54]	198	1			T554	1		T716	11		T863	1
values[55]	183	1			T554	1		T716	7		T863	1
values[56]	177	1			T554	1		T716	7		T863	1
values[57]	164	1			T554	1		T716	14		T863	1
values[58]	166	1			T554	1		T716	6		T863	1
values[59]	174	1			T554	1		T863	1		T514	1
values[60]	175	1			T554	1		T863	1		T514	1
values[61]	143	1			T554	1		T863	1		T514	1
values[62]	133	1			T554	1		T863	1		T514	1
values[63]	169	1			T554	1		T863	1		T514	1
values[64]	190	1			T554	1		T863	1		T514	1
values[65]	192	1			T554	1		T863	1		T514	1
values[66]	169	1			T554	1		T863	1		T514	1
values[67]	162	1			T554	1		T863	1		T514	1
values[68]	147	1			T554	1		T863	1		T514	1
values[69]	168	1			T554	1		T863	1		T514	1
values[70]	146	1			T554	1		T863	1		T514	1
values[71]	117	1			T554	1		T863	1		T514	1
values[72]	114	1			T554	1		T863	1		T514	1
values[73]	107	1			T554	1		T863	1		T514	1
values[74]	95	1			T554	1		T863	1		T514	1
values[75]	116	1			T554	1		T863	1		T514	1
values[76]	123	1			T554	1		T863	1		T514	1
values[77]	113	1			T554	1		T863	1		T514	1
values[78]	105	1			T554	1		T863	1		T514	1
values[79]	116	1			T554	1		T863	1		T514	1
values[80]	119	1			T554	1		T863	1		T514	1
values[81]	113	1			T554	1		T863	1		T514	1
values[82]	151	1			T554	1		T863	1		T514	1
values[83]	143	1			T554	1		T863	1		T514	1
values[84]	103	1			T554	1		T863	1		T514	1
values[85]	121	1			T554	1		T863	1		T514	1
values[86]	141	1			T554	1		T863	1		T514	1
values[87]	102	1			T554	1		T863	1		T514	1
values[88]	96	1			T554	1		T863	1		T514	1
values[89]	103	1			T554	1		T863	1		T514	1
values[90]	116	1			T554	1		T863	1		T514	1
values[91]	99	1			T554	1		T863	1		T514	1
values[92]	88	1			T554	1		T863	1		T514	1
values[93]	85	1			T554	1		T863	1		T514	1
values[94]	85	1			T554	1		T863	1		T514	1
values[95]	76	1			T554	1		T863	1		T514	1
values[96]	70	1			T554	1		T863	1		T514	1
values[97]	60	1			T554	1		T863	2		T514	1
values[98]	59	1			T554	1		T863	1		T514	1
values[99]	69	1			T554	1		T863	1		T514	1
values[100]	72	1			T554	1		T863	1		T514	1
values[101]	77	1			T554	1		T863	1		T514	1
values[102]	66	1			T554	1		T863	1		T514	1
values[103]	76	1			T554	1		T863	1		T514	1
values[104]	68	1			T554	1		T863	1		T514	1
values[105]	69	1			T554	1		T863	1		T514	1
values[106]	66	1			T554	1		T863	1		T514	1
values[107]	70	1			T554	1		T863	1		T514	1
values[108]	63	1			T554	1		T863	1		T514	1
values[109]	68	1			T554	1		T863	1		T514	1
values[110]	63	1			T554	1		T863	1		T514	1
values[111]	59	1			T554	1		T863	1		T514	1
values[112]	74	1			T554	1		T863	1		T514	1
values[113]	84	1			T554	1		T863	1		T514	2
values[114]	82	1			T554	1		T863	1		T514	2
values[115]	53	1			T554	1		T863	1		T514	3
values[116]	61	1			T554	1		T863	1		T514	1
values[117]	71	1			T554	1		T863	1		T514	1
values[118]	83	1			T554	1		T863	1		T514	1
values[119]	70	1			T554	1		T863	1		T514	2
values[120]	62	1			T554	1		T863	1		T514	1
values[121]	62	1			T554	2		T863	1		T514	1
values[122]	91	1			T554	1		T863	1		T514	2
values[123]	65	1			T554	4		T863	1		T514	3
values[124]	54	1			T554	5		T863	1		T514	1
values[125]	52	1			T554	2		T863	1		T514	2
values[126]	68	1			T554	2		T863	4		T514	2
values[127]	729	1			T554	42		T863	26		T514	46
values[128]	6873	1			T554	287		T863	431		T514	391