Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	150230	1			T85	390		T87	89		T124	687
values[2]	10452	1			T85	24		T87	2		T124	2
values[3]	4085	1			T85	21		T554	1		T494	1
values[4]	2538	1			T85	12		T554	1		T489	5
values[5]	1782	1			T85	21		T554	1		T489	13
values[6]	1256	1			T85	10		T554	1		T489	9
values[7]	819	1			T85	9		T554	1		T489	6
values[8]	618	1			T85	13		T554	1		T489	6
values[9]	544	1			T85	17		T554	1		T489	17
values[10]	447	1			T85	22		T554	1		T489	4
values[11]	425	1			T85	17		T554	1		T489	6
values[12]	438	1			T85	13		T554	1		T489	5
values[13]	439	1			T85	13		T554	1		T489	4
values[14]	482	1			T85	14		T554	1		T489	13
values[15]	403	1			T85	12		T554	1		T489	9
values[16]	400	1			T85	15		T554	1		T489	6
values[17]	405	1			T85	17		T554	1		T489	8
values[18]	419	1			T85	16		T554	1		T489	9
values[19]	386	1			T85	20		T554	1		T489	6
values[20]	365	1			T85	22		T554	1		T489	8
values[21]	363	1			T85	17		T554	1		T489	5
values[22]	340	1			T85	13		T554	1		T489	3
values[23]	383	1			T85	20		T554	1		T489	5
values[24]	377	1			T85	9		T554	1		T489	5
values[25]	354	1			T85	25		T554	1		T489	5
values[26]	371	1			T85	16		T554	1		T489	10
values[27]	375	1			T85	15		T554	1		T489	6
values[28]	360	1			T85	9		T554	1		T489	9
values[29]	406	1			T85	13		T554	1		T489	9
values[30]	380	1			T85	22		T554	1		T489	15
values[31]	378	1			T85	14		T554	1		T489	12
values[32]	376	1			T85	31		T554	1		T489	3
values[33]	373	1			T85	13		T554	1		T489	11
values[34]	338	1			T85	18		T554	1		T489	4
values[35]	337	1			T85	22		T554	1		T489	5
values[36]	373	1			T85	12		T554	1		T489	7
values[37]	354	1			T85	13		T554	1		T489	3
values[38]	372	1			T85	29		T554	1		T489	5
values[39]	329	1			T85	9		T554	1		T489	10
values[40]	343	1			T85	12		T554	1		T489	5
values[41]	380	1			T85	9		T554	1		T489	18
values[42]	352	1			T85	8		T554	1		T489	25
values[43]	326	1			T85	13		T554	1		T489	9
values[44]	316	1			T85	15		T554	1		T489	5
values[45]	342	1			T85	10		T554	1		T489	8
values[46]	294	1			T85	12		T554	1		T489	8
values[47]	312	1			T85	11		T554	1		T489	4
values[48]	263	1			T85	14		T554	1		T489	4
values[49]	286	1			T85	17		T554	1		T489	8
values[50]	274	1			T85	11		T554	1		T489	4
values[51]	257	1			T85	10		T554	1		T489	8
values[52]	243	1			T85	12		T554	1		T489	3
values[53]	289	1			T85	9		T554	1		T489	11
values[54]	255	1			T85	14		T554	1		T489	8
values[55]	267	1			T85	10		T554	1		T489	9
values[56]	250	1			T85	16		T554	1		T489	10
values[57]	247	1			T85	24		T554	1		T489	4
values[58]	272	1			T85	6		T554	1		T489	9
values[59]	233	1			T85	11		T554	1		T489	7
values[60]	244	1			T85	11		T554	1		T489	9
values[61]	197	1			T85	4		T554	1		T489	7
values[62]	203	1			T85	4		T554	1		T489	4
values[63]	245	1			T85	11		T554	1		T489	3
values[64]	276	1			T85	4		T554	1		T480	1
values[65]	220	1			T554	1		T480	2		T716	3
values[66]	225	1			T554	1		T480	3		T716	3
values[67]	191	1			T554	1		T480	3		T716	6
values[68]	191	1			T554	1		T480	1		T716	4
values[69]	146	1			T554	1		T480	2		T880	18
values[70]	139	1			T554	1		T480	3		T880	5
values[71]	182	1			T554	1		T480	9		T880	10
values[72]	161	1			T554	1		T480	6		T880	18
values[73]	143	1			T554	1		T480	8		T880	9
values[74]	131	1			T554	1		T480	1		T880	8
values[75]	124	1			T554	1		T480	5		T880	11
values[76]	91	1			T554	1		T480	5		T880	7
values[77]	93	1			T554	1		T480	3		T470	4
values[78]	79	1			T554	1		T480	1		T470	6
values[79]	83	1			T554	1		T480	2		T470	5
values[80]	85	1			T554	1		T480	2		T470	4
values[81]	95	1			T554	2		T480	2		T470	8
values[82]	96	1			T554	4		T480	1		T470	16
values[83]	108	1			T554	2		T480	2		T470	3
values[84]	107	1			T554	5		T480	7		T470	3
values[85]	105	1			T554	12		T480	2		T470	5
values[86]	92	1			T554	3		T480	1		T470	6
values[87]	100	1			T554	5		T480	2		T470	5
values[88]	77	1			T554	9		T480	4		T470	6
values[89]	75	1			T554	4		T480	1		T470	4
values[90]	95	1			T554	5		T480	1		T470	8
values[91]	93	1			T554	3		T480	6		T470	4
values[92]	103	1			T554	1		T480	8		T470	3
values[93]	92	1			T554	2		T480	5		T470	4
values[94]	113	1			T554	6		T480	5		T470	7
values[95]	114	1			T554	1		T480	4		T470	7
values[96]	109	1			T554	2		T480	6		T470	7
values[97]	79	1			T554	5		T480	5		T470	3
values[98]	84	1			T554	5		T480	6		T470	2
values[99]	76	1			T554	2		T480	3		T470	4
values[100]	63	1			T554	1		T480	1		T470	5
values[101]	55	1			T554	3		T480	1		T470	5
values[102]	66	1			T554	1		T480	1		T470	4
values[103]	65	1			T554	3		T480	2		T470	7
values[104]	62	1			T554	4		T480	2		T470	10
values[105]	83	1			T554	4		T480	3		T470	5
values[106]	83	1			T554	4		T480	9		T470	2
values[107]	73	1			T554	1		T480	3		T470	3
values[108]	85	1			T554	2		T480	2		T470	5
values[109]	63	1			T554	1		T480	1		T470	1
values[110]	100	1			T554	2		T480	4		T470	1
values[111]	79	1			T554	3		T480	7		T470	1
values[112]	74	1			T554	2		T480	5		T868	1
values[113]	67	1			T554	2		T480	3		T868	1
values[114]	59	1			T554	2		T480	1		T868	1
values[115]	73	1			T554	1		T480	2		T868	4
values[116]	74	1			T554	3		T480	4		T868	1
values[117]	68	1			T554	2		T480	4		T868	1
values[118]	62	1			T554	2		T480	3		T868	1
values[119]	85	1			T554	1		T480	1		T868	1
values[120]	90	1			T554	1		T480	3		T868	2
values[121]	85	1			T554	1		T480	8		T868	2
values[122]	74	1			T554	3		T480	2		T868	4
values[123]	55	1			T554	1		T480	2		T868	3
values[124]	64	1			T554	2		T480	6		T868	1
values[125]	88	1			T554	2		T480	14		T868	2
values[126]	181	1			T554	2		T480	21		T868	1
values[127]	861	1			T554	26		T480	87		T868	32
values[128]	5417	1			T554	272		T480	45		T868	306