Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149110	1			T85	674		T87	96		T124	711
values[2]	11659	1			T85	111		T87	2		T124	17
values[3]	4142	1			T85	26		T124	6		T554	1
values[4]	2319	1			T85	12		T124	4		T554	1
values[5]	1538	1			T85	5		T124	9		T554	1
values[6]	1028	1			T85	9		T124	9		T554	1
values[7]	733	1			T85	5		T124	13		T554	1
values[8]	606	1			T85	9		T124	9		T554	1
values[9]	512	1			T85	7		T124	2		T554	1
values[10]	476	1			T85	5		T124	12		T554	1
values[11]	398	1			T85	7		T124	5		T554	1
values[12]	398	1			T85	18		T124	8		T554	1
values[13]	387	1			T85	9		T124	9		T554	1
values[14]	399	1			T85	4		T124	8		T554	1
values[15]	385	1			T85	5		T124	15		T554	1
values[16]	306	1			T85	6		T124	4		T554	1
values[17]	299	1			T85	5		T124	3		T554	1
values[18]	300	1			T85	5		T124	3		T554	1
values[19]	316	1			T85	11		T124	3		T554	1
values[20]	339	1			T85	4		T124	5		T554	1
values[21]	306	1			T85	7		T124	12		T554	1
values[22]	349	1			T85	11		T124	19		T554	1
values[23]	292	1			T85	9		T124	6		T554	1
values[24]	344	1			T85	18		T124	5		T554	1
values[25]	246	1			T85	4		T124	3		T554	1
values[26]	282	1			T85	5		T124	4		T554	1
values[27]	266	1			T85	4		T124	11		T554	1
values[28]	323	1			T85	10		T124	3		T554	1
values[29]	345	1			T85	6		T124	14		T554	1
values[30]	279	1			T85	6		T124	7		T554	1
values[31]	323	1			T85	7		T124	13		T554	1
values[32]	352	1			T85	10		T124	6		T554	1
values[33]	353	1			T85	7		T124	5		T554	1
values[34]	366	1			T85	8		T124	3		T554	1
values[35]	329	1			T85	9		T124	9		T554	1
values[36]	338	1			T85	4		T124	5		T554	1
values[37]	290	1			T85	12		T124	18		T554	1
values[38]	311	1			T85	5		T124	13		T554	1
values[39]	332	1			T85	3		T124	11		T554	1
values[40]	288	1			T85	6		T124	3		T554	1
values[41]	295	1			T85	5		T124	3		T554	1
values[42]	319	1			T85	6		T124	3		T554	1
values[43]	329	1			T85	8		T124	5		T554	1
values[44]	292	1			T85	4		T124	15		T554	1
values[45]	346	1			T85	6		T124	4		T554	1
values[46]	321	1			T85	8		T124	4		T554	1
values[47]	302	1			T85	5		T124	7		T554	1
values[48]	286	1			T85	4		T124	5		T554	1
values[49]	317	1			T85	9		T124	11		T554	1
values[50]	287	1			T85	19		T124	5		T554	1
values[51]	277	1			T85	7		T124	5		T554	1
values[52]	253	1			T124	8		T554	1		T499	4
values[53]	332	1			T124	27		T554	1		T499	3
values[54]	258	1			T554	1		T499	5		T863	1
values[55]	282	1			T554	1		T499	8		T863	1
values[56]	240	1			T554	1		T499	10		T863	1
values[57]	238	1			T554	1		T499	4		T863	1
values[58]	259	1			T554	1		T499	5		T863	1
values[59]	228	1			T554	1		T499	6		T863	1
values[60]	223	1			T554	1		T499	7		T863	1
values[61]	206	1			T554	1		T499	9		T863	1
values[62]	196	1			T554	1		T499	1		T863	1
values[63]	243	1			T554	1		T863	1		T514	1
values[64]	269	1			T554	1		T863	1		T514	1
values[65]	235	1			T554	1		T863	1		T514	1
values[66]	203	1			T554	1		T863	1		T514	1
values[67]	179	1			T554	1		T863	1		T514	1
values[68]	194	1			T554	1		T863	1		T514	1
values[69]	188	1			T554	1		T863	1		T514	1
values[70]	192	1			T554	1		T863	1		T514	1
values[71]	180	1			T554	1		T863	1		T514	1
values[72]	191	1			T554	1		T863	1		T514	1
values[73]	230	1			T554	1		T863	1		T514	1
values[74]	163	1			T554	2		T863	1		T514	1
values[75]	133	1			T554	1		T863	1		T514	1
values[76]	145	1			T554	1		T863	1		T514	1
values[77]	120	1			T554	1		T863	1		T514	1
values[78]	112	1			T554	1		T863	1		T514	1
values[79]	108	1			T554	1		T863	1		T514	1
values[80]	113	1			T554	1		T863	1		T514	1
values[81]	127	1			T554	1		T863	1		T514	1
values[82]	101	1			T554	1		T863	1		T514	1
values[83]	94	1			T554	1		T863	1		T514	2
values[84]	104	1			T554	1		T863	1		T514	2
values[85]	118	1			T554	1		T863	1		T514	3
values[86]	110	1			T554	1		T863	1		T514	7
values[87]	101	1			T554	1		T863	1		T514	4
values[88]	119	1			T554	1		T863	1		T514	4
values[89]	92	1			T554	1		T863	1		T514	5
values[90]	79	1			T554	1		T863	2		T514	4
values[91]	82	1			T554	1		T863	2		T514	2
values[92]	79	1			T554	1		T863	2		T514	1
values[93]	93	1			T554	1		T863	1		T514	3
values[94]	89	1			T554	1		T863	1		T514	1
values[95]	89	1			T554	1		T863	3		T514	1
values[96]	93	1			T554	1		T863	1		T514	12
values[97]	82	1			T554	1		T863	3		T514	4
values[98]	87	1			T554	1		T863	5		T514	3
values[99]	109	1			T554	1		T863	1		T514	9
values[100]	115	1			T554	1		T863	1		T514	10
values[101]	97	1			T554	1		T863	2		T514	2
values[102]	95	1			T554	1		T863	1		T514	2
values[103]	89	1			T554	1		T863	4		T514	7
values[104]	80	1			T554	1		T863	7		T514	3
values[105]	71	1			T554	1		T863	2		T514	1
values[106]	76	1			T554	1		T863	3		T514	2
values[107]	61	1			T554	1		T863	2		T514	1
values[108]	49	1			T554	1		T863	2		T514	1
values[109]	54	1			T554	1		T863	1		T514	2
values[110]	50	1			T554	1		T863	2		T514	6
values[111]	44	1			T554	1		T863	1		T514	2
values[112]	61	1			T554	1		T863	1		T514	3
values[113]	57	1			T554	1		T863	5		T514	1
values[114]	42	1			T554	1		T863	1		T514	1
values[115]	51	1			T554	1		T863	1		T514	2
values[116]	56	1			T554	1		T863	1		T514	2
values[117]	43	1			T554	1		T863	2		T514	2
values[118]	52	1			T554	1		T863	1		T514	2
values[119]	58	1			T554	2		T863	1		T514	3
values[120]	37	1			T554	1		T863	1		T514	1
values[121]	47	1			T554	2		T863	2		T514	2
values[122]	48	1			T554	2		T863	4		T514	1
values[123]	41	1			T554	1		T863	2		T514	4
values[124]	32	1			T554	1		T863	1		T514	1
values[125]	46	1			T554	2		T863	2		T514	2
values[126]	58	1			T554	1		T863	2		T514	5
values[127]	665	1			T554	28		T863	35		T514	33
values[128]	6308	1			T554	284		T863	250		T514	258