Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sysrst_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146474	1			T85	628		T87	111		T124	629
values[2]	9648	1			T85	81		T87	3		T124	2
values[3]	3610	1			T85	27		T554	1		T552	10
values[4]	2269	1			T85	9		T554	1		T552	14
values[5]	1501	1			T85	6		T554	1		T552	13
values[6]	1107	1			T85	4		T554	1		T552	10
values[7]	859	1			T85	6		T554	1		T552	14
values[8]	680	1			T85	7		T554	1		T552	6
values[9]	587	1			T85	2		T554	1		T552	4
values[10]	560	1			T554	1		T552	3		T499	5
values[11]	490	1			T554	1		T499	5		T764	2
values[12]	447	1			T554	1		T499	10		T764	10
values[13]	419	1			T554	1		T499	3		T764	4
values[14]	436	1			T554	1		T499	5		T764	9
values[15]	455	1			T554	1		T499	6		T764	6
values[16]	417	1			T554	1		T499	7		T764	2
values[17]	460	1			T554	1		T499	7		T764	6
values[18]	454	1			T554	1		T499	6		T764	4
values[19]	443	1			T554	1		T499	8		T764	4
values[20]	387	1			T554	1		T499	9		T764	2
values[21]	435	1			T554	1		T499	7		T764	3
values[22]	417	1			T554	1		T499	4		T764	3
values[23]	390	1			T554	1		T499	3		T764	1
values[24]	419	1			T554	1		T499	8		T764	4
values[25]	441	1			T554	1		T499	3		T764	14
values[26]	462	1			T554	1		T499	17		T764	4
values[27]	400	1			T554	1		T499	5		T764	2
values[28]	416	1			T554	1		T499	5		T764	5
values[29]	411	1			T554	1		T499	7		T764	3
values[30]	370	1			T554	1		T499	2		T764	3
values[31]	433	1			T554	1		T499	3		T764	1
values[32]	434	1			T554	1		T499	3		T764	3
values[33]	373	1			T554	1		T499	6		T764	3
values[34]	397	1			T554	1		T499	14		T764	1
values[35]	480	1			T554	1		T499	17		T764	2
values[36]	417	1			T554	1		T499	12		T764	2
values[37]	465	1			T554	1		T499	4		T764	13
values[38]	441	1			T554	1		T499	3		T764	10
values[39]	416	1			T554	1		T499	16		T764	6
values[40]	412	1			T554	1		T499	3		T764	1
values[41]	374	1			T554	1		T499	5		T764	3
values[42]	407	1			T554	1		T499	3		T764	2
values[43]	444	1			T554	1		T499	18		T764	2
values[44]	386	1			T554	1		T499	3		T764	4
values[45]	375	1			T554	1		T499	3		T764	3
values[46]	369	1			T554	1		T499	9		T764	2
values[47]	408	1			T554	1		T499	7		T764	4
values[48]	435	1			T554	1		T499	9		T764	7
values[49]	363	1			T554	1		T499	6		T764	3
values[50]	393	1			T554	1		T499	8		T764	2
values[51]	385	1			T554	1		T499	2		T764	2
values[52]	380	1			T554	1		T499	8		T514	1
values[53]	362	1			T554	1		T499	11		T514	2
values[54]	284	1			T554	1		T499	5		T514	1
values[55]	348	1			T554	1		T499	4		T514	1
values[56]	353	1			T554	1		T499	6		T514	1
values[57]	311	1			T554	1		T499	9		T514	1
values[58]	274	1			T554	1		T499	8		T514	1
values[59]	298	1			T554	1		T499	10		T514	1
values[60]	336	1			T554	1		T499	3		T514	1
values[61]	358	1			T554	1		T499	2		T514	1
values[62]	300	1			T554	1		T514	1		T881	1
values[63]	262	1			T554	1		T514	1		T881	1
values[64]	267	1			T554	1		T514	1		T881	1
values[65]	200	1			T554	1		T514	1		T881	1
values[66]	216	1			T554	1		T514	1		T881	1
values[67]	179	1			T554	2		T514	1		T881	1
values[68]	178	1			T554	1		T514	1		T881	1
values[69]	185	1			T554	1		T514	1		T881	1
values[70]	184	1			T554	1		T514	1		T881	1
values[71]	189	1			T554	1		T514	1		T881	1
values[72]	183	1			T554	1		T514	1		T881	1
values[73]	175	1			T554	1		T514	1		T881	1
values[74]	156	1			T554	1		T514	1		T881	1
values[75]	126	1			T554	1		T514	1		T881	1
values[76]	117	1			T554	1		T514	1		T881	1
values[77]	112	1			T554	1		T514	1		T881	1
values[78]	114	1			T554	1		T514	1		T881	1
values[79]	94	1			T554	1		T514	1		T881	1
values[80]	91	1			T554	1		T514	1		T881	1
values[81]	100	1			T554	1		T514	1		T881	1
values[82]	89	1			T554	1		T514	1		T881	1
values[83]	104	1			T554	1		T514	1		T881	1
values[84]	69	1			T554	1		T514	1		T881	1
values[85]	93	1			T554	1		T514	1		T881	1
values[86]	108	1			T554	4		T514	1		T881	1
values[87]	98	1			T554	3		T514	1		T881	1
values[88]	91	1			T554	2		T514	1		T881	1
values[89]	99	1			T554	1		T514	1		T881	1
values[90]	94	1			T554	6		T514	1		T881	1
values[91]	95	1			T554	1		T514	2		T881	1
values[92]	100	1			T554	1		T514	1		T881	1
values[93]	95	1			T554	2		T514	1		T881	1
values[94]	107	1			T554	8		T514	1		T881	1
values[95]	85	1			T554	5		T514	1		T881	1
values[96]	106	1			T554	3		T514	1		T881	1
values[97]	95	1			T554	2		T514	1		T881	2
values[98]	78	1			T554	3		T514	1		T881	1
values[99]	88	1			T554	2		T514	1		T881	1
values[100]	97	1			T554	1		T514	1		T881	1
values[101]	86	1			T554	2		T514	1		T881	1
values[102]	82	1			T554	1		T514	1		T881	1
values[103]	88	1			T554	1		T514	1		T881	1
values[104]	105	1			T554	2		T514	1		T881	1
values[105]	85	1			T554	2		T514	4		T881	1
values[106]	94	1			T554	1		T514	3		T881	1
values[107]	99	1			T554	1		T514	4		T881	1
values[108]	98	1			T554	4		T514	2		T881	2
values[109]	90	1			T554	4		T514	1		T881	5
values[110]	97	1			T554	1		T514	1		T881	3
values[111]	84	1			T554	1		T514	1		T881	2
values[112]	81	1			T554	2		T514	1		T881	3
values[113]	100	1			T554	3		T514	1		T881	2
values[114]	81	1			T554	6		T514	1		T881	3
values[115]	91	1			T554	1		T514	4		T881	2
values[116]	98	1			T554	2		T514	4		T881	9
values[117]	79	1			T554	1		T514	1		T881	3
values[118]	92	1			T554	1		T514	3		T881	1
values[119]	93	1			T554	2		T514	2		T881	4
values[120]	89	1			T554	1		T514	1		T881	1
values[121]	81	1			T554	4		T514	1		T881	2
values[122]	84	1			T554	1		T514	2		T881	1
values[123]	94	1			T554	3		T514	6		T881	1
values[124]	77	1			T554	1		T514	3		T881	3
values[125]	89	1			T554	3		T514	1		T881	2
values[126]	160	1			T554	4		T514	1		T881	4
values[127]	1054	1			T554	39		T514	29		T881	31
values[128]	8902	1			T554	262		T514	294		T881	318