Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.csrng_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	168830	1			T85	900		T86	1		T87	101
values[2]	5453	1			T86	1		T464	1		T554	1
values[3]	2746	1			T86	1		T554	1		T480	20
values[4]	1841	1			T86	1		T554	1		T480	14
values[5]	1403	1			T86	1		T554	1		T480	20
values[6]	1349	1			T86	1		T554	1		T480	22
values[7]	1130	1			T86	1		T554	1		T480	16
values[8]	1097	1			T86	1		T554	1		T480	21
values[9]	1044	1			T86	1		T554	1		T480	19
values[10]	1009	1			T86	1		T554	1		T480	15
values[11]	971	1			T86	1		T554	1		T480	18
values[12]	905	1			T86	1		T554	1		T480	35
values[13]	808	1			T86	1		T554	1		T480	36
values[14]	687	1			T86	1		T554	1		T480	38
values[15]	613	1			T86	1		T554	1		T480	43
values[16]	549	1			T86	1		T554	1		T480	52
values[17]	423	1			T86	1		T554	1		T480	38
values[18]	344	1			T86	1		T554	1		T480	24
values[19]	328	1			T86	1		T554	1		T480	10
values[20]	253	1			T86	1		T554	1		T480	1
values[21]	234	1			T86	1		T554	1		T863	2
values[22]	224	1			T86	1		T554	1		T863	2
values[23]	163	1			T86	1		T554	1		T863	2
values[24]	121	1			T86	1		T554	1		T863	2
values[25]	101	1			T86	1		T554	1		T863	2
values[26]	113	1			T86	1		T554	1		T863	2
values[27]	106	1			T86	1		T554	1		T863	2
values[28]	124	1			T86	1		T554	1		T863	2
values[29]	142	1			T86	1		T554	1		T863	2
values[30]	151	1			T86	1		T554	1		T863	2
values[31]	171	1			T86	1		T554	1		T863	2
values[32]	151	1			T86	1		T554	1		T863	2
values[33]	152	1			T86	1		T554	1		T863	2
values[34]	131	1			T86	1		T554	1		T863	2
values[35]	110	1			T86	1		T554	1		T863	2
values[36]	99	1			T86	1		T554	1		T863	2
values[37]	107	1			T86	1		T554	1		T863	2
values[38]	116	1			T86	1		T554	1		T863	2
values[39]	97	1			T86	1		T554	1		T863	2
values[40]	134	1			T86	1		T554	1		T863	2
values[41]	110	1			T86	1		T554	1		T863	2
values[42]	93	1			T86	1		T554	1		T863	2
values[43]	90	1			T86	1		T554	1		T863	2
values[44]	63	1			T86	1		T554	1		T863	2
values[45]	71	1			T86	1		T554	1		T863	2
values[46]	107	1			T86	1		T554	1		T863	2
values[47]	121	1			T86	1		T554	1		T863	2
values[48]	102	1			T86	1		T554	1		T863	2
values[49]	78	1			T86	1		T554	1		T863	2
values[50]	85	1			T86	1		T554	1		T863	2
values[51]	83	1			T86	1		T554	1		T863	2
values[52]	64	1			T86	1		T554	1		T863	2
values[53]	65	1			T86	1		T554	1		T863	2
values[54]	67	1			T86	1		T554	1		T863	2
values[55]	63	1			T86	1		T554	1		T863	2
values[56]	53	1			T86	1		T554	1		T863	2
values[57]	46	1			T86	1		T554	1		T863	2
values[58]	44	1			T86	1		T554	1		T863	2
values[59]	48	1			T86	1		T554	1		T863	2
values[60]	50	1			T86	1		T554	1		T863	2
values[61]	58	1			T86	1		T554	1		T863	2
values[62]	61	1			T86	1		T554	1		T863	2
values[63]	53	1			T86	1		T554	1		T863	2
values[64]	48	1			T86	1		T554	1		T863	2
values[65]	45	1			T86	1		T554	1		T863	2
values[66]	57	1			T86	1		T554	1		T863	2
values[67]	47	1			T86	1		T554	1		T863	2
values[68]	42	1			T86	1		T554	1		T863	2
values[69]	50	1			T86	1		T554	1		T863	2
values[70]	55	1			T86	1		T554	1		T863	2
values[71]	37	1			T86	1		T554	1		T863	2
values[72]	40	1			T86	1		T554	1		T863	2
values[73]	44	1			T86	1		T554	1		T863	2
values[74]	35	1			T86	1		T554	1		T863	2
values[75]	45	1			T86	1		T554	1		T863	2
values[76]	51	1			T86	1		T554	1		T863	2
values[77]	51	1			T86	1		T554	1		T863	3
values[78]	46	1			T86	1		T554	1		T863	2
values[79]	45	1			T86	1		T554	1		T863	2
values[80]	50	1			T86	1		T554	1		T863	2
values[81]	49	1			T86	1		T554	1		T863	2
values[82]	41	1			T86	1		T554	1		T863	2
values[83]	55	1			T86	1		T554	1		T863	2
values[84]	50	1			T86	1		T554	1		T863	3
values[85]	45	1			T86	1		T554	1		T863	4
values[86]	45	1			T86	1		T554	1		T863	3
values[87]	50	1			T86	1		T554	1		T863	2
values[88]	50	1			T86	1		T554	1		T863	4
values[89]	47	1			T86	1		T554	1		T863	2
values[90]	58	1			T86	1		T554	1		T863	5
values[91]	57	1			T86	1		T554	1		T863	5
values[92]	65	1			T86	1		T554	2		T863	7
values[93]	58	1			T86	2		T554	6		T863	4
values[94]	47	1			T86	2		T554	3		T863	2
values[95]	53	1			T86	7		T554	4		T863	2
values[96]	48	1			T86	1		T554	3		T863	2
values[97]	51	1			T86	1		T554	3		T863	4
values[98]	61	1			T86	2		T554	6		T863	4
values[99]	69	1			T86	2		T554	1		T863	2
values[100]	71	1			T86	3		T554	3		T863	5
values[101]	61	1			T86	5		T554	1		T863	5
values[102]	59	1			T86	2		T554	2		T863	7
values[103]	51	1			T86	1		T554	4		T863	5
values[104]	56	1			T86	1		T554	2		T863	4
values[105]	68	1			T86	1		T554	1		T863	4
values[106]	67	1			T86	3		T554	2		T863	3
values[107]	59	1			T86	1		T554	2		T863	4
values[108]	72	1			T86	5		T554	2		T863	4
values[109]	59	1			T86	4		T554	1		T863	2
values[110]	79	1			T86	1		T554	2		T863	7
values[111]	83	1			T86	2		T554	3		T863	4
values[112]	76	1			T86	2		T554	3		T863	3
values[113]	104	1			T86	3		T554	7		T863	7
values[114]	79	1			T86	1		T554	3		T863	6
values[115]	77	1			T86	2		T554	5		T863	6
values[116]	74	1			T86	1		T554	1		T863	2
values[117]	96	1			T86	1		T554	1		T863	3
values[118]	102	1			T86	1		T554	1		T863	4
values[119]	104	1			T86	6		T554	1		T863	7
values[120]	90	1			T86	3		T554	1		T863	6
values[121]	89	1			T86	1		T554	1		T863	4
values[122]	67	1			T86	2		T554	3		T863	5
values[123]	93	1			T86	2		T554	3		T863	6
values[124]	175	1			T86	2		T554	2		T863	6
values[125]	306	1			T86	2		T554	4		T863	3
values[126]	714	1			T86	12		T554	11		T863	28
values[127]	2973	1			T86	106		T554	109		T863	200
values[128]	5314	1			T86	210		T554	251		T863	428