Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__core_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	166675	1			T85	2318		T87	91		T124	1229
values[2]	4774	1			T87	2		T465	1		T464	1
values[3]	2381	1			T554	1		T564	1		T514	3
values[4]	1626	1			T554	1		T514	2		T865	37
values[5]	1237	1			T554	1		T514	2		T865	24
values[6]	1049	1			T554	1		T514	2		T865	19
values[7]	819	1			T554	1		T514	2		T865	14
values[8]	734	1			T554	1		T514	2		T865	11
values[9]	741	1			T554	1		T514	2		T865	14
values[10]	714	1			T554	1		T514	2		T865	10
values[11]	658	1			T554	1		T514	2		T865	7
values[12]	578	1			T554	1		T514	2		T865	5
values[13]	480	1			T554	1		T514	2		T865	4
values[14]	417	1			T554	1		T514	2		T865	6
values[15]	355	1			T554	1		T514	3		T865	12
values[16]	360	1			T554	1		T514	2		T865	28
values[17]	372	1			T554	1		T514	2		T865	35
values[18]	365	1			T554	1		T514	2		T865	26
values[19]	310	1			T554	1		T514	2		T865	9
values[20]	279	1			T554	1		T514	2		T865	2
values[21]	251	1			T554	1		T514	2		T865	9
values[22]	202	1			T554	1		T514	2		T865	5
values[23]	148	1			T554	1		T514	2		T865	12
values[24]	142	1			T554	1		T514	2		T865	11
values[25]	156	1			T554	1		T514	2		T865	16
values[26]	183	1			T554	1		T514	2		T865	21
values[27]	250	1			T554	1		T514	2		T865	28
values[28]	279	1			T554	1		T514	2		T865	12
values[29]	211	1			T554	1		T514	2		T865	2
values[30]	198	1			T554	1		T514	2		T470	1
values[31]	167	1			T554	1		T514	2		T470	3
values[32]	164	1			T554	1		T514	2		T470	2
values[33]	161	1			T554	1		T514	2		T470	3
values[34]	149	1			T554	1		T514	2		T470	7
values[35]	182	1			T554	1		T514	2		T470	12
values[36]	148	1			T554	1		T514	2		T470	3
values[37]	135	1			T554	1		T514	2		T470	11
values[38]	148	1			T554	1		T514	2		T470	6
values[39]	135	1			T554	1		T514	2		T470	5
values[40]	125	1			T554	1		T514	2		T470	2
values[41]	122	1			T554	1		T514	2		T470	3
values[42]	131	1			T554	1		T514	2		T470	6
values[43]	126	1			T554	1		T514	2		T470	4
values[44]	94	1			T554	2		T514	2		T470	2
values[45]	100	1			T554	1		T514	2		T470	3
values[46]	94	1			T554	1		T514	2		T470	2
values[47]	73	1			T554	1		T514	2		T470	1
values[48]	88	1			T554	1		T514	2		T470	1
values[49]	80	1			T554	1		T514	2		T470	3
values[50]	81	1			T554	1		T514	2		T470	3
values[51]	86	1			T554	1		T514	2		T470	3
values[52]	81	1			T554	1		T514	2		T470	3
values[53]	67	1			T554	1		T514	2		T470	1
values[54]	80	1			T554	1		T514	2		T470	2
values[55]	68	1			T554	1		T514	2		T470	1
values[56]	76	1			T554	1		T514	2		T470	5
values[57]	74	1			T554	1		T514	2		T470	2
values[58]	92	1			T554	1		T514	2		T470	2
values[59]	90	1			T554	1		T514	2		T470	3
values[60]	89	1			T554	1		T514	2		T470	2
values[61]	87	1			T554	1		T514	2		T470	1
values[62]	96	1			T554	1		T514	2		T470	2
values[63]	88	1			T554	1		T514	2		T470	2
values[64]	81	1			T554	1		T514	2		T470	1
values[65]	74	1			T554	1		T514	2		T470	3
values[66]	85	1			T554	1		T514	2		T470	2
values[67]	81	1			T554	1		T514	2		T470	1
values[68]	98	1			T554	1		T514	2		T470	2
values[69]	84	1			T554	1		T514	2		T470	3
values[70]	88	1			T554	1		T514	2		T470	1
values[71]	84	1			T554	1		T514	2		T470	4
values[72]	60	1			T554	1		T514	2		T470	3
values[73]	76	1			T554	1		T514	2		T470	4
values[74]	87	1			T554	1		T514	2		T470	4
values[75]	85	1			T554	1		T514	2		T470	2
values[76]	83	1			T554	1		T514	2		T470	1
values[77]	82	1			T554	1		T514	2		T470	1
values[78]	82	1			T554	1		T514	2		T470	4
values[79]	77	1			T554	1		T514	2		T470	1
values[80]	63	1			T554	1		T514	2		T470	1
values[81]	77	1			T554	1		T514	2		T470	3
values[82]	83	1			T554	1		T514	2		T470	1
values[83]	91	1			T554	1		T514	2		T470	1
values[84]	96	1			T554	1		T514	2		T470	3
values[85]	88	1			T554	1		T514	2		T470	2
values[86]	86	1			T554	1		T514	2		T470	2
values[87]	98	1			T554	1		T514	2		T470	1
values[88]	82	1			T554	1		T514	2		T470	4
values[89]	91	1			T554	1		T514	2		T470	2
values[90]	106	1			T554	1		T514	7		T470	1
values[91]	92	1			T554	1		T514	3		T470	1
values[92]	106	1			T554	1		T514	6		T470	2
values[93]	87	1			T554	1		T514	6		T470	1
values[94]	119	1			T554	1		T514	8		T470	2
values[95]	113	1			T554	1		T514	5		T470	2
values[96]	111	1			T554	1		T514	4		T470	2
values[97]	90	1			T554	1		T514	5		T470	1
values[98]	100	1			T554	1		T514	2		T470	2
values[99]	117	1			T554	1		T514	2		T470	2
values[100]	95	1			T554	2		T514	3		T470	1
values[101]	101	1			T554	3		T514	2		T470	3
values[102]	106	1			T554	4		T514	3		T470	6
values[103]	118	1			T554	5		T514	6		T470	4
values[104]	114	1			T554	5		T514	4		T470	10
values[105]	128	1			T554	4		T514	5		T470	10
values[106]	116	1			T554	4		T514	6		T470	8
values[107]	106	1			T554	4		T514	4		T470	6
values[108]	108	1			T554	1		T514	2		T470	10
values[109]	106	1			T554	1		T514	6		T470	2
values[110]	137	1			T554	7		T514	4		T470	6
values[111]	117	1			T554	2		T514	4		T470	8
values[112]	129	1			T554	1		T514	3		T470	7
values[113]	135	1			T554	1		T514	5		T470	13
values[114]	142	1			T554	5		T514	2		T470	7
values[115]	135	1			T554	2		T514	4		T470	8
values[116]	163	1			T554	1		T514	7		T470	8
values[117]	157	1			T554	1		T514	7		T470	5
values[118]	128	1			T554	1		T514	6		T470	8
values[119]	128	1			T554	1		T514	5		T470	1
values[120]	151	1			T554	3		T514	5		T470	2
values[121]	149	1			T554	2		T514	3		T470	6
values[122]	118	1			T554	3		T514	4		T470	3
values[123]	173	1			T554	2		T514	5		T470	12
values[124]	262	1			T554	1		T514	5		T470	12
values[125]	541	1			T554	2		T514	6		T470	23
values[126]	1035	1			T554	11		T514	25		T470	65
values[127]	2995	1			T554	106		T514	208		T470	36
values[128]	4826	1			T554	197		T514	414		T470	2