Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	493	1			T85	4		T86	1		T555	1
all_values[1]	477	1			T85	5		T124	3		T552	2
all_values[2]	503	1			T85	5		T86	2		T124	2
all_values[3]	504	1			T85	2		T124	4		T552	2
all_values[4]	474	1			T85	1		T86	1		T554	2
all_values[5]	481	1			T85	1		T124	3		T555	1
all_values[6]	485	1			T85	3		T124	3		T555	3
all_values[7]	501	1			T85	7		T124	1		T554	1
all_values[8]	474	1			T85	1		T124	2		T555	4
all_values[9]	480	1			T85	4		T86	1		T124	2
all_values[10]	444	1			T85	3		T555	1		T552	1
all_values[11]	513	1			T85	3		T554	1		T553	1
all_values[12]	484	1			T85	3		T124	4		T555	1
all_values[13]	441	1			T85	2		T124	3		T554	1
all_values[14]	481	1			T85	4		T86	1		T124	3
all_values[15]	509	1			T85	7		T124	5		T552	1
all_values[16]	501	1			T85	3		T124	2		T872	1
all_values[17]	449	1			T124	1		T489	1		T546	2
all_values[18]	499	1			T85	6		T86	1		T124	2
all_values[19]	498	1			T85	1		T124	1		T555	1
all_values[20]	493	1			T85	3		T86	1		T124	3
all_values[21]	529	1			T85	4		T124	2		T555	2
all_values[22]	487	1			T85	1		T124	1		T553	2
all_values[23]	503	1			T85	3		T86	1		T124	5
all_values[24]	521	1			T85	4		T124	3		T555	4
all_values[25]	513	1			T85	2		T124	4		T555	1
all_values[26]	489	1			T85	3		T124	4		T555	1
all_values[27]	499	1			T85	1		T86	1		T124	1
all_values[28]	528	1			T86	1		T124	3		T555	1
all_values[29]	518	1			T85	2		T124	1		T554	1
all_values[30]	472	1			T85	5		T124	5		T555	1
all_values[31]	499	1			T85	4		T86	1		T124	2
all_values[32]	503	1			T85	3		T124	3		T555	1
all_values[33]	483	1			T85	4		T86	1		T124	3
all_values[34]	502	1			T85	2		T124	3		T552	1
all_values[35]	494	1			T85	2		T124	2		T554	1
all_values[36]	459	1			T85	2		T124	3		T555	1
all_values[37]	475	1			T85	5		T124	3		T467	1
all_values[38]	532	1			T85	1		T86	1		T124	2
all_values[39]	510	1			T85	1		T124	1		T555	1
all_values[40]	456	1			T85	2		T86	1		T124	3
all_values[41]	502	1			T85	5		T124	3		T553	1
all_values[42]	474	1			T85	5		T124	4		T555	1
all_values[43]	429	1			T85	1		T124	2		T554	1
all_values[44]	504	1			T85	3		T124	3		T554	1
all_values[45]	512	1			T85	5		T124	3		T554	1
all_values[46]	497	1			T85	3		T86	1		T124	3
all_values[47]	490	1			T85	1		T124	3		T554	1
all_values[48]	503	1			T85	5		T124	1		T552	1
all_values[49]	497	1			T85	4		T124	2		T467	1