Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3536	1			T85	23		T124	36		T428	2
all_values[1]	3666	1			T85	24		T124	34		T428	2
all_values[2]	3632	1			T85	26		T124	36		T428	2
all_values[3]	3681	1			T85	18		T124	30		T428	1
all_values[4]	3779	1			T85	29		T124	28		T428	2
all_values[5]	3604	1			T85	23		T124	26		T428	5
all_values[6]	3570	1			T85	15		T124	28		T428	1
all_values[7]	3675	1			T85	22		T124	39		T428	1
all_values[8]	3712	1			T85	25		T124	31		T428	4
all_values[9]	3645	1			T85	27		T124	31		T557	2
all_values[10]	3734	1			T85	20		T124	32		T428	1
all_values[11]	3687	1			T85	29		T124	30		T428	1
all_values[12]	3666	1			T85	20		T124	33		T428	3
all_values[13]	3676	1			T85	30		T124	28		T428	6
all_values[14]	3694	1			T85	25		T124	41		T557	3
all_values[15]	3552	1			T85	27		T124	25		T428	1
all_values[16]	3602	1			T85	25		T124	29		T428	2
all_values[17]	3600	1			T85	26		T124	30		T428	1
all_values[18]	3630	1			T85	34		T124	26		T428	2
all_values[19]	3633	1			T85	22		T124	39		T428	2
all_values[20]	3632	1			T85	24		T124	36		T428	4
all_values[21]	3611	1			T85	32		T124	34		T428	1
all_values[22]	3549	1			T85	27		T124	33		T428	1
all_values[23]	3511	1			T85	21		T124	24		T428	3
all_values[24]	3670	1			T85	24		T124	41		T428	3
all_values[25]	3642	1			T85	21		T124	23		T428	1
all_values[26]	3634	1			T85	21		T124	21		T428	5
all_values[27]	3737	1			T85	21		T124	33		T428	3
all_values[28]	3658	1			T85	28		T124	38		T557	2
all_values[29]	3627	1			T85	24		T124	24		T428	5
all_values[30]	3686	1			T85	27		T124	39		T428	2
all_values[31]	3704	1			T85	23		T124	33		T428	2
all_values[32]	3614	1			T85	26		T124	29		T428	2
all_values[33]	3623	1			T85	19		T124	34		T428	6
all_values[34]	3655	1			T85	19		T124	29		T428	2
all_values[35]	3703	1			T85	20		T124	35		T428	4
all_values[36]	3586	1			T85	21		T124	32		T557	4
all_values[37]	3790	1			T85	30		T124	34		T428	4
all_values[38]	3629	1			T85	23		T124	36		T428	4
all_values[39]	3485	1			T85	19		T124	30		T428	1
all_values[40]	3541	1			T85	18		T124	38		T428	1
all_values[41]	3592	1			T85	15		T124	15		T428	2
all_values[42]	3573	1			T85	26		T124	29		T428	3
all_values[43]	3669	1			T85	19		T124	37		T428	2
all_values[44]	3600	1			T85	18		T124	27		T428	3
all_values[45]	3587	1			T85	34		T124	33		T428	2
all_values[46]	3701	1			T85	29		T124	36		T428	4
all_values[47]	3563	1			T85	28		T124	29		T428	2
all_values[48]	3680	1			T85	24		T124	32		T428	5
all_values[49]	3719	1			T85	27		T124	33		T428	4
all_values[50]	3830	1			T85	27		T124	32		T428	3
all_values[51]	3656	1			T85	26		T124	33		T428	2
all_values[52]	3683	1			T85	25		T124	32		T428	4
all_values[53]	3666	1			T85	29		T124	34		T428	2
all_values[54]	3623	1			T85	23		T124	27		T428	1
all_values[55]	3652	1			T85	20		T124	35		T428	2
all_values[56]	3729	1			T85	22		T124	32		T428	2
all_values[57]	3743	1			T85	30		T124	42		T557	2
all_values[58]	3661	1			T85	41		T124	31		T428	2
all_values[59]	3660	1			T85	20		T124	37		T428	2
all_values[60]	3567	1			T85	21		T124	25		T428	1
all_values[61]	3589	1			T85	18		T124	37		T428	1
all_values[62]	3701	1			T85	22		T124	28		T557	1
all_values[63]	3532	1			T85	23		T124	43		T557	1