Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	137847	1			T71	18		T72	1		T77	46
values[2]	11452	1			T77	2		T119	2		T246	3
values[3]	4798	1			T77	1		T464	21		T545	94
values[4]	2978	1			T464	19		T545	47		T546	42
values[5]	1731	1			T464	17		T545	44		T546	10
values[6]	1135	1			T464	3		T545	26		T546	5
values[7]	846	1			T464	13		T545	23		T864	4
values[8]	667	1			T464	2		T545	18		T864	10
values[9]	505	1			T545	10		T864	17		T429	2
values[10]	416	1			T545	6		T864	3		T429	2
values[11]	354	1			T545	1		T864	6		T429	2
values[12]	387	1			T864	9		T429	2		T466	11
values[13]	386	1			T864	9		T429	2		T466	6
values[14]	315	1			T864	3		T429	2		T506	22
values[15]	341	1			T864	9		T429	2		T506	16
values[16]	313	1			T864	5		T429	2		T506	8
values[17]	392	1			T864	9		T429	2		T506	17
values[18]	381	1			T864	9		T429	2		T506	15
values[19]	320	1			T864	5		T429	2		T506	10
values[20]	339	1			T864	11		T429	2		T506	18
values[21]	302	1			T864	11		T429	2		T506	9
values[22]	291	1			T864	9		T429	2		T506	7
values[23]	303	1			T864	6		T429	2		T506	14
values[24]	337	1			T864	5		T429	2		T506	10
values[25]	247	1			T864	4		T429	2		T506	6
values[26]	281	1			T864	2		T429	2		T506	10
values[27]	353	1			T864	16		T429	2		T506	10
values[28]	306	1			T864	8		T429	2		T506	9
values[29]	302	1			T864	5		T429	2		T506	9
values[30]	320	1			T864	9		T429	2		T506	9
values[31]	331	1			T864	4		T429	2		T506	10
values[32]	321	1			T864	5		T429	2		T506	17
values[33]	301	1			T864	9		T429	2		T506	9
values[34]	313	1			T864	8		T429	2		T506	4
values[35]	290	1			T864	4		T429	2		T506	3
values[36]	253	1			T864	3		T429	2		T506	8
values[37]	296	1			T864	3		T429	2		T506	9
values[38]	276	1			T864	5		T429	2		T506	9
values[39]	308	1			T864	8		T429	2		T506	9
values[40]	333	1			T864	4		T429	2		T506	15
values[41]	250	1			T864	17		T429	2		T506	6
values[42]	276	1			T864	16		T429	2		T506	5
values[43]	266	1			T864	3		T429	2		T506	7
values[44]	237	1			T864	8		T429	2		T506	4
values[45]	272	1			T864	3		T429	2		T506	5
values[46]	270	1			T864	6		T429	2		T506	6
values[47]	271	1			T864	7		T429	2		T506	15
values[48]	257	1			T864	10		T429	2		T506	5
values[49]	244	1			T864	3		T429	2		T506	4
values[50]	204	1			T864	6		T429	2		T506	5
values[51]	216	1			T864	12		T429	2		T506	3
values[52]	228	1			T864	19		T429	2		T506	3
values[53]	176	1			T864	5		T429	3		T506	6
values[54]	166	1			T864	3		T429	2		T506	6
values[55]	196	1			T864	4		T429	2		T506	7
values[56]	207	1			T864	4		T429	2		T506	8
values[57]	152	1			T429	2		T506	11		T726	1
values[58]	152	1			T429	2		T506	12		T726	1
values[59]	173	1			T429	2		T506	13		T726	1
values[60]	159	1			T429	2		T506	6		T726	1
values[61]	170	1			T429	2		T506	5		T726	1
values[62]	149	1			T429	2		T506	2		T726	1
values[63]	163	1			T429	2		T506	2		T726	1
values[64]	116	1			T429	2		T506	6		T726	1
values[65]	127	1			T429	2		T506	5		T726	1
values[66]	76	1			T429	2		T506	3		T726	1
values[67]	100	1			T429	2		T506	7		T726	1
values[68]	94	1			T429	2		T506	5		T726	1
values[69]	78	1			T429	2		T506	4		T726	1
values[70]	69	1			T429	2		T506	10		T726	1
values[71]	72	1			T429	2		T506	12		T726	1
values[72]	59	1			T429	2		T506	7		T726	1
values[73]	56	1			T429	2		T506	2		T726	1
values[74]	67	1			T429	2		T506	4		T726	1
values[75]	62	1			T429	2		T506	18		T726	1
values[76]	53	1			T429	2		T506	4		T726	1
values[77]	48	1			T429	2		T506	2		T726	1
values[78]	59	1			T429	2		T506	7		T726	1
values[79]	50	1			T429	2		T506	7		T726	1
values[80]	55	1			T429	2		T506	11		T726	1
values[81]	74	1			T429	2		T506	16		T726	1
values[82]	76	1			T429	3		T506	10		T726	1
values[83]	68	1			T429	2		T506	17		T726	1
values[84]	61	1			T429	2		T506	11		T726	1
values[85]	58	1			T429	2		T506	9		T726	1
values[86]	59	1			T429	2		T506	10		T726	1
values[87]	55	1			T429	2		T506	8		T726	1
values[88]	51	1			T429	2		T506	10		T726	1
values[89]	74	1			T429	2		T506	12		T726	1
values[90]	47	1			T429	2		T506	6		T726	1
values[91]	61	1			T429	2		T506	6		T726	1
values[92]	64	1			T429	2		T506	5		T726	1
values[93]	58	1			T429	2		T506	7		T726	1
values[94]	66	1			T429	8		T506	3		T726	1
values[95]	54	1			T429	2		T506	7		T726	1
values[96]	73	1			T429	3		T506	9		T726	1
values[97]	61	1			T429	3		T506	7		T726	1
values[98]	58	1			T429	5		T506	8		T726	1
values[99]	64	1			T429	3		T506	11		T726	1
values[100]	60	1			T429	7		T506	4		T726	1
values[101]	58	1			T429	3		T506	7		T726	1
values[102]	71	1			T429	6		T506	5		T726	1
values[103]	59	1			T429	3		T506	10		T726	1
values[104]	63	1			T429	5		T506	8		T726	1
values[105]	63	1			T429	2		T506	6		T726	1
values[106]	61	1			T429	4		T506	13		T726	1
values[107]	59	1			T429	2		T506	9		T726	1
values[108]	42	1			T429	2		T506	3		T726	1
values[109]	61	1			T429	3		T506	10		T726	1
values[110]	73	1			T429	2		T506	18		T726	1
values[111]	51	1			T429	3		T506	10		T726	1
values[112]	45	1			T429	3		T506	9		T726	1
values[113]	42	1			T429	3		T506	4		T726	1
values[114]	48	1			T429	6		T506	5		T726	1
values[115]	54	1			T429	2		T506	10		T726	1
values[116]	49	1			T429	2		T506	13		T726	1
values[117]	44	1			T429	5		T506	5		T726	1
values[118]	55	1			T429	3		T506	12		T726	1
values[119]	49	1			T429	2		T506	8		T726	1
values[120]	43	1			T429	4		T506	5		T726	1
values[121]	58	1			T429	3		T506	8		T726	1
values[122]	47	1			T429	2		T506	8		T726	1
values[123]	38	1			T429	6		T506	6		T726	1
values[124]	39	1			T429	3		T506	3		T726	2
values[125]	52	1			T429	2		T506	9		T726	1
values[126]	77	1			T429	3		T506	18		T726	4
values[127]	633	1			T429	65		T506	46		T726	26
values[128]	5351	1			T429	696		T506	15		T726	315