Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	95.32	93.68	95.40		94.44	97.53	99.57

Total tests in report: 2933

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
40.27	40.27	44.96	44.96	43.00	43.00	35.98	35.98			57.87	57.87	59.44	59.44	0.39	0.39	/workspace/coverage/default/74.chip_sw_all_escalation_resets.2243687074
49.40	9.13	50.87	5.90	56.90	13.90	36.57	0.58			67.76	9.89	82.52	23.08	1.80	1.41	/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1698790533
57.19	7.79	62.16	11.30	60.18	3.28	39.70	3.13			68.67	0.92	82.52	0.00	29.93	28.13	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.973936429
62.66	5.46	73.80	11.64	67.54	7.36	43.28	3.58			78.87	10.20	82.52	0.00	29.93	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.1110084986
66.20	3.54	73.91	0.11	69.25	1.72	45.81	2.54			79.08	0.20	82.52	0.00	46.61	16.68	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1970985421
69.43	3.23	79.27	5.36	73.28	4.03	49.46	3.64			80.88	1.80	87.06	4.55	46.61	0.00	/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3289142618
72.04	2.62	79.27	0.00	73.30	0.01	49.46	0.00			80.88	0.00	87.06	0.00	62.30	15.69	/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.2732024053
74.52	2.47	81.76	2.49	76.29	2.99	55.95	6.49			83.22	2.34	87.59	0.52	62.30	0.00	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2529578082
76.47	1.95	81.76	0.00	76.29	0.00	67.67	11.73			83.22	0.00	87.59	0.00	62.30	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.601755044
78.34	1.87	81.76	0.00	76.29	0.00	67.67	0.00			83.22	0.00	87.59	0.00	73.50	11.21	/workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.3302317068
80.14	1.80	84.78	3.02	77.84	1.55	71.90	4.22			84.20	0.98	88.64	1.05	73.50	0.00	/workspace/coverage/default/1.chip_sw_power_virus.2115351456
81.70	1.56	85.07	0.29	77.99	0.15	80.47	8.58			84.38	0.18	88.81	0.17	73.50	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.824524958
82.96	1.26	86.29	1.22	78.93	0.94	81.07	0.60			85.45	1.07	92.48	3.67	73.55	0.05	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3382204545
84.09	1.13	88.39	2.10	80.87	1.94	81.51	0.44			87.74	2.29	92.48	0.00	73.55	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.1928488423
85.20	1.11	89.71	1.32	83.29	2.42	81.59	0.08			90.60	2.86	92.48	0.00	73.55	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3451791358
86.18	0.98	89.71	0.00	83.29	0.00	81.59	0.00			90.60	0.00	92.48	0.00	79.44	5.89	/workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.4129891011
87.11	0.93	90.02	0.32	83.33	0.04	84.11	2.51			90.60	0.01	92.48	0.00	82.13	2.69	/workspace/coverage/cover_reg_top/51.xbar_random.2167033977
87.96	0.85	90.85	0.83	84.16	0.82	85.55	1.45			91.18	0.58	92.48	0.00	83.53	1.40	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1161967516
88.78	0.83	91.57	0.73	84.33	0.17	85.57	0.01			91.38	0.19	96.33	3.85	83.53	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3837524017
89.57	0.78	91.57	0.00	84.33	0.00	85.57	0.00			91.38	0.00	96.33	0.00	88.23	4.70	/workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.1547406720
90.16	0.60	91.57	0.00	84.76	0.44	85.57	0.00			91.39	0.02	96.33	0.00	91.35	3.13	/workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.649391824
90.69	0.53	91.58	0.01	87.53	2.76	85.57	0.00			91.39	0.00	96.33	0.00	91.76	0.41	/workspace/coverage/cover_reg_top/11.chip_tl_errors.576827546
91.14	0.45	92.66	1.08	88.13	0.60	86.10	0.53			91.88	0.49	96.33	0.00	91.76	0.00	/workspace/coverage/default/2.chip_sw_gpio_smoketest.1402848194
91.50	0.35	92.71	0.04	88.14	0.02	88.12	2.02			91.89	0.01	96.33	0.00	91.80	0.04	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3087719095
91.85	0.35	93.23	0.52	88.66	0.52	88.66	0.54			92.40	0.51	96.33	0.00	91.80	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1406939612
92.18	0.34	93.23	0.00	88.66	0.00	88.66	0.00			92.40	0.00	96.33	0.00	93.82	2.02	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.3480579301
92.44	0.25	93.23	0.00	88.67	0.01	88.66	0.00			92.40	0.00	96.33	0.00	95.34	1.52	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3102116270
92.69	0.25	93.23	0.00	88.78	0.12	88.66	0.00			92.41	0.02	96.33	0.00	96.72	1.39	/workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.2682898016
92.90	0.21	93.35	0.12	88.83	0.05	89.70	1.05			92.45	0.03	96.33	0.00	96.72	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.337701126
93.07	0.17	93.35	0.00	88.83	0.00	90.74	1.03			92.45	0.00	96.33	0.00	96.72	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2659186779
93.23	0.16	93.51	0.15	89.09	0.26	90.82	0.09			92.71	0.27	96.33	0.00	96.90	0.18	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3404363006
93.37	0.15	93.71	0.21	89.41	0.32	91.18	0.35			92.71	0.00	96.33	0.00	96.90	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1170240848
93.52	0.14	93.93	0.22	89.81	0.40	91.18	0.00			92.96	0.24	96.33	0.00	96.90	0.00	/workspace/coverage/cover_reg_top/6.chip_csr_rw.592960039
93.66	0.14	93.94	0.01	90.20	0.39	91.19	0.01			93.40	0.44	96.33	0.00	96.90	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3534948180
93.79	0.13	93.94	0.00	90.23	0.03	91.19	0.00			93.40	0.00	96.33	0.00	97.67	0.78	/workspace/coverage/cover_reg_top/95.xbar_random_large_delays.91352766
93.91	0.12	93.98	0.04	90.36	0.13	91.45	0.26			93.49	0.10	96.50	0.17	97.67	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2084617837
94.02	0.11	93.98	0.00	91.04	0.69	91.45	0.00			93.49	0.00	96.50	0.00	97.67	0.00	/workspace/coverage/cover_reg_top/28.chip_tl_errors.2566095178
94.14	0.11	93.98	0.00	91.04	0.00	92.13	0.68			93.49	0.00	96.50	0.00	97.67	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3438146891
94.24	0.10	94.20	0.22	91.17	0.13	92.26	0.13			93.62	0.13	96.50	0.00	97.67	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3958205532
94.32	0.08	94.20	0.00	91.40	0.23	92.26	0.00			93.66	0.03	96.50	0.00	97.89	0.21	/workspace/coverage/cover_reg_top/13.xbar_stress_all.1478457949
94.39	0.08	94.20	0.00	91.40	0.00	92.72	0.46			93.66	0.00	96.50	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1581270630
94.47	0.08	94.20	0.00	91.61	0.21	92.72	0.00			93.90	0.24	96.50	0.00	97.89	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3077437405
94.54	0.07	94.20	0.00	91.64	0.02	93.10	0.38			93.91	0.02	96.50	0.00	97.89	0.00	/workspace/coverage/default/0.chip_sw_flash_init.4158702616
94.60	0.06	94.22	0.02	91.68	0.04	93.22	0.12			93.91	0.00	96.50	0.00	98.07	0.19	/workspace/coverage/default/0.chip_sw_alert_test.353070962
94.66	0.05	94.22	0.01	91.71	0.04	93.49	0.27			93.91	0.00	96.50	0.00	98.08	0.01	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2538162532
94.71	0.05	94.22	0.00	91.71	0.00	93.82	0.32			93.91	0.00	96.50	0.00	98.08	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1918928427
94.76	0.05	94.29	0.07	91.87	0.15	93.82	0.01			94.01	0.10	96.50	0.00	98.08	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.517476014
94.81	0.04	94.31	0.02	91.90	0.03	93.82	0.00			94.03	0.02	96.68	0.17	98.10	0.01	/workspace/coverage/default/92.chip_sw_all_escalation_resets.2605452854
94.85	0.04	94.32	0.01	91.91	0.02	93.83	0.01			94.05	0.02	96.85	0.17	98.11	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1423264704
94.88	0.04	94.35	0.03	91.92	0.01	93.83	0.01			94.06	0.01	97.03	0.17	98.12	0.01	/workspace/coverage/default/30.chip_sw_all_escalation_resets.764238805
94.92	0.04	94.37	0.02	91.97	0.06	93.95	0.11			94.09	0.03	97.03	0.00	98.12	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2800725664
94.96	0.04	94.37	0.00	91.97	0.00	94.17	0.22			94.09	0.00	97.03	0.00	98.12	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1601806803
95.00	0.04	94.38	0.01	91.98	0.01	94.18	0.01			94.10	0.01	97.20	0.17	98.13	0.01	/workspace/coverage/default/50.chip_sw_all_escalation_resets.434297923
95.03	0.04	94.38	0.01	91.99	0.01	94.19	0.01			94.11	0.01	97.38	0.17	98.14	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.2304383544
95.07	0.03	94.38	0.00	92.20	0.21	94.19	0.00			94.11	0.00	97.38	0.00	98.14	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.931914832
95.10	0.03	94.38	0.00	92.20	0.00	94.22	0.03			94.11	0.00	97.55	0.17	98.14	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3006767783
95.14	0.03	94.38	0.00	92.40	0.19	94.22	0.00			94.11	0.00	97.55	0.00	98.16	0.01	/workspace/coverage/cover_reg_top/4.chip_tl_errors.1861152543
95.17	0.03	94.38	0.00	92.41	0.02	94.22	0.00			94.11	0.00	97.55	0.00	98.34	0.19	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.446962501
95.20	0.03	94.42	0.04	92.45	0.04	94.30	0.08			94.15	0.04	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3863375825
95.23	0.03	94.42	0.00	92.45	0.00	94.48	0.18			94.15	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3260562471
95.26	0.03	94.49	0.07	92.45	0.00	94.57	0.09			94.16	0.01	97.55	0.00	98.34	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.1236356607
95.29	0.03	94.56	0.07	92.48	0.03	94.58	0.01			94.21	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3872048435
95.31	0.02	94.63	0.07	92.53	0.05	94.58	0.00			94.24	0.03	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3308580163
95.33	0.02	94.63	0.01	92.53	0.01	94.71	0.13			94.24	0.00	97.55	0.00	98.34	0.00	/workspace/coverage/default/51.chip_sw_all_escalation_resets.1791894808
95.36	0.02	94.66	0.02	92.59	0.06	94.71	0.00			94.29	0.05	97.55	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1118231913
95.38	0.02	94.66	0.00	92.59	0.00	94.71	0.00			94.29	0.00	97.55	0.00	98.46	0.12	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2083557708
95.40	0.02	94.66	0.00	92.59	0.00	94.82	0.12			94.29	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2145954702
95.41	0.02	94.66	0.00	92.69	0.09	94.82	0.00			94.29	0.00	97.55	0.00	98.47	0.01	/workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.399811134
95.43	0.02	94.66	0.01	92.73	0.04	94.82	0.00			94.34	0.05	97.55	0.00	98.47	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2876379229
95.44	0.01	94.66	0.00	92.80	0.07	94.82	0.00			94.35	0.02	97.55	0.00	98.47	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1001145893
95.46	0.01	94.66	0.00	92.87	0.07	94.82	0.00			94.35	0.00	97.55	0.00	98.48	0.01	/workspace/coverage/cover_reg_top/10.chip_tl_errors.4017837988
95.47	0.01	94.66	0.00	92.89	0.01	94.82	0.00			94.35	0.00	97.55	0.00	98.55	0.07	/workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.2862361129
95.49	0.01	94.66	0.00	92.91	0.02	94.82	0.00			94.37	0.02	97.55	0.00	98.60	0.05	/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1261243387
95.50	0.01	94.66	0.00	92.91	0.00	94.90	0.08			94.37	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3439907912
95.51	0.01	94.66	0.00	92.91	0.00	94.98	0.07			94.37	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.611059377
95.52	0.01	94.66	0.00	92.98	0.07	94.98	0.00			94.37	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.176148486
95.54	0.01	94.66	0.00	93.01	0.03	94.98	0.00			94.39	0.02	97.55	0.00	98.63	0.02	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.2554283816
95.55	0.01	94.66	0.00	93.08	0.07	94.98	0.00			94.39	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1449393560
95.56	0.01	94.66	0.00	93.08	0.00	95.03	0.06			94.39	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1955877515
95.56	0.01	94.66	0.00	93.13	0.05	95.03	0.00			94.39	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3860266927
95.57	0.01	94.69	0.02	93.14	0.01	95.04	0.01			94.40	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3299463510
95.58	0.01	94.70	0.02	93.15	0.01	95.05	0.01			94.42	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.4115772970
95.59	0.01	94.70	0.00	93.16	0.01	95.05	0.00			94.42	0.00	97.55	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.3058895007
95.60	0.01	94.71	0.01	93.19	0.03	95.06	0.01			94.42	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.156369425
95.60	0.01	94.71	0.00	93.23	0.04	95.06	0.00			94.42	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1135285730
95.61	0.01	94.71	0.00	93.23	0.00	95.10	0.04			94.42	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3670337008
95.62	0.01	94.71	0.00	93.27	0.04	95.10	0.00			94.42	0.00	97.55	0.00	98.66	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.3003272959
95.62	0.01	94.71	0.00	93.27	0.01	95.10	0.00			94.42	0.00	97.55	0.00	98.70	0.04	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1913679450
95.63	0.01	94.71	0.01	93.29	0.02	95.11	0.01			94.42	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.268195202
95.64	0.01	94.71	0.00	93.31	0.01	95.11	0.00			94.42	0.00	97.55	0.00	98.72	0.02	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.3272470207
95.64	0.01	94.71	0.00	93.31	0.00	95.11	0.00			94.42	0.00	97.55	0.00	98.75	0.04	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.1416273698
95.65	0.01	94.71	0.00	93.33	0.02	95.11	0.00			94.42	0.00	97.55	0.00	98.77	0.01	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2412895156
95.65	0.01	94.71	0.00	93.33	0.00	95.15	0.03			94.42	0.00	97.55	0.00	98.77	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1666169315
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95.70	0.01	94.72	0.00	93.42	0.01	95.28	0.00			94.43	0.02	97.55	0.00	98.79	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1715713623
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95.71	0.01	94.74	0.01	93.47	0.00	95.29	0.01			94.43	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.1765668762
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95.73	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3969341781
95.73	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2584670132
95.73	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3574797925
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95.76	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2712113302
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95.77	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.2486727520
95.77	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/27.chip_sw_all_escalation_resets.4038342624
95.78	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.3545931163
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95.79	0.01	94.74	0.00	93.50	0.00	95.31	0.00			94.43	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/33.chip_sw_all_escalation_resets.2230564489
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95.85	0.01	94.74	0.00	93.50	0.00	95.32	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1282110937
95.85	0.01	94.74	0.00	93.51	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_tl_errors.3511664270
95.86	0.01	94.74	0.00	93.52	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all.272421632
95.86	0.01	94.74	0.00	93.53	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.4144966031
95.86	0.01	94.74	0.00	93.54	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3578303246
95.86	0.01	94.74	0.00	93.55	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_pattgen_ios.2101586440
95.86	0.01	94.74	0.00	93.57	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.4015019680
95.86	0.01	94.74	0.00	93.58	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_gpio.2220878893
95.87	0.01	94.74	0.01	93.58	0.01	95.32	0.00			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2798732214
95.87	0.01	94.74	0.00	93.58	0.00	95.33	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4015607990
95.87	0.01	94.74	0.00	93.58	0.00	95.34	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2329664134
95.87	0.01	94.74	0.00	93.58	0.00	95.35	0.01			94.43	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2966831063
95.87	0.01	94.74	0.00	93.58	0.00	95.35	0.00			94.44	0.01	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3444411744
95.87	0.01	94.74	0.00	93.59	0.01	95.35	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2636594931
95.87	0.01	94.74	0.00	93.60	0.01	95.35	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/14.xbar_stress_all.2889477540
95.88	0.01	94.74	0.00	93.60	0.01	95.35	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/17.xbar_access_same_device.3699028460
95.88	0.01	94.74	0.00	93.61	0.01	95.35	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.836244889
95.88	0.01	94.74	0.00	93.62	0.01	95.35	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1155636801
95.88	0.01	94.74	0.00	93.63	0.01	95.35	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2727102533
95.88	0.01	94.74	0.00	93.63	0.00	95.36	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.850559705
95.88	0.01	94.74	0.00	93.63	0.00	95.36	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.339006908
95.88	0.01	94.74	0.00	93.63	0.00	95.36	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2905769364
95.88	0.01	94.74	0.00	93.63	0.00	95.37	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3438198787
95.88	0.01	94.74	0.00	93.63	0.00	95.37	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.1673764917
95.88	0.01	94.74	0.00	93.63	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.1433773389
95.88	0.01	94.74	0.00	93.63	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1054732608
95.89	0.01	94.74	0.00	93.64	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.401971448
95.89	0.01	94.74	0.00	93.64	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/25.chip_tl_errors.3117755864
95.89	0.01	94.74	0.00	93.64	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1835946752
95.89	0.01	94.74	0.00	93.65	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.3261440606
95.89	0.01	94.74	0.00	93.65	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1823727203
95.89	0.01	94.74	0.00	93.65	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.688554556
95.89	0.01	94.74	0.00	93.66	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/86.xbar_error_random.4246367527
95.89	0.01	94.74	0.00	93.66	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.1719020766
95.89	0.01	94.74	0.00	93.66	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sival_flash_info_access.4238464361
95.89	0.01	94.74	0.00	93.67	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_gpio.1730527307
95.89	0.01	94.74	0.00	93.67	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1166956205
95.89	0.01	94.74	0.00	93.67	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2049903136
95.89	0.01	94.74	0.00	93.68	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_hmac_enc.1819304521
95.89	0.01	94.74	0.00	93.68	0.01	95.37	0.00			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1040400968
95.89	0.01	94.74	0.00	93.68	0.00	95.38	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.2930700306
95.89	0.01	94.74	0.00	93.68	0.00	95.38	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.305461116
95.89	0.01	94.74	0.00	93.68	0.00	95.38	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.790622550
95.89	0.01	94.74	0.00	93.68	0.00	95.38	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2909056697
95.90	0.01	94.74	0.00	93.68	0.00	95.39	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.81673798
95.90	0.01	94.74	0.00	93.68	0.00	95.39	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2358463615
95.90	0.01	94.74	0.00	93.68	0.00	95.39	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.176258419
95.90	0.01	94.74	0.00	93.68	0.00	95.39	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.436245665
95.90	0.01	94.74	0.00	93.68	0.00	95.40	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.32471923
95.90	0.01	94.74	0.00	93.68	0.00	95.40	0.01			94.44	0.00	97.55	0.00	99.57	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3859835192

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3732082097
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.345999291
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.194181592
/workspace/coverage/cover_reg_top/0.chip_csr_rw.930159120
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.513160568
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.2925305539
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.1086874827
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2411272530
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2049744444
/workspace/coverage/cover_reg_top/0.xbar_error_random.1383031595
/workspace/coverage/cover_reg_top/0.xbar_random.3123829497
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2414336970
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.2685942818
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2221841167
/workspace/coverage/cover_reg_top/0.xbar_same_source.2094631484
/workspace/coverage/cover_reg_top/0.xbar_smoke.3753368316
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2458842555
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.1929715364
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.152033155
/workspace/coverage/cover_reg_top/0.xbar_stress_all.987647774
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3049763914
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1425692302
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2305461704
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1090887726
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.2524104990
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.565247442
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1602948181
/workspace/coverage/cover_reg_top/1.chip_csr_rw.1661556613
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2954372133
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1229715476
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1326106482
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2313518649
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3909789417
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.77598921
/workspace/coverage/cover_reg_top/1.xbar_error_random.3176984704
/workspace/coverage/cover_reg_top/1.xbar_random.2125846006
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1381974755
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1530843675
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2050922959
/workspace/coverage/cover_reg_top/1.xbar_same_source.2848647728
/workspace/coverage/cover_reg_top/1.xbar_smoke.2756913751
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3298289467
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.1497108850
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2841698559
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2180768061
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1640188269
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.158308282
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1093791707
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3210325890
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3947036790
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2238794978
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4091427894
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1380024679
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1108382108
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.450464068
/workspace/coverage/cover_reg_top/10.xbar_error_random.2244396926
/workspace/coverage/cover_reg_top/10.xbar_random.3725464653
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.459767725
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3552452568
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.3348518990
/workspace/coverage/cover_reg_top/10.xbar_same_source.522384029
/workspace/coverage/cover_reg_top/10.xbar_smoke.2573564645
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3369215164
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3137721854
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.364158626
/workspace/coverage/cover_reg_top/10.xbar_stress_all.804590765
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3517218641
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.3767585926
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1593043796
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1612071989
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1078227609
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3403618205
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2694615912
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3060665087
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1027578441
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2616679266
/workspace/coverage/cover_reg_top/11.xbar_error_random.3756115510
/workspace/coverage/cover_reg_top/11.xbar_random.1361421583
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3200661343
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.836886834
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1885779649
/workspace/coverage/cover_reg_top/11.xbar_same_source.498719296
/workspace/coverage/cover_reg_top/11.xbar_smoke.245051492
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.868768710
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2188703417
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.493129507
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.1075648566
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.436197195
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.5279645
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3618069421
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2408026539
/workspace/coverage/cover_reg_top/12.chip_csr_rw.2240970446
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2019530078
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.2571871724
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.3076529102
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2357515381
/workspace/coverage/cover_reg_top/12.xbar_error_random.1644762922
/workspace/coverage/cover_reg_top/12.xbar_random.530958653
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1935424897
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2735834100
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1735215569
/workspace/coverage/cover_reg_top/12.xbar_same_source.605277369
/workspace/coverage/cover_reg_top/12.xbar_smoke.2356039195
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2602423905
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3542564861
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.4289978049
/workspace/coverage/cover_reg_top/12.xbar_stress_all.2650852666
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1072891719
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3794614894
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2677159556
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2322275391
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.1649573589
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3298689433
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1553000975
/workspace/coverage/cover_reg_top/13.chip_tl_errors.4101452538
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.3758923681
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2344006224
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1598398414
/workspace/coverage/cover_reg_top/13.xbar_error_random.4074874585
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/workspace/coverage/default/22.chip_sw_all_escalation_resets.1758632282
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/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410507655
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/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3435537905
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/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3600922523
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/workspace/coverage/default/3.chip_tap_straps_testunlock0.3735154799
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.424449836
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3727377188
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2112073384
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755631045
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1402466393
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.73950753
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2363890867
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.1123044993
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.263115543
/workspace/coverage/default/39.chip_sw_all_escalation_resets.2214437180
/workspace/coverage/default/4.chip_sw_all_escalation_resets.152245249
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1825541645
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.3031116672
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1286720775
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.553512407
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2220092618
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2935845820
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3367234735
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2062601739
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2191318070
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2242234240
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3071078838
/workspace/coverage/default/4.chip_tap_straps_dev.97310692
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/workspace/coverage/default/41.chip_sw_all_escalation_resets.4003556288
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2967490705
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3770412825
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.341728364
/workspace/coverage/default/43.chip_sw_all_escalation_resets.131566206
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.110469053
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1726603601
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.857500921
/workspace/coverage/default/46.chip_sw_all_escalation_resets.330179006
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2664666613
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3015142783
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788453283
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2627831652
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.1255357977
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3278690242
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3331171064
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3061208393
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2124876824
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2993522563
/workspace/coverage/default/52.chip_sw_all_escalation_resets.929161607
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1064470278
/workspace/coverage/default/54.chip_sw_all_escalation_resets.482829051
/workspace/coverage/default/55.chip_sw_all_escalation_resets.4074692110
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3273360932
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.533882620
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1801805485
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196212199
/workspace/coverage/default/58.chip_sw_all_escalation_resets.4138960982
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634744508
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1283276165
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174822428
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1306654235
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.4212505191
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3771930283
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2360943478
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.512420414
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1047693887
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2950343068
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230195611
/workspace/coverage/default/62.chip_sw_all_escalation_resets.1707134930
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2647251509
/workspace/coverage/default/63.chip_sw_all_escalation_resets.859662798
/workspace/coverage/default/64.chip_sw_all_escalation_resets.985667212
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3009891162
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1358104220
/workspace/coverage/default/66.chip_sw_all_escalation_resets.641383049
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416988729
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3001891684
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2484639593
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.448328295
/workspace/coverage/default/7.chip_sw_all_escalation_resets.397428628
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2827385647
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3960431973
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2600366607
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.154440509
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2783834054
/workspace/coverage/default/71.chip_sw_all_escalation_resets.200643165
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3623066091
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2898836696
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2919204349
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3784349069
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082306474
/workspace/coverage/default/75.chip_sw_all_escalation_resets.808213291
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.578862150
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3139287650
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1209569832
/workspace/coverage/default/77.chip_sw_all_escalation_resets.2573306774
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2816742232
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.636911271
/workspace/coverage/default/79.chip_sw_all_escalation_resets.287592442
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3356097433
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2245386044
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1885184522
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2170400196
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3853236304
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.43259531
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3630504241
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1453253675
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327877123
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2165309273
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.382217682
/workspace/coverage/default/85.chip_sw_all_escalation_resets.4048497817
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3149110447
/workspace/coverage/default/86.chip_sw_all_escalation_resets.238502476
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.404187830
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.388770280
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1964096369
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.350771857
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3419677418
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3805644401
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1363553620
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1481556370
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2880584152
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2134176105
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2927789822
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2010307149
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3192382326
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2200309757
/workspace/coverage/default/96.chip_sw_all_escalation_resets.52039121
/workspace/coverage/default/97.chip_sw_all_escalation_resets.2662087776
/workspace/coverage/default/98.chip_sw_all_escalation_resets.601162066
/workspace/coverage/default/99.chip_sw_all_escalation_resets.595522149
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3561234847
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.585873058
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.860084973
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2325534800
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3854272278
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1127870023
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3346083230
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.2240381374

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Total test records in report: 2933

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.1009283985			Jul 28 08:34:46 PM PDT 24	Jul 28 08:41:03 PM PDT 24	3460168108 ps
T2	/workspace/coverage/default/3.chip_sw_all_escalation_resets.4181564691			Jul 28 08:30:04 PM PDT 24	Jul 28 08:39:23 PM PDT 24	5613933694 ps
T3	/workspace/coverage/default/2.chip_sw_gpio_smoketest.1402848194			Jul 28 08:29:55 PM PDT 24	Jul 28 08:35:53 PM PDT 24	2743086299 ps
T85	/workspace/coverage/default/0.chip_sw_hmac_multistream.2287080772			Jul 28 08:06:33 PM PDT 24	Jul 28 08:32:19 PM PDT 24	7220446760 ps
T86	/workspace/coverage/default/2.chip_sw_kmac_entropy.558879775			Jul 28 08:23:31 PM PDT 24	Jul 28 08:29:44 PM PDT 24	2933040320 ps
T87	/workspace/coverage/default/1.chip_sw_example_rom.2662254515			Jul 28 08:08:54 PM PDT 24	Jul 28 08:10:45 PM PDT 24	2422764392 ps
T5	/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.824524958			Jul 28 08:22:59 PM PDT 24	Jul 28 08:58:30 PM PDT 24	33652254968 ps
T4	/workspace/coverage/default/74.chip_sw_all_escalation_resets.2243687074			Jul 28 08:40:02 PM PDT 24	Jul 28 08:48:56 PM PDT 24	5022915600 ps
T60	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2060123554			Jul 28 08:36:25 PM PDT 24	Jul 28 08:48:10 PM PDT 24	5955112988 ps
T42	/workspace/coverage/default/2.rom_e2e_asm_init_prod.2529578082			Jul 28 08:33:25 PM PDT 24	Jul 28 09:44:33 PM PDT 24	15628650931 ps
T6	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1955877515			Jul 28 08:14:30 PM PDT 24	Jul 28 09:44:58 PM PDT 24	23235619438 ps
T7	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2593935324			Jul 28 08:25:03 PM PDT 24	Jul 28 11:14:05 PM PDT 24	57795433253 ps
T185	/workspace/coverage/default/51.chip_sw_all_escalation_resets.1791894808			Jul 28 08:35:49 PM PDT 24	Jul 28 08:44:57 PM PDT 24	4663694640 ps
T169	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.587746236			Jul 28 08:26:58 PM PDT 24	Jul 28 08:47:52 PM PDT 24	9196905560 ps
T387	/workspace/coverage/default/0.chip_sw_uart_smoketest.1392128420			Jul 28 08:15:42 PM PDT 24	Jul 28 08:20:45 PM PDT 24	3074197572 ps
T16	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1253033549			Jul 28 08:30:42 PM PDT 24	Jul 28 08:51:35 PM PDT 24	21413045596 ps
T45	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3439907912			Jul 28 08:18:20 PM PDT 24	Jul 28 08:30:22 PM PDT 24	4809704808 ps
T101	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.672083155			Jul 28 08:26:42 PM PDT 24	Jul 28 08:44:32 PM PDT 24	12188471722 ps
T102	/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3950552355			Jul 28 08:26:12 PM PDT 24	Jul 28 08:36:04 PM PDT 24	3271168788 ps
T103	/workspace/coverage/default/0.chip_plic_all_irqs_20.1110084986			Jul 28 08:07:00 PM PDT 24	Jul 28 08:18:47 PM PDT 24	3968922688 ps
T104	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3087719095			Jul 28 08:08:52 PM PDT 24	Jul 28 08:25:17 PM PDT 24	5954010068 ps
T83	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2538162532			Jul 28 08:21:42 PM PDT 24	Jul 28 11:54:53 PM PDT 24	78735018498 ps
T105	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.1484426031			Jul 28 08:31:23 PM PDT 24	Jul 28 08:35:24 PM PDT 24	2258688235 ps
T44	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2524607117			Jul 28 08:32:25 PM PDT 24	Jul 28 08:51:45 PM PDT 24	12001616288 ps
T106	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3969341781			Jul 28 08:32:39 PM PDT 24	Jul 28 08:39:03 PM PDT 24	3692294408 ps
T64	/workspace/coverage/default/1.rom_raw_unlock.1665494095			Jul 28 08:19:56 PM PDT 24	Jul 28 08:24:35 PM PDT 24	6086071791 ps
T202	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.767336843			Jul 28 08:25:17 PM PDT 24	Jul 28 08:57:34 PM PDT 24	8408989844 ps
T61	/workspace/coverage/default/0.chip_tap_straps_testunlock0.825614657			Jul 28 08:11:10 PM PDT 24	Jul 28 08:17:05 PM PDT 24	4387247384 ps
T159	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.409385458			Jul 28 08:10:37 PM PDT 24	Jul 28 08:35:20 PM PDT 24	7335183256 ps
T208	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2817043882			Jul 28 08:06:59 PM PDT 24	Jul 28 08:20:48 PM PDT 24	5074421864 ps
T305	/workspace/coverage/default/1.chip_sw_kmac_idle.1992482653			Jul 28 08:18:58 PM PDT 24	Jul 28 08:23:10 PM PDT 24	2910052450 ps
T118	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4047135046			Jul 28 08:14:30 PM PDT 24	Jul 28 08:18:44 PM PDT 24	2288200442 ps
T394	/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.96448856			Jul 28 08:37:13 PM PDT 24	Jul 28 08:42:11 PM PDT 24	3785927160 ps
T160	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2145492420			Jul 28 08:24:06 PM PDT 24	Jul 28 08:43:54 PM PDT 24	6859615096 ps
T214	/workspace/coverage/default/79.chip_sw_all_escalation_resets.287592442			Jul 28 08:39:43 PM PDT 24	Jul 28 08:50:00 PM PDT 24	4221263848 ps
T43	/workspace/coverage/default/1.rom_e2e_static_critical.3636324719			Jul 28 08:24:12 PM PDT 24	Jul 28 09:34:47 PM PDT 24	17138024220 ps
T932	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1701016531			Jul 28 08:18:18 PM PDT 24	Jul 28 08:24:35 PM PDT 24	2840025848 ps
T151	/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3210423189			Jul 28 08:22:53 PM PDT 24	Jul 28 09:53:02 PM PDT 24	46905603186 ps
T108	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3201341836			Jul 28 08:18:58 PM PDT 24	Jul 28 09:15:28 PM PDT 24	23322681239 ps
T413	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3784349069			Jul 28 08:37:46 PM PDT 24	Jul 28 08:48:33 PM PDT 24	5174544232 ps
T78	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1161967516			Jul 28 08:26:26 PM PDT 24	Jul 28 08:43:02 PM PDT 24	9331704772 ps
T409	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3025980683			Jul 28 08:15:29 PM PDT 24	Jul 28 09:15:51 PM PDT 24	14927585660 ps
T933	/workspace/coverage/default/0.chip_sw_example_rom.84784969			Jul 28 08:05:17 PM PDT 24	Jul 28 08:07:41 PM PDT 24	2784050320 ps
T14	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.156369425			Jul 28 08:05:34 PM PDT 24	Jul 28 08:16:42 PM PDT 24	3942367648 ps
T356	/workspace/coverage/default/0.chip_sw_flash_crash_alert.2683932876			Jul 28 08:08:54 PM PDT 24	Jul 28 08:19:27 PM PDT 24	4706932880 ps
T136	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1793965487			Jul 28 08:05:56 PM PDT 24	Jul 28 08:17:00 PM PDT 24	4050105520 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3056374356			Jul 28 08:13:06 PM PDT 24	Jul 28 09:19:11 PM PDT 24	15369019223 ps
T215	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.601755044			Jul 28 08:08:17 PM PDT 24	Jul 28 08:46:49 PM PDT 24	11316214192 ps
T145	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3404363006			Jul 28 08:07:09 PM PDT 24	Jul 28 08:39:39 PM PDT 24	13470146794 ps
T74	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1264712780			Jul 28 08:09:53 PM PDT 24	Jul 28 08:45:31 PM PDT 24	11456985506 ps
T748	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2647251509			Jul 28 08:37:06 PM PDT 24	Jul 28 08:42:51 PM PDT 24	4004110450 ps
T252	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.176258419			Jul 28 08:06:29 PM PDT 24	Jul 28 08:34:13 PM PDT 24	12164855424 ps
T109	/workspace/coverage/default/2.chip_sw_power_sleep_load.1275218370			Jul 28 08:27:42 PM PDT 24	Jul 28 08:36:47 PM PDT 24	11008234544 ps
T132	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1694771610			Jul 28 08:07:12 PM PDT 24	Jul 28 08:11:31 PM PDT 24	2478057601 ps
T934	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1765439718			Jul 28 08:18:11 PM PDT 24	Jul 28 08:24:52 PM PDT 24	3532562364 ps
T210	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2987210376			Jul 28 08:35:52 PM PDT 24	Jul 28 09:16:08 PM PDT 24	12587878372 ps
T113	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1118231913			Jul 28 08:11:02 PM PDT 24	Jul 28 08:23:32 PM PDT 24	4904031371 ps
T20	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3958205532			Jul 28 08:05:22 PM PDT 24	Jul 28 08:33:10 PM PDT 24	22060652676 ps
T360	/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3035563077			Jul 28 08:05:08 PM PDT 24	Jul 28 08:16:53 PM PDT 24	5472001750 ps
T322	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1213678737			Jul 28 08:18:38 PM PDT 24	Jul 28 08:23:00 PM PDT 24	3426234066 ps
T184	/workspace/coverage/default/4.chip_tap_straps_prod.87844936			Jul 28 08:30:23 PM PDT 24	Jul 28 08:33:15 PM PDT 24	2930063867 ps
T935	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.42523994			Jul 28 08:28:53 PM PDT 24	Jul 28 08:36:41 PM PDT 24	2911750760 ps
T751	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.158948599			Jul 28 08:30:20 PM PDT 24	Jul 28 08:44:30 PM PDT 24	6984012092 ps
T334	/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1876943699			Jul 28 08:32:26 PM PDT 24	Jul 28 09:08:07 PM PDT 24	9186365916 ps
T365	/workspace/coverage/default/96.chip_sw_all_escalation_resets.52039121			Jul 28 08:40:20 PM PDT 24	Jul 28 08:49:54 PM PDT 24	4577513560 ps
T129	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3299463510			Jul 28 08:10:32 PM PDT 24	Jul 28 08:19:28 PM PDT 24	4244115212 ps
T114	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3545065843			Jul 28 08:16:27 PM PDT 24	Jul 28 08:27:15 PM PDT 24	4569625720 ps
T462	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2435026896			Jul 28 08:24:39 PM PDT 24	Jul 28 08:28:49 PM PDT 24	2754521356 ps
T323	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.180642523			Jul 28 08:22:49 PM PDT 24	Jul 28 08:34:52 PM PDT 24	4639829816 ps
T742	/workspace/coverage/default/1.chip_sw_aes_enc.4008045688			Jul 28 08:14:57 PM PDT 24	Jul 28 08:20:32 PM PDT 24	3305490850 ps
T170	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1168826096			Jul 28 08:15:55 PM PDT 24	Jul 28 08:22:15 PM PDT 24	4857490760 ps
T166	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3837524017			Jul 28 08:18:01 PM PDT 24	Jul 28 08:21:59 PM PDT 24	2657508126 ps
T307	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2214437180			Jul 28 08:35:23 PM PDT 24	Jul 28 08:49:12 PM PDT 24	5991878100 ps
T402	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.2479899035			Jul 28 08:21:02 PM PDT 24	Jul 28 08:43:07 PM PDT 24	5805656280 ps
T403	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3929737783			Jul 28 08:06:43 PM PDT 24	Jul 28 08:11:06 PM PDT 24	3200538566 ps
T216	/workspace/coverage/default/64.chip_sw_all_escalation_resets.985667212			Jul 28 08:38:47 PM PDT 24	Jul 28 08:48:24 PM PDT 24	4595554134 ps
T268	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3480407324			Jul 28 08:24:29 PM PDT 24	Jul 28 08:26:11 PM PDT 24	2140227995 ps
T404	/workspace/coverage/default/78.chip_sw_all_escalation_resets.2816742232			Jul 28 08:40:02 PM PDT 24	Jul 28 08:51:06 PM PDT 24	5655255910 ps
T34	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1807890309			Jul 28 08:22:51 PM PDT 24	Jul 28 08:32:32 PM PDT 24	5977145526 ps
T201	/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1103062132			Jul 28 08:24:04 PM PDT 24	Jul 28 08:28:04 PM PDT 24	2777834990 ps
T405	/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2958293632			Jul 28 08:23:54 PM PDT 24	Jul 28 08:33:37 PM PDT 24	3898177200 ps
T357	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3859102675			Jul 28 08:36:25 PM PDT 24	Jul 28 08:46:36 PM PDT 24	5539269400 ps
T791	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.341728364			Jul 28 08:36:50 PM PDT 24	Jul 28 08:44:43 PM PDT 24	3141293928 ps
T936	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2170400196			Jul 28 08:31:14 PM PDT 24	Jul 28 09:13:55 PM PDT 24	12789345384 ps
T461	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3149110447			Jul 28 08:38:50 PM PDT 24	Jul 28 08:44:09 PM PDT 24	3353765856 ps
T937	/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1959693230			Jul 28 08:19:48 PM PDT 24	Jul 28 08:25:24 PM PDT 24	2908437470 ps
T938	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.3762107014			Jul 28 08:23:10 PM PDT 24	Jul 28 08:32:24 PM PDT 24	4541902002 ps
T747	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634744508			Jul 28 08:38:28 PM PDT 24	Jul 28 08:44:53 PM PDT 24	4098877182 ps
T757	/workspace/coverage/default/34.chip_sw_all_escalation_resets.1785430305			Jul 28 08:40:16 PM PDT 24	Jul 28 08:49:47 PM PDT 24	4997596640 ps
T115	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2098437456			Jul 28 08:27:12 PM PDT 24	Jul 28 08:40:07 PM PDT 24	3781976416 ps
T17	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3382204545			Jul 28 08:12:29 PM PDT 24	Jul 28 08:20:16 PM PDT 24	7956742214 ps
T772	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.857500921			Jul 28 08:35:50 PM PDT 24	Jul 28 08:42:57 PM PDT 24	3444156440 ps
T939	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3438198787			Jul 28 08:07:55 PM PDT 24	Jul 28 08:14:46 PM PDT 24	6027555608 ps
T715	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3273360932			Jul 28 08:36:00 PM PDT 24	Jul 28 08:42:52 PM PDT 24	3787665912 ps
T131	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.166417091			Jul 28 08:29:10 PM PDT 24	Jul 28 08:36:55 PM PDT 24	6184773760 ps
T385	/workspace/coverage/default/2.rom_e2e_asm_init_dev.1791109254			Jul 28 08:34:41 PM PDT 24	Jul 28 09:27:11 PM PDT 24	15750505941 ps
T792	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.4174822428			Jul 28 08:31:50 PM PDT 24	Jul 28 08:38:26 PM PDT 24	3854488928 ps
T758	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755631045			Jul 28 08:34:00 PM PDT 24	Jul 28 08:40:04 PM PDT 24	3752699984 ps
T940	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3204278027			Jul 28 08:08:01 PM PDT 24	Jul 28 08:14:57 PM PDT 24	5223026266 ps
T116	/workspace/coverage/default/1.chip_sw_edn_boot_mode.489507374			Jul 28 08:13:16 PM PDT 24	Jul 28 08:22:42 PM PDT 24	2840110736 ps
T340	/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1794868528			Jul 28 08:29:49 PM PDT 24	Jul 28 08:33:14 PM PDT 24	3223500308 ps
T398	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.263115543			Jul 28 08:35:36 PM PDT 24	Jul 28 08:43:45 PM PDT 24	4107473976 ps
T941	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3697374143			Jul 28 08:29:11 PM PDT 24	Jul 28 08:37:18 PM PDT 24	4979281448 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.861251126			Jul 28 08:17:44 PM PDT 24	Jul 28 08:45:33 PM PDT 24	22956708424 ps
T255	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1918928427			Jul 28 08:08:06 PM PDT 24	Jul 28 10:09:21 PM PDT 24	27136586168 ps
T942	/workspace/coverage/default/0.chip_sw_edn_sw_mode.1113373999			Jul 28 08:06:13 PM PDT 24	Jul 28 08:40:13 PM PDT 24	9320210846 ps
T756	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1106412473			Jul 28 08:12:51 PM PDT 24	Jul 28 08:38:13 PM PDT 24	13984548242 ps
T943	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2271002480			Jul 28 08:12:50 PM PDT 24	Jul 28 08:36:18 PM PDT 24	5688592531 ps
T944	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.1763806671			Jul 28 08:24:56 PM PDT 24	Jul 28 08:28:21 PM PDT 24	2607233634 ps
T269	/workspace/coverage/default/0.rom_volatile_raw_unlock.2287307350			Jul 28 08:12:07 PM PDT 24	Jul 28 08:14:31 PM PDT 24	2896019925 ps
T241	/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1470364586			Jul 28 08:18:43 PM PDT 24	Jul 28 08:58:23 PM PDT 24	21111494894 ps
T270	/workspace/coverage/default/1.rom_volatile_raw_unlock.4184543967			Jul 28 08:20:31 PM PDT 24	Jul 28 08:22:38 PM PDT 24	2491214270 ps
T176	/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.531651779			Jul 28 08:13:26 PM PDT 24	Jul 28 09:47:12 PM PDT 24	48257584560 ps
T945	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3588369280			Jul 28 08:22:14 PM PDT 24	Jul 28 08:26:07 PM PDT 24	2863949460 ps
T120	/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2220092618			Jul 28 08:31:15 PM PDT 24	Jul 28 08:46:15 PM PDT 24	7773000602 ps
T156	/workspace/coverage/default/0.chip_sw_flash_init.4158702616			Jul 28 08:05:46 PM PDT 24	Jul 28 08:43:41 PM PDT 24	24677863430 ps
T709	/workspace/coverage/default/1.chip_sw_aes_masking_off.329102444			Jul 28 08:14:06 PM PDT 24	Jul 28 08:19:54 PM PDT 24	3373506131 ps
T167	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1282110937			Jul 28 08:07:13 PM PDT 24	Jul 28 08:23:23 PM PDT 24	7739148843 ps
T759	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3030509982			Jul 28 08:38:42 PM PDT 24	Jul 28 08:45:41 PM PDT 24	4026214292 ps
T117	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3438146891			Jul 28 08:14:21 PM PDT 24	Jul 28 08:25:50 PM PDT 24	5853093637 ps
T820	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269409574			Jul 28 08:36:41 PM PDT 24	Jul 28 08:42:47 PM PDT 24	3584861250 ps
T946	/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2021569420			Jul 28 08:15:03 PM PDT 24	Jul 28 08:19:42 PM PDT 24	3024563580 ps
T754	/workspace/coverage/default/93.chip_sw_all_escalation_resets.3192382326			Jul 28 08:39:19 PM PDT 24	Jul 28 08:49:57 PM PDT 24	5146407928 ps
T793	/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230195611			Jul 28 08:38:22 PM PDT 24	Jul 28 08:44:29 PM PDT 24	3545652640 ps
T783	/workspace/coverage/default/27.chip_sw_all_escalation_resets.4038342624			Jul 28 08:34:29 PM PDT 24	Jul 28 08:45:40 PM PDT 24	4898624120 ps
T358	/workspace/coverage/default/47.chip_sw_all_escalation_resets.4257282079			Jul 28 08:36:12 PM PDT 24	Jul 28 08:48:15 PM PDT 24	5721929200 ps
T463	/workspace/coverage/default/0.chip_sw_kmac_entropy.3169960247			Jul 28 08:06:50 PM PDT 24	Jul 28 08:12:42 PM PDT 24	3295673500 ps
T209	/workspace/coverage/default/0.chip_sw_pattgen_ios.2983927514			Jul 28 08:10:30 PM PDT 24	Jul 28 08:16:13 PM PDT 24	3649076880 ps
T353	/workspace/coverage/default/1.chip_sival_flash_info_access.302123549			Jul 28 08:13:31 PM PDT 24	Jul 28 08:19:30 PM PDT 24	3169248068 ps
T112	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4114226127			Jul 28 08:08:45 PM PDT 24	Jul 28 08:42:32 PM PDT 24	11059368974 ps
T947	/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2900031923			Jul 28 08:07:45 PM PDT 24	Jul 28 08:26:07 PM PDT 24	5529883040 ps
T236	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.4291223040			Jul 28 08:15:23 PM PDT 24	Jul 28 08:24:33 PM PDT 24	4230656120 ps
T149	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2905769364			Jul 28 08:09:29 PM PDT 24	Jul 28 08:13:37 PM PDT 24	2643827627 ps
T217	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1687081061			Jul 28 08:26:04 PM PDT 24	Jul 28 08:45:34 PM PDT 24	6522953704 ps
T289	/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2063752836			Jul 28 08:26:07 PM PDT 24	Jul 28 08:30:28 PM PDT 24	2456976460 ps
T290	/workspace/coverage/default/0.chip_sival_flash_info_access.4238464361			Jul 28 08:06:48 PM PDT 24	Jul 28 08:13:08 PM PDT 24	3571694040 ps
T291	/workspace/coverage/default/8.chip_sw_all_escalation_resets.729198614			Jul 28 08:31:31 PM PDT 24	Jul 28 08:44:23 PM PDT 24	5276164584 ps
T31	/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3200073046			Jul 28 08:10:57 PM PDT 24	Jul 28 08:16:29 PM PDT 24	3629430144 ps
T292	/workspace/coverage/default/38.chip_sw_all_escalation_resets.708826459			Jul 28 08:36:20 PM PDT 24	Jul 28 08:45:55 PM PDT 24	5238224674 ps
T293	/workspace/coverage/default/12.chip_sw_all_escalation_resets.1586848859			Jul 28 08:31:46 PM PDT 24	Jul 28 08:42:07 PM PDT 24	5668608808 ps
T294	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3958386157			Jul 28 08:12:27 PM PDT 24	Jul 28 08:22:09 PM PDT 24	6533111523 ps
T386	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2302250117			Jul 28 08:14:07 PM PDT 24	Jul 28 10:01:15 PM PDT 24	24202639160 ps
T271	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1352636425			Jul 28 08:08:19 PM PDT 24	Jul 28 08:10:33 PM PDT 24	2350207466 ps
T41	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2781140883			Jul 28 08:14:18 PM PDT 24	Jul 28 09:48:33 PM PDT 24	23674220392 ps
T205	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.342137614			Jul 28 08:20:58 PM PDT 24	Jul 28 08:36:08 PM PDT 24	5506838186 ps
T137	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4101093621			Jul 28 08:24:50 PM PDT 24	Jul 28 09:24:20 PM PDT 24	17530522012 ps
T144	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3785023696			Jul 28 08:25:23 PM PDT 24	Jul 28 11:49:09 PM PDT 24	255304891564 ps
T344	/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1040400968			Jul 28 08:20:53 PM PDT 24	Jul 28 08:31:51 PM PDT 24	4059614278 ps
T779	/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2505218783			Jul 28 08:16:30 PM PDT 24	Jul 28 08:22:39 PM PDT 24	3040329928 ps
T368	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2529983962			Jul 28 08:12:11 PM PDT 24	Jul 28 08:18:13 PM PDT 24	3206607480 ps
T203	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2161909561			Jul 28 08:34:26 PM PDT 24	Jul 28 08:41:38 PM PDT 24	3229132000 ps
T213	/workspace/coverage/default/0.chip_tap_straps_dev.3797453609			Jul 28 08:10:54 PM PDT 24	Jul 28 08:13:20 PM PDT 24	2477244393 ps
T948	/workspace/coverage/default/2.chip_sw_uart_smoketest.3926872584			Jul 28 08:28:46 PM PDT 24	Jul 28 08:35:30 PM PDT 24	2660283656 ps
T949	/workspace/coverage/default/0.chip_sw_kmac_smoketest.4005172082			Jul 28 08:12:44 PM PDT 24	Jul 28 08:16:52 PM PDT 24	2897726498 ps
T749	/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.973176113			Jul 28 08:28:32 PM PDT 24	Jul 28 08:59:51 PM PDT 24	22494769774 ps
T15	/workspace/coverage/default/1.chip_sw_gpio_smoketest.2226613971			Jul 28 08:22:59 PM PDT 24	Jul 28 08:27:00 PM PDT 24	2693475393 ps
T950	/workspace/coverage/default/0.rom_e2e_smoke.1402518754			Jul 28 08:19:53 PM PDT 24	Jul 28 09:23:48 PM PDT 24	15794856412 ps
T951	/workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.1054794796			Jul 28 08:14:40 PM PDT 24	Jul 28 08:19:04 PM PDT 24	2279054609 ps
T395	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1848375013			Jul 28 08:15:55 PM PDT 24	Jul 28 09:59:03 PM PDT 24	23931977210 ps
T781	/workspace/coverage/default/55.chip_sw_all_escalation_resets.4074692110			Jul 28 08:35:52 PM PDT 24	Jul 28 08:46:16 PM PDT 24	5279267348 ps
T253	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2961865753			Jul 28 08:10:44 PM PDT 24	Jul 28 08:44:30 PM PDT 24	10955868889 ps
T952	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.817893242			Jul 28 08:13:47 PM PDT 24	Jul 28 08:29:23 PM PDT 24	9533527400 ps
T247	/workspace/coverage/default/0.chip_sw_power_sleep_load.3850568180			Jul 28 08:07:55 PM PDT 24	Jul 28 08:14:47 PM PDT 24	4693788632 ps
T346	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1166956205			Jul 28 08:09:16 PM PDT 24	Jul 28 08:16:54 PM PDT 24	4358142880 ps
T79	/workspace/coverage/default/99.chip_sw_all_escalation_resets.595522149			Jul 28 08:39:37 PM PDT 24	Jul 28 08:48:30 PM PDT 24	4641861244 ps
T92	/workspace/coverage/default/0.rom_keymgr_functest.2837213618			Jul 28 08:10:33 PM PDT 24	Jul 28 08:16:47 PM PDT 24	3676369928 ps
T93	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2679678844			Jul 28 08:24:30 PM PDT 24	Jul 28 08:35:35 PM PDT 24	7671842544 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_config_host.3910744689			Jul 28 08:06:45 PM PDT 24	Jul 28 08:43:08 PM PDT 24	7903687150 ps
T94	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2866625600			Jul 28 08:20:37 PM PDT 24	Jul 28 08:56:29 PM PDT 24	9672252808 ps
T21	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3438960391			Jul 28 08:17:04 PM PDT 24	Jul 28 08:44:41 PM PDT 24	22842633232 ps
T95	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3518365897			Jul 28 08:12:43 PM PDT 24	Jul 28 08:18:56 PM PDT 24	4311738376 ps
T96	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1196816237			Jul 28 08:30:54 PM PDT 24	Jul 28 08:47:27 PM PDT 24	6593440728 ps
T97	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3554518042			Jul 28 08:22:30 PM PDT 24	Jul 28 08:25:37 PM PDT 24	3916632002 ps
T98	/workspace/coverage/default/0.chip_sw_edn_kat.852249102			Jul 28 08:09:11 PM PDT 24	Jul 28 08:20:37 PM PDT 24	3012282582 ps
T374	/workspace/coverage/default/25.chip_sw_all_escalation_resets.1423264704			Jul 28 08:33:41 PM PDT 24	Jul 28 08:45:42 PM PDT 24	5845972856 ps
T327	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2474228438			Jul 28 08:06:06 PM PDT 24	Jul 28 08:16:47 PM PDT 24	3833501200 ps
T379	/workspace/coverage/default/0.chip_sw_hmac_oneshot.560758229			Jul 28 08:08:34 PM PDT 24	Jul 28 08:14:56 PM PDT 24	3401915398 ps
T369	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.4077155824			Jul 28 08:13:57 PM PDT 24	Jul 28 09:02:22 PM PDT 24	40231742100 ps
T380	/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2454016787			Jul 28 08:11:54 PM PDT 24	Jul 28 08:34:14 PM PDT 24	9536616903 ps
T381	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3523128287			Jul 28 08:21:09 PM PDT 24	Jul 28 08:25:38 PM PDT 24	2746147320 ps
T382	/workspace/coverage/default/32.chip_sw_all_escalation_resets.1732993658			Jul 28 08:33:42 PM PDT 24	Jul 28 08:44:02 PM PDT 24	4930650944 ps
T211	/workspace/coverage/default/3.chip_sw_uart_tx_rx.747139697			Jul 28 08:30:53 PM PDT 24	Jul 28 08:42:06 PM PDT 24	4168135616 ps
T383	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2049903136			Jul 28 08:07:47 PM PDT 24	Jul 28 08:22:58 PM PDT 24	5050576200 ps
T384	/workspace/coverage/default/2.chip_sw_edn_auto_mode.3859888755			Jul 28 08:24:47 PM PDT 24	Jul 28 08:43:27 PM PDT 24	4013902560 ps
T212	/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1729134792			Jul 28 08:33:51 PM PDT 24	Jul 28 08:56:56 PM PDT 24	7977831700 ps
T953	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3750585963			Jul 28 08:27:17 PM PDT 24	Jul 28 08:38:48 PM PDT 24	4441044500 ps
T457	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3374130389			Jul 28 08:30:42 PM PDT 24	Jul 28 08:34:02 PM PDT 24	2659890280 ps
T954	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.4187644043			Jul 28 08:25:36 PM PDT 24	Jul 28 08:31:11 PM PDT 24	3471712712 ps
T80	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2664666613			Jul 28 08:37:08 PM PDT 24	Jul 28 08:45:22 PM PDT 24	4157034100 ps
T955	/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.801689027			Jul 28 08:23:41 PM PDT 24	Jul 28 08:33:50 PM PDT 24	4281650380 ps
T760	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3249914550			Jul 28 08:24:26 PM PDT 24	Jul 28 08:52:27 PM PDT 24	7810538166 ps
T23	/workspace/coverage/default/0.chip_sw_usbdev_stream.1558169323			Jul 28 08:06:43 PM PDT 24	Jul 28 09:19:29 PM PDT 24	18950224000 ps
T956	/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.545879551			Jul 28 08:10:58 PM PDT 24	Jul 28 08:19:50 PM PDT 24	5942305702 ps
T351	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.1134634457			Jul 28 08:14:19 PM PDT 24	Jul 28 08:19:03 PM PDT 24	3478653523 ps
T957	/workspace/coverage/default/0.chip_sw_example_concurrency.887826033			Jul 28 08:10:38 PM PDT 24	Jul 28 08:16:00 PM PDT 24	3341042860 ps
T745	/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.3130842117			Jul 28 08:09:35 PM PDT 24	Jul 28 08:37:02 PM PDT 24	9572765880 ps
T773	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218403776			Jul 28 08:16:39 PM PDT 24	Jul 28 08:22:12 PM PDT 24	3419982316 ps
T237	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.2334490375			Jul 28 08:24:12 PM PDT 24	Jul 28 08:32:10 PM PDT 24	3608954656 ps
T308	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2890975919			Jul 28 08:08:19 PM PDT 24	Jul 28 08:16:02 PM PDT 24	6518332653 ps
T958	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.958994623			Jul 28 08:31:26 PM PDT 24	Jul 28 08:58:08 PM PDT 24	8428864920 ps
T959	/workspace/coverage/default/2.chip_sw_aes_enc.3869349962			Jul 28 08:25:01 PM PDT 24	Jul 28 08:30:10 PM PDT 24	3125469964 ps
T960	/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.4013889980			Jul 28 08:12:34 PM PDT 24	Jul 28 08:29:41 PM PDT 24	7636479766 ps
T414	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1728859950			Jul 28 08:08:40 PM PDT 24	Jul 28 08:29:42 PM PDT 24	6311528876 ps
T138	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2358463615			Jul 28 08:08:28 PM PDT 24	Jul 28 09:07:32 PM PDT 24	17469976594 ps
T710	/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2827385647			Jul 28 08:31:54 PM PDT 24	Jul 28 09:18:08 PM PDT 24	12637643236 ps
T961	/workspace/coverage/default/2.rom_keymgr_functest.3541645123			Jul 28 08:30:56 PM PDT 24	Jul 28 08:43:29 PM PDT 24	5366203696 ps
T272	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1862932009			Jul 28 08:26:01 PM PDT 24	Jul 28 08:34:48 PM PDT 24	8706633396 ps
T161	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2145954702			Jul 28 08:05:28 PM PDT 24	Jul 28 08:08:51 PM PDT 24	2757230908 ps
T88	/workspace/coverage/default/97.chip_sw_all_escalation_resets.2662087776			Jul 28 08:39:08 PM PDT 24	Jul 28 08:47:19 PM PDT 24	5368143940 ps
T962	/workspace/coverage/default/2.rom_e2e_self_hash.1336827826			Jul 28 08:33:32 PM PDT 24	Jul 28 10:07:36 PM PDT 24	26001647980 ps
T780	/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3805644401			Jul 28 08:32:33 PM PDT 24	Jul 28 08:39:49 PM PDT 24	3800624312 ps
T963	/workspace/coverage/default/0.chip_sw_uart_tx_rx.2781264136			Jul 28 08:10:24 PM PDT 24	Jul 28 08:24:22 PM PDT 24	3954219880 ps
T133	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2966831063			Jul 28 08:06:51 PM PDT 24	Jul 28 08:17:23 PM PDT 24	10138218220 ps
T350	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2513996062			Jul 28 08:11:52 PM PDT 24	Jul 28 08:20:58 PM PDT 24	4333828581 ps
T964	/workspace/coverage/default/2.rom_e2e_smoke.62622300			Jul 28 08:33:10 PM PDT 24	Jul 28 09:25:13 PM PDT 24	14763493416 ps
T206	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2675394025			Jul 28 08:29:55 PM PDT 24	Jul 28 08:51:44 PM PDT 24	8416277008 ps
T25	/workspace/coverage/default/2.chip_sw_gpio.2220878893			Jul 28 08:21:46 PM PDT 24	Jul 28 08:29:52 PM PDT 24	4238338464 ps
T339	/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.2329415026			Jul 28 08:15:15 PM PDT 24	Jul 28 09:16:47 PM PDT 24	19381223630 ps
T139	/workspace/coverage/default/2.rom_raw_unlock.785054903			Jul 28 08:29:22 PM PDT 24	Jul 28 08:33:56 PM PDT 24	5132915578 ps
T965	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1073361319			Jul 28 08:06:40 PM PDT 24	Jul 28 08:17:15 PM PDT 24	5694265264 ps
T218	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3444411744			Jul 28 08:12:38 PM PDT 24	Jul 28 08:25:18 PM PDT 24	4893136649 ps
T220	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.1171814486			Jul 28 08:25:44 PM PDT 24	Jul 28 08:55:32 PM PDT 24	10010045304 ps
T966	/workspace/coverage/default/1.chip_sw_example_concurrency.1751479023			Jul 28 08:11:53 PM PDT 24	Jul 28 08:16:13 PM PDT 24	2616336422 ps
T207	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.268195202			Jul 28 08:06:58 PM PDT 24	Jul 28 08:26:03 PM PDT 24	8898511055 ps
T238	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.1775806228			Jul 28 08:23:01 PM PDT 24	Jul 28 08:35:19 PM PDT 24	5433375236 ps
T262	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2147306901			Jul 28 08:31:59 PM PDT 24	Jul 28 08:56:33 PM PDT 24	8017847240 ps
T250	/workspace/coverage/default/1.chip_sw_rv_timer_irq.4276554686			Jul 28 08:13:45 PM PDT 24	Jul 28 08:17:31 PM PDT 24	2368666964 ps
T263	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3061208393			Jul 28 08:30:15 PM PDT 24	Jul 28 08:38:05 PM PDT 24	3914879680 ps
T264	/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.932364332			Jul 28 08:11:45 PM PDT 24	Jul 28 08:18:03 PM PDT 24	5148990280 ps
T162	/workspace/coverage/default/2.rom_e2e_shutdown_output.2828258680			Jul 28 08:29:53 PM PDT 24	Jul 28 09:19:19 PM PDT 24	27457297920 ps
T265	/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3670936869			Jul 28 08:17:24 PM PDT 24	Jul 28 08:24:18 PM PDT 24	4596390254 ps
T84	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.3496385828			Jul 28 08:13:01 PM PDT 24	Jul 28 11:54:20 PM PDT 24	79645354800 ps
T266	/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.571140963			Jul 28 08:17:00 PM PDT 24	Jul 28 09:17:15 PM PDT 24	15170122568 ps
T267	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1505856225			Jul 28 08:20:17 PM PDT 24	Jul 28 08:26:56 PM PDT 24	3104589450 ps
T195	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.4279153933			Jul 28 08:23:31 PM PDT 24	Jul 28 08:28:47 PM PDT 24	2876095801 ps
T366	/workspace/coverage/default/10.chip_sw_all_escalation_resets.2584670132			Jul 28 08:32:10 PM PDT 24	Jul 28 08:43:18 PM PDT 24	6327514766 ps
T967	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1819452892			Jul 28 08:07:37 PM PDT 24	Jul 28 08:27:49 PM PDT 24	9803643885 ps
T219	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1979047368			Jul 28 08:08:06 PM PDT 24	Jul 28 08:36:06 PM PDT 24	8690541208 ps
T157	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2659186779			Jul 28 08:10:56 PM PDT 24	Jul 28 09:38:45 PM PDT 24	49339806430 ps
T196	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2720471128			Jul 28 08:16:38 PM PDT 24	Jul 28 08:23:38 PM PDT 24	2883748628 ps
T968	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1583390262			Jul 28 08:27:23 PM PDT 24	Jul 28 08:40:09 PM PDT 24	5029902068 ps
T75	/workspace/coverage/default/2.chip_jtag_csr_rw.337701126			Jul 28 08:19:17 PM PDT 24	Jul 28 08:39:25 PM PDT 24	10737852390 ps
T204	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.1811789184			Jul 28 08:15:47 PM PDT 24	Jul 28 08:49:40 PM PDT 24	7236902178 ps
T273	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.798504043			Jul 28 08:15:31 PM PDT 24	Jul 28 08:59:53 PM PDT 24	14494170148 ps
T221	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.551886203			Jul 28 08:15:21 PM PDT 24	Jul 28 08:44:38 PM PDT 24	8859474544 ps
T969	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3331171064			Jul 28 08:30:54 PM PDT 24	Jul 28 08:38:24 PM PDT 24	5799329873 ps
T99	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4049837788			Jul 28 08:19:35 PM PDT 24	Jul 28 08:26:53 PM PDT 24	7958487080 ps
T274	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.1736119898			Jul 28 08:13:36 PM PDT 24	Jul 28 10:10:43 PM PDT 24	24105369960 ps
T711	/workspace/coverage/default/2.chip_sw_aes_masking_off.3462197938			Jul 28 08:23:59 PM PDT 24	Jul 28 08:30:47 PM PDT 24	2841954548 ps
T970	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3250028726			Jul 28 08:05:57 PM PDT 24	Jul 28 08:13:38 PM PDT 24	4907293912 ps