Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	503	1			T464	1		T547	1		T426	2
all_values[1]	510	1			T545	2		T547	1		T426	2
all_values[2]	442	1			T73	1		T464	1		T545	2
all_values[3]	475	1			T547	2		T426	1		T549	2
all_values[4]	463	1			T464	2		T545	1		T547	2
all_values[5]	508	1			T73	1		T545	2		T547	2
all_values[6]	516	1			T545	3		T547	6		T426	1
all_values[7]	509	1			T73	2		T545	1		T546	3
all_values[8]	464	1			T464	3		T545	1		T546	1
all_values[9]	502	1			T545	1		T547	2		T429	1
all_values[10]	465	1			T73	1		T547	2		T426	1
all_values[11]	476	1			T464	1		T547	1		T426	2
all_values[12]	451	1			T464	2		T545	1		T547	5
all_values[13]	443	1			T464	2		T547	5		T426	3
all_values[14]	475	1			T464	1		T545	1		T546	1
all_values[15]	479	1			T464	1		T547	2		T426	2
all_values[16]	495	1			T546	2		T547	4		T549	1
all_values[17]	520	1			T464	1		T545	1		T546	1
all_values[18]	527	1			T73	1		T546	1		T547	2
all_values[19]	474	1			T464	1		T545	2		T546	1
all_values[20]	508	1			T73	1		T545	1		T546	2
all_values[21]	488	1			T73	2		T464	1		T545	1
all_values[22]	493	1			T73	1		T464	2		T545	2
all_values[23]	496	1			T73	1		T464	1		T545	2
all_values[24]	495	1			T464	1		T545	1		T547	1
all_values[25]	537	1			T545	2		T546	1		T547	7
all_values[26]	480	1			T73	1		T545	2		T546	1
all_values[27]	499	1			T464	1		T545	1		T547	4
all_values[28]	484	1			T464	1		T545	1		T546	1
all_values[29]	500	1			T464	1		T545	1		T547	7
all_values[30]	506	1			T464	2		T545	1		T546	1
all_values[31]	473	1			T464	2		T545	1		T426	1
all_values[32]	493	1			T464	1		T545	4		T547	2
all_values[33]	459	1			T464	1		T545	1		T546	1
all_values[34]	501	1			T464	1		T545	1		T547	3
all_values[35]	522	1			T464	1		T545	1		T426	1
all_values[36]	510	1			T546	1		T547	7		T426	4
all_values[37]	458	1			T546	1		T547	2		T549	1
all_values[38]	444	1			T73	1		T464	2		T547	3
all_values[39]	476	1			T73	1		T464	1		T546	2
all_values[40]	500	1			T73	1		T464	1		T547	3
all_values[41]	500	1			T464	1		T545	2		T546	2
all_values[42]	495	1			T464	1		T547	4		T426	1
all_values[43]	496	1			T546	1		T547	4		T426	1
all_values[44]	497	1			T546	1		T547	3		T663	1
all_values[45]	539	1			T464	1		T545	1		T546	2
all_values[46]	519	1			T547	2		T426	1		T723	1
all_values[47]	488	1			T464	2		T545	1		T546	2
all_values[48]	503	1			T547	2		T549	1		T429	1
all_values[49]	468	1			T464	4		T545	1		T546	2