Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3442	1			T464	5		T545	1		T546	2
all_values[1]	3463	1			T119	4		T464	1		T545	4
all_values[2]	3512	1			T119	2		T464	6		T545	2
all_values[3]	3412	1			T119	2		T464	3		T545	4
all_values[4]	3428	1			T464	3		T545	1		T546	1
all_values[5]	3503	1			T119	1		T464	5		T545	3
all_values[6]	3442	1			T119	3		T464	5		T545	4
all_values[7]	3407	1			T119	2		T464	11		T545	2
all_values[8]	3400	1			T119	2		T464	2		T545	3
all_values[9]	3609	1			T119	2		T464	6		T545	3
all_values[10]	3557	1			T119	1		T464	5		T545	5
all_values[11]	3546	1			T119	3		T464	3		T545	4
all_values[12]	3455	1			T119	2		T464	5		T545	2
all_values[13]	3545	1			T119	5		T464	4		T545	2
all_values[14]	3486	1			T119	4		T464	3		T545	2
all_values[15]	3434	1			T119	1		T464	6		T545	2
all_values[16]	3406	1			T119	1		T464	5		T545	2
all_values[17]	3452	1			T119	3		T464	3		T545	3
all_values[18]	3550	1			T119	3		T464	5		T545	4
all_values[19]	3484	1			T119	4		T464	5		T545	1
all_values[20]	3513	1			T464	4		T545	4		T546	2
all_values[21]	3418	1			T119	5		T464	3		T545	3
all_values[22]	3490	1			T119	4		T464	4		T545	2
all_values[23]	3508	1			T119	2		T464	6		T545	1
all_values[24]	3449	1			T119	3		T464	3		T545	1
all_values[25]	3517	1			T119	3		T464	2		T545	4
all_values[26]	3474	1			T119	1		T464	2		T545	3
all_values[27]	3443	1			T119	2		T464	3		T545	2
all_values[28]	3501	1			T119	2		T464	3		T545	3
all_values[29]	3571	1			T119	1		T464	1		T545	3
all_values[30]	3491	1			T464	7		T545	1		T546	1
all_values[31]	3477	1			T119	2		T464	3		T545	3
all_values[32]	3471	1			T119	2		T464	4		T545	3
all_values[33]	3474	1			T119	2		T464	4		T545	2
all_values[34]	3495	1			T119	1		T464	7		T545	3
all_values[35]	3394	1			T119	1		T464	2		T545	3
all_values[36]	3473	1			T119	4		T464	7		T545	4
all_values[37]	3446	1			T119	1		T464	4		T546	1
all_values[38]	3461	1			T464	6		T545	3		T547	11
all_values[39]	3414	1			T119	1		T464	4		T545	1
all_values[40]	3417	1			T119	2		T464	7		T545	3
all_values[41]	3509	1			T119	2		T464	4		T545	1
all_values[42]	3345	1			T119	5		T464	3		T545	3
all_values[43]	3481	1			T119	1		T464	6		T545	1
all_values[44]	3518	1			T119	5		T464	5		T545	4
all_values[45]	3459	1			T119	1		T464	2		T545	1
all_values[46]	3517	1			T119	1		T464	9		T545	1
all_values[47]	3429	1			T119	4		T464	2		T545	4
all_values[48]	3495	1			T119	2		T464	4		T545	1
all_values[49]	3443	1			T119	2		T464	9		T545	2
all_values[50]	3364	1			T464	1		T545	3		T546	3
all_values[51]	3561	1			T119	2		T464	4		T545	2
all_values[52]	3503	1			T464	4		T545	3		T546	1
all_values[53]	3421	1			T119	2		T464	4		T546	4
all_values[54]	3608	1			T119	1		T464	4		T545	4
all_values[55]	3409	1			T119	1		T464	7		T546	2
all_values[56]	3482	1			T119	2		T464	5		T545	1
all_values[57]	3486	1			T119	2		T464	4		T546	1
all_values[58]	3590	1			T119	2		T464	4		T546	4
all_values[59]	3458	1			T119	3		T464	3		T545	1
all_values[60]	3513	1			T119	2		T464	3		T545	3
all_values[61]	3440	1			T119	2		T464	1		T545	1
all_values[62]	3466	1			T119	2		T464	6		T545	2
all_values[63]	3469	1			T464	5		T545	1		T546	3