Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.edn1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	164820	1			T73	12		T74	37		T75	190
values[2]	4503	1			T255	36		T543	3		T548	2
values[3]	2031	1			T255	22		T478	1		T840	119
values[4]	1505	1			T255	15		T840	86		T843	1
values[5]	1277	1			T255	24		T840	77		T843	1
values[6]	1111	1			T255	29		T840	68		T843	1
values[7]	1020	1			T255	37		T840	64		T843	1
values[8]	974	1			T255	34		T840	94		T843	1
values[9]	823	1			T255	33		T840	65		T843	1
values[10]	684	1			T255	29		T840	39		T843	1
values[11]	741	1			T255	46		T840	41		T843	1
values[12]	737	1			T255	35		T840	22		T843	1
values[13]	610	1			T255	23		T840	23		T843	1
values[14]	526	1			T255	19		T840	15		T843	1
values[15]	532	1			T255	8		T840	31		T843	1
values[16]	538	1			T255	4		T840	29		T843	1
values[17]	517	1			T255	2		T840	43		T843	1
values[18]	432	1			T255	1		T840	30		T843	1
values[19]	392	1			T840	20		T843	1		T654	3
values[20]	401	1			T840	8		T843	1		T654	8
values[21]	386	1			T840	3		T843	1		T654	6
values[22]	269	1			T843	1		T654	4		T502	3
values[23]	246	1			T843	1		T654	2		T502	5
values[24]	210	1			T843	1		T654	4		T502	1
values[25]	190	1			T843	1		T654	1		T502	2
values[26]	183	1			T843	1		T654	4		T502	2
values[27]	177	1			T843	1		T654	2		T502	2
values[28]	135	1			T843	1		T654	3		T502	2
values[29]	123	1			T843	1		T654	1		T502	1
values[30]	135	1			T843	1		T654	3		T502	2
values[31]	126	1			T843	1		T654	3		T502	2
values[32]	149	1			T843	1		T654	1		T502	3
values[33]	129	1			T843	1		T654	1		T502	2
values[34]	167	1			T843	1		T654	15		T502	3
values[35]	209	1			T843	1		T654	38		T502	1
values[36]	179	1			T843	1		T654	43		T502	6
values[37]	166	1			T843	1		T654	29		T502	4
values[38]	180	1			T843	1		T654	11		T502	6
values[39]	126	1			T843	1		T654	18		T502	2
values[40]	126	1			T843	1		T654	31		T502	2
values[41]	140	1			T843	1		T654	20		T502	4
values[42]	72	1			T843	1		T654	4		T502	1
values[43]	81	1			T843	1		T654	1		T502	1
values[44]	70	1			T843	1		T502	2		T850	2
values[45]	74	1			T843	1		T502	2		T850	3
values[46]	85	1			T843	1		T502	1		T850	2
values[47]	94	1			T843	1		T502	1		T850	4
values[48]	121	1			T843	1		T502	3		T850	5
values[49]	81	1			T843	1		T502	1		T850	5
values[50]	72	1			T843	1		T502	1		T850	2
values[51]	74	1			T843	1		T502	2		T850	3
values[52]	56	1			T843	1		T502	4		T850	3
values[53]	62	1			T843	1		T502	2		T850	2
values[54]	77	1			T843	1		T502	1		T850	1
values[55]	71	1			T843	1		T502	4		T850	2
values[56]	62	1			T843	1		T502	3		T850	2
values[57]	63	1			T843	1		T502	3		T850	5
values[58]	57	1			T843	1		T502	1		T850	5
values[59]	54	1			T843	1		T502	1		T850	3
values[60]	55	1			T843	1		T502	2		T850	3
values[61]	61	1			T843	1		T502	1		T850	8
values[62]	63	1			T843	1		T502	3		T850	4
values[63]	62	1			T843	1		T502	1		T850	5
values[64]	60	1			T843	1		T502	2		T850	2
values[65]	60	1			T843	1		T502	4		T850	7
values[66]	64	1			T843	1		T502	2		T850	6
values[67]	75	1			T843	1		T502	3		T850	2
values[68]	62	1			T843	1		T502	1		T850	5
values[69]	58	1			T843	1		T502	1		T850	7
values[70]	67	1			T843	1		T502	2		T850	5
values[71]	62	1			T843	1		T502	1		T850	3
values[72]	68	1			T843	1		T502	1		T850	3
values[73]	56	1			T843	1		T502	3		T850	1
values[74]	60	1			T843	1		T502	2		T850	3
values[75]	60	1			T843	1		T502	3		T850	2
values[76]	54	1			T843	1		T502	4		T850	1
values[77]	62	1			T843	1		T502	4		T850	2
values[78]	69	1			T843	1		T502	2		T850	2
values[79]	62	1			T843	1		T502	3		T850	3
values[80]	62	1			T843	1		T502	2		T850	2
values[81]	54	1			T843	1		T502	2		T850	1
values[82]	74	1			T843	1		T502	1		T850	2
values[83]	65	1			T843	1		T502	2		T850	2
values[84]	56	1			T843	1		T502	2		T850	1
values[85]	72	1			T843	1		T502	2		T850	2
values[86]	81	1			T843	1		T502	2		T850	3
values[87]	71	1			T843	1		T502	1		T850	1
values[88]	73	1			T843	1		T502	1		T850	3
values[89]	85	1			T843	2		T502	1		T850	1
values[90]	80	1			T843	1		T502	2		T850	2
values[91]	74	1			T843	1		T502	2		T850	4
values[92]	88	1			T843	1		T502	2		T850	3
values[93]	96	1			T843	1		T502	1		T850	2
values[94]	103	1			T843	1		T502	4		T850	2
values[95]	103	1			T843	1		T502	4		T850	3
values[96]	84	1			T843	1		T502	4		T850	2
values[97]	83	1			T843	1		T502	2		T850	8
values[98]	71	1			T843	1		T502	1		T850	2
values[99]	86	1			T843	1		T502	3		T850	2
values[100]	77	1			T843	1		T502	3		T850	1
values[101]	91	1			T843	1		T502	4		T850	4
values[102]	85	1			T843	1		T502	2		T850	5
values[103]	82	1			T843	1		T502	1		T850	8
values[104]	98	1			T843	1		T502	6		T850	4
values[105]	98	1			T843	1		T502	4		T850	6
values[106]	98	1			T843	1		T502	4		T850	4
values[107]	85	1			T843	1		T502	3		T850	2
values[108]	98	1			T843	1		T502	2		T850	7
values[109]	79	1			T843	1		T502	1		T850	2
values[110]	96	1			T843	1		T502	4		T850	4
values[111]	84	1			T843	1		T502	3		T850	1
values[112]	100	1			T843	1		T502	1		T850	2
values[113]	92	1			T843	1		T502	1		T850	2
values[114]	100	1			T843	1		T502	2		T850	5
values[115]	114	1			T843	1		T502	3		T850	5
values[116]	90	1			T843	1		T502	4		T850	3
values[117]	103	1			T843	1		T502	1		T850	4
values[118]	117	1			T843	1		T502	2		T850	1
values[119]	115	1			T843	1		T502	1		T850	4
values[120]	121	1			T843	1		T502	1		T850	10
values[121]	114	1			T843	1		T502	2		T850	9
values[122]	112	1			T843	1		T502	3		T850	11
values[123]	127	1			T843	5		T502	11		T850	7
values[124]	189	1			T843	3		T502	25		T850	3
values[125]	395	1			T843	3		T502	57		T850	28
values[126]	783	1			T843	11		T502	101		T850	42
values[127]	2855	1			T843	122		T502	70		T850	23
values[128]	5048	1			T843	244		T502	4		T642	3