Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.05	95.42	93.80	95.40		94.64	97.53	99.51

Total tests in report: 2939

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.67	39.67	44.87	44.87	43.00	43.00	32.45	32.45			58.02	58.02	59.27	59.27	0.39	0.39	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.504766932
49.05	9.39	50.51	5.63	56.40	13.40	32.85	0.40			68.18	10.16	84.44	25.17	1.94	1.55	/workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.3078413406
56.07	7.02	61.21	10.70	61.65	5.25	39.34	6.48			69.57	1.40	84.44	0.00	20.23	18.29	/workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.2760079660
61.63	5.55	72.98	11.77	69.49	7.84	42.55	3.21			80.07	10.50	84.44	0.00	20.23	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1809154648
65.33	3.70	72.98	0.00	69.82	0.32	42.55	0.00			80.12	0.05	84.44	0.00	42.06	21.83	/workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.2849888227
68.53	3.20	78.25	5.26	73.79	3.97	46.15	3.59			81.92	1.80	88.99	4.55	42.06	0.00	/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3155774724
71.21	2.69	78.25	0.01	74.23	0.44	46.15	0.00			82.04	0.11	88.99	0.00	57.63	15.57	/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1428128826
73.78	2.56	80.35	2.09	76.92	2.68	54.52	8.37			83.92	1.88	89.34	0.35	57.63	0.00	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3162791622
76.08	2.30	83.87	3.53	78.48	1.56	61.28	6.76			84.84	0.92	90.38	1.05	57.63	0.00	/workspace/coverage/default/1.chip_sw_power_virus.3692461097
78.15	2.06	83.87	0.00	78.48	0.00	73.61	12.33			84.84	0.00	90.38	0.00	57.68	0.05	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.84228797
80.07	1.93	83.87	0.00	78.48	0.00	73.61	0.00			84.84	0.00	90.38	0.00	69.25	11.57	/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1943661263
81.51	1.44	83.87	0.00	78.48	0.00	73.61	0.00			84.84	0.00	90.38	0.00	77.86	8.61	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1974942739
82.80	1.29	86.20	2.33	80.96	2.49	73.87	0.25			87.55	2.70	90.38	0.00	77.86	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3185717799
83.93	1.13	86.20	0.00	80.96	0.00	80.62	6.76			87.55	0.00	90.38	0.00	77.86	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2170759227
84.92	0.99	87.50	1.30	82.04	1.08	81.21	0.59			88.71	1.16	92.13	1.75	77.91	0.05	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1384096935
85.80	0.88	88.23	0.73	82.40	0.36	81.22	0.01			89.03	0.32	95.98	3.85	77.91	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3836535546
86.58	0.78	88.23	0.00	82.50	0.11	81.22	0.00			89.06	0.03	95.98	0.00	82.46	4.55	/workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.1059328007
87.35	0.77	89.51	1.28	83.52	1.02	82.20	0.97			90.42	1.35	95.98	0.00	82.46	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.18640768
88.00	0.65	90.74	1.23	84.52	1.00	82.69	0.49			91.59	1.17	95.98	0.00	82.46	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.3166777541
88.56	0.56	90.74	0.00	84.52	0.00	82.69	0.00			91.59	0.00	95.98	0.00	85.83	3.37	/workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.4261010760
89.06	0.51	91.08	0.33	84.81	0.29	83.72	1.03			91.59	0.01	95.98	0.00	87.19	1.36	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3121210837
89.55	0.49	91.89	0.81	85.64	0.83	84.34	0.63			92.18	0.58	95.98	0.00	87.29	0.09	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.658681915
90.01	0.46	91.89	0.00	85.64	0.00	84.34	0.00			92.18	0.00	95.98	0.00	90.05	2.76	/workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.370199959
90.46	0.45	91.94	0.05	85.70	0.06	85.08	0.74			92.18	0.00	95.98	0.00	91.90	1.86	/workspace/coverage/default/1.chip_sw_alert_test.4179812984
90.91	0.45	92.23	0.29	85.85	0.16	86.80	1.72			92.36	0.18	96.33	0.35	91.90	0.00	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2530407674
91.32	0.41	92.23	0.00	85.86	0.01	86.80	0.00			92.36	0.00	96.33	0.00	94.34	2.43	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.2430806695
91.65	0.34	92.92	0.69	86.42	0.55	87.12	0.32			92.80	0.45	96.33	0.00	94.34	0.00	/workspace/coverage/default/1.chip_sw_gpio.3880568773
91.96	0.30	92.93	0.01	86.42	0.01	88.93	1.81			92.80	0.00	96.33	0.00	94.34	0.00	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2483224543
92.23	0.27	92.93	0.01	86.64	0.22	88.93	0.00			92.81	0.01	96.33	0.00	95.73	1.40	/workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.222805836
92.50	0.27	93.21	0.28	87.93	1.28	88.95	0.01			92.83	0.02	96.33	0.00	95.73	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.3867697428
92.71	0.21	93.52	0.31	88.09	0.16	89.50	0.55			93.10	0.27	96.33	0.00	95.73	0.00	/workspace/coverage/default/0.rom_e2e_shutdown_output.944367098
92.92	0.21	93.52	0.01	89.29	1.20	89.50	0.00			93.10	0.00	96.33	0.00	95.78	0.05	/workspace/coverage/cover_reg_top/15.chip_tl_errors.1587951379
93.10	0.19	93.58	0.06	89.30	0.01	90.54	1.04			93.10	0.01	96.33	0.00	95.78	0.00	/workspace/coverage/default/0.chip_jtag_mem_access.106413208
93.27	0.16	93.58	0.00	89.30	0.00	90.54	0.00			93.10	0.00	96.33	0.00	96.77	0.99	/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3745736511
93.42	0.16	93.59	0.01	89.72	0.43	90.55	0.01			93.59	0.49	96.33	0.00	96.77	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1604604462
93.57	0.15	93.79	0.21	90.04	0.32	90.91	0.36			93.59	0.00	96.33	0.00	96.77	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1096439921
93.69	0.12	93.90	0.11	90.15	0.11	91.34	0.43			93.67	0.08	96.33	0.00	96.77	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.2179773112
93.81	0.12	93.90	0.00	90.19	0.04	91.34	0.00			93.67	0.00	96.33	0.00	97.43	0.66	/workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.650487688
93.92	0.12	93.95	0.05	90.25	0.06	91.87	0.54			93.71	0.04	96.33	0.00	97.43	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4275554668
94.04	0.11	93.95	0.00	90.25	0.00	92.53	0.65			93.71	0.00	96.33	0.00	97.46	0.04	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.4038205711
94.15	0.11	93.95	0.00	90.25	0.00	93.17	0.64			93.71	0.00	96.33	0.00	97.46	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.447765364
94.24	0.10	93.95	0.00	90.82	0.57	93.17	0.00			93.71	0.00	96.33	0.00	97.46	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.1984374457
94.33	0.09	93.95	0.00	91.08	0.25	93.18	0.01			94.00	0.29	96.33	0.00	97.46	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3561653312
94.42	0.08	93.95	0.00	91.23	0.15	93.18	0.00			94.00	0.00	96.33	0.00	97.80	0.34	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1984255921
94.48	0.07	94.08	0.13	91.27	0.04	93.19	0.01			94.04	0.04	96.50	0.17	97.81	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3327594173
94.55	0.07	94.08	0.00	91.36	0.09	93.19	0.00			94.04	0.00	96.50	0.00	98.12	0.31	/workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.652360870
94.61	0.06	94.20	0.12	91.45	0.09	93.25	0.06			94.14	0.10	96.50	0.00	98.12	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2545356440
94.67	0.06	94.23	0.03	91.52	0.07	93.43	0.18			94.19	0.05	96.50	0.00	98.12	0.00	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3511130261
94.72	0.06	94.23	0.00	91.65	0.13	93.43	0.00			94.21	0.02	96.50	0.00	98.31	0.19	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.4105462795
94.77	0.05	94.25	0.01	91.70	0.05	93.49	0.06			94.23	0.02	96.68	0.17	98.31	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1495179527
94.82	0.05	94.34	0.10	91.81	0.11	93.49	0.01			94.30	0.07	96.68	0.00	98.31	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.195485443
94.87	0.05	94.34	0.00	92.10	0.29	93.49	0.00			94.30	0.00	96.68	0.00	98.31	0.00	/workspace/coverage/cover_reg_top/24.chip_tl_errors.4075044442
94.92	0.05	94.34	0.00	92.10	0.00	93.78	0.28			94.30	0.00	96.68	0.00	98.31	0.00	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2912527884
94.96	0.04	94.36	0.02	92.12	0.02	93.78	0.00			94.32	0.02	96.85	0.17	98.32	0.01	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3793062802
95.00	0.04	94.47	0.11	92.12	0.00	93.91	0.13			94.32	0.00	96.85	0.00	98.32	0.00	/workspace/coverage/cover_reg_top/68.xbar_random.1089838228
95.04	0.04	94.50	0.03	92.12	0.01	93.91	0.01			94.33	0.01	97.03	0.17	98.33	0.01	/workspace/coverage/default/3.chip_sw_all_escalation_resets.2356793588
95.07	0.04	94.50	0.01	92.14	0.01	93.93	0.02			94.34	0.01	97.20	0.17	98.34	0.01	/workspace/coverage/default/83.chip_sw_all_escalation_resets.2515531249
95.11	0.04	94.50	0.00	92.14	0.00	94.14	0.22			94.34	0.00	97.20	0.00	98.34	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3952128153
95.15	0.04	94.50	0.01	92.15	0.01	94.15	0.01			94.34	0.01	97.38	0.17	98.36	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.275561928
95.18	0.04	94.54	0.03	92.18	0.04	94.25	0.10			94.39	0.04	97.38	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.395822927
95.21	0.03	94.54	0.00	92.37	0.19	94.25	0.00			94.39	0.00	97.38	0.00	98.36	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.473301592
95.24	0.03	94.54	0.00	92.37	0.00	94.26	0.01			94.39	0.00	97.55	0.17	98.36	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.605965988
95.27	0.03	94.61	0.07	92.40	0.03	94.27	0.01			94.43	0.05	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.37540819
95.30	0.03	94.61	0.00	92.40	0.00	94.43	0.16			94.43	0.00	97.55	0.00	98.36	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2652763957
95.32	0.03	94.61	0.00	92.48	0.08	94.43	0.00			94.46	0.02	97.55	0.00	98.41	0.06	/workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1629780949
95.35	0.03	94.61	0.00	92.48	0.00	94.59	0.16			94.46	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.857813465
95.38	0.03	94.61	0.00	92.52	0.05	94.59	0.00			94.46	0.00	97.55	0.00	98.52	0.11	/workspace/coverage/cover_reg_top/61.xbar_stress_all.585281039
95.40	0.02	94.68	0.07	92.52	0.00	94.66	0.07			94.47	0.01	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_tap_straps_testunlock0.81213259
95.42	0.02	94.75	0.07	92.57	0.05	94.66	0.00			94.50	0.03	97.55	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.269272942
95.45	0.02	94.75	0.00	92.71	0.14	94.66	0.00			94.50	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1883371999
95.47	0.02	94.75	0.00	92.73	0.02	94.78	0.12			94.50	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1107781143
95.49	0.02	94.75	0.00	92.81	0.07	94.78	0.00			94.52	0.02	97.55	0.00	98.54	0.02	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1997231264
95.51	0.02	94.75	0.00	92.91	0.10	94.78	0.00			94.52	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.4114608625
95.52	0.02	94.75	0.01	92.91	0.00	94.86	0.08			94.52	0.01	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.4159930268
95.54	0.02	94.75	0.00	92.96	0.05	94.86	0.00			94.56	0.04	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.3013573730
95.56	0.02	94.75	0.00	92.96	0.00	94.96	0.09			94.56	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3756958022
95.57	0.01	94.75	0.00	93.04	0.08	94.96	0.00			94.56	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.1892703764
95.58	0.01	94.75	0.00	93.12	0.08	94.96	0.00			94.56	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.2589966173
95.59	0.01	94.75	0.00	93.12	0.00	95.02	0.07			94.56	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1898513699
95.60	0.01	94.75	0.00	93.19	0.07	95.02	0.00			94.56	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.36132480
95.62	0.01	94.75	0.00	93.24	0.05	95.02	0.00			94.58	0.02	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.926906148
95.62	0.01	94.75	0.00	93.25	0.01	95.02	0.00			94.58	0.00	97.55	0.00	98.59	0.05	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.281461248
95.63	0.01	94.75	0.00	93.27	0.02	95.02	0.00			94.58	0.00	97.55	0.00	98.63	0.04	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.623842904
95.64	0.01	94.77	0.02	93.28	0.01	95.03	0.01			94.60	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.662756844
95.65	0.01	94.80	0.02	93.28	0.01	95.04	0.01			94.61	0.02	97.55	0.00	98.63	0.00	/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1293033010
95.66	0.01	94.80	0.01	93.33	0.04	95.04	0.00			94.61	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.4035713244
95.67	0.01	94.80	0.00	93.33	0.00	95.04	0.00			94.61	0.00	97.55	0.00	98.67	0.05	/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.659298486
95.67	0.01	94.80	0.00	93.33	0.00	95.08	0.04			94.61	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1252010825
95.68	0.01	94.80	0.00	93.33	0.00	95.12	0.04			94.61	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4025934873
95.69	0.01	94.81	0.01	93.35	0.02	95.13	0.01			94.61	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2294268151
95.69	0.01	94.81	0.01	93.37	0.02	95.14	0.01			94.61	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.928945527
95.70	0.01	94.81	0.00	93.39	0.01	95.17	0.03			94.61	0.00	97.55	0.00	98.67	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1452035747
95.71	0.01	94.81	0.00	93.41	0.02	95.17	0.00			94.61	0.00	97.55	0.00	98.68	0.01	/workspace/coverage/cover_reg_top/23.chip_tl_errors.1017839739
95.71	0.01	94.81	0.00	93.45	0.04	95.17	0.00			94.61	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1688177626
95.72	0.01	94.81	0.00	93.45	0.00	95.17	0.00			94.61	0.00	97.55	0.00	98.72	0.04	/workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.2123727259
95.72	0.01	94.81	0.00	93.48	0.03	95.17	0.00			94.61	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.1619936779
95.73	0.01	94.81	0.00	93.51	0.03	95.17	0.00			94.61	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2738168213
95.73	0.01	94.82	0.01	93.53	0.02	95.17	0.01			94.61	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.513909038
95.74	0.01	94.82	0.00	93.53	0.00	95.20	0.03			94.61	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3952445157
95.74	0.01	94.82	0.00	93.53	0.00	95.23	0.03			94.61	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.748444533
95.75	0.01	94.82	0.00	93.55	0.02	95.23	0.00			94.61	0.00	97.55	0.00	98.72	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.2366347866
95.75	0.01	94.82	0.00	93.55	0.00	95.25	0.01			94.61	0.00	97.55	0.00	98.73	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3337851332
95.76	0.01	94.82	0.00	93.55	0.00	95.25	0.00			94.61	0.00	97.55	0.00	98.75	0.02	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.1144399766
95.76	0.01	94.82	0.00	93.55	0.00	95.25	0.00			94.61	0.00	97.55	0.00	98.78	0.02	/workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.940624737
95.76	0.01	94.82	0.01	93.57	0.01	95.25	0.01			94.61	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3612348015
95.77	0.01	94.82	0.00	93.59	0.02	95.25	0.00			94.61	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/83.xbar_stress_all.3835412666
95.77	0.01	94.82	0.00	93.59	0.00	95.27	0.02			94.61	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.772373942
95.77	0.01	94.82	0.01	93.59	0.00	95.29	0.02			94.61	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3317935606
95.78	0.01	94.82	0.00	93.61	0.02	95.29	0.00			94.61	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.3179928986
95.78	0.01	94.83	0.01	93.62	0.01	95.29	0.00			94.61	0.00	97.55	0.00	98.78	0.00	/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.879818539
95.78	0.01	94.83	0.00	93.62	0.00	95.29	0.01			94.61	0.00	97.55	0.00	98.79	0.01	/workspace/coverage/default/72.chip_sw_all_escalation_resets.1000680610
95.79	0.01	94.83	0.00	93.62	0.00	95.31	0.02			94.61	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.178919140
95.79	0.01	94.83	0.00	93.64	0.01	95.31	0.00			94.61	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/22.xbar_stress_all.2095734595
95.79	0.01	94.83	0.00	93.65	0.01	95.31	0.00			94.61	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/cover_reg_top/5.xbar_stress_all.1490909756
95.79	0.01	94.83	0.00	93.66	0.01	95.31	0.00			94.61	0.00	97.55	0.00	98.79	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.44039742
95.79	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.80	0.01	/workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.2366380549
95.80	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.81	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1423968646
95.80	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.83	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.3572622674
95.80	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.84	0.01	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2832952162
95.80	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.85	0.01	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3364846180
95.80	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.86	0.01	/workspace/coverage/default/10.chip_sw_all_escalation_resets.560248169
95.81	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.87	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468077021
95.81	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/11.chip_sw_all_escalation_resets.748919061
95.81	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.90	0.01	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488036829
95.81	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.91	0.01	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2656295275
95.81	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.92	0.01	/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600784783
95.82	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1448303239
95.82	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.94	0.01	/workspace/coverage/default/14.chip_sw_all_escalation_resets.4082794774
95.82	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.95	0.01	/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.937246609
95.82	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1929401953
95.82	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1559108488
95.83	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/17.chip_sw_all_escalation_resets.1223056698
95.83	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1047449921
95.83	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.36235145
95.83	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248972566
95.83	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/21.chip_sw_all_escalation_resets.513039641
95.84	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.05	0.01	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462330525
95.84	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.06	0.01	/workspace/coverage/default/22.chip_sw_all_escalation_resets.775262136
95.84	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.07	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1426168947
95.84	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.08	0.01	/workspace/coverage/default/24.chip_sw_all_escalation_resets.3606164653
95.84	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3796485070
95.85	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.11	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.537021637
95.85	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420521379
95.85	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/28.chip_sw_all_escalation_resets.2059419440
95.85	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2102092010
95.85	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.15	0.01	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119619587
95.86	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.17	0.01	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013849373
95.86	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.18	0.01	/workspace/coverage/default/31.chip_sw_all_escalation_resets.4031596312
95.86	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/32.chip_sw_all_escalation_resets.3044870943
95.86	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.20	0.01	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3230293285
95.86	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.21	0.01	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2491143774
95.86	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.22	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.769145143
95.87	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.24	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3205311989
95.87	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.25	0.01	/workspace/coverage/default/37.chip_sw_all_escalation_resets.2805606349
95.87	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.26	0.01	/workspace/coverage/default/38.chip_sw_all_escalation_resets.705133462
95.87	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.27	0.01	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.180186534
95.87	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.28	0.01	/workspace/coverage/default/42.chip_sw_all_escalation_resets.2734880058
95.88	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.30	0.01	/workspace/coverage/default/43.chip_sw_all_escalation_resets.604162141
95.88	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.31	0.01	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2645299729
95.88	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.32	0.01	/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655967303
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95.89	0.01	94.83	0.00	93.66	0.00	95.31	0.00			94.61	0.00	97.55	0.00	99.38	0.01	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3239997585
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95.92	0.01	94.83	0.00	93.69	0.01	95.32	0.00			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.134541844
95.92	0.01	94.83	0.00	93.70	0.01	95.32	0.00			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.837391418
95.92	0.01	94.83	0.00	93.71	0.01	95.32	0.00			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_gpio.1459424129
95.92	0.01	94.83	0.00	93.72	0.01	95.32	0.00			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1457657487
95.92	0.01	94.83	0.00	93.73	0.01	95.32	0.00			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1761375881
95.93	0.01	94.83	0.01	93.73	0.00	95.33	0.01			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/20.chip_sw_all_escalation_resets.1662996137
95.93	0.01	94.83	0.00	93.73	0.00	95.34	0.01			94.61	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.296488613
95.93	0.01	94.83	0.00	93.73	0.00	95.34	0.00			94.62	0.01	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2151899896
95.93	0.01	94.83	0.00	93.73	0.00	95.34	0.00			94.63	0.01	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3694364508
95.93	0.01	94.83	0.00	93.73	0.00	95.34	0.00			94.64	0.01	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_tap_straps_dev.1516332575
95.93	0.01	94.83	0.00	93.73	0.01	95.34	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/1.chip_tl_errors.954012990
95.93	0.01	94.83	0.00	93.73	0.00	95.34	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3847282583
95.94	0.01	94.83	0.00	93.73	0.00	95.35	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.551772071
95.94	0.01	94.83	0.00	93.73	0.00	95.36	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2438147294
95.94	0.01	94.84	0.01	93.73	0.00	95.36	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.1412652380
95.94	0.01	94.84	0.00	93.73	0.00	95.36	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1830839024
95.94	0.01	94.84	0.00	93.73	0.00	95.37	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3007840538
95.94	0.01	94.84	0.00	93.73	0.00	95.37	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.100015246
95.94	0.01	94.84	0.00	93.73	0.00	95.38	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3912291924
95.94	0.01	94.84	0.00	93.73	0.00	95.38	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2329326094
95.94	0.01	94.84	0.00	93.73	0.00	95.39	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2844649311
95.94	0.01	94.84	0.00	93.74	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3994077267
95.94	0.01	94.84	0.00	93.74	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.619356594
95.94	0.01	94.84	0.00	93.75	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/16.chip_tl_errors.4977068
95.94	0.01	94.84	0.00	93.75	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/20.xbar_random_large_delays.1556720458
95.95	0.01	94.84	0.00	93.75	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.903114721
95.95	0.01	94.84	0.00	93.76	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1995009274
95.95	0.01	94.84	0.00	93.76	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.640228641
95.95	0.01	94.84	0.00	93.76	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.3258814498
95.95	0.01	94.84	0.00	93.77	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1631200723
95.95	0.01	94.84	0.00	93.77	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/74.xbar_error_random.3536858615
95.95	0.01	94.84	0.00	93.77	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_jtag_csr_rw.1980270906
95.95	0.01	94.84	0.00	93.78	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_aon_timer_irq.1048145236
95.95	0.01	94.84	0.00	93.78	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3544699050
95.95	0.01	94.84	0.00	93.78	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3123776158
95.95	0.01	94.84	0.00	93.79	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2179098780
95.95	0.01	94.84	0.00	93.79	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3611252911
95.95	0.01	94.84	0.00	93.80	0.01	95.39	0.00			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2629609584
95.95	0.01	94.84	0.00	93.80	0.00	95.39	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_tap_straps_rma.1073786890
95.95	0.01	94.84	0.00	93.80	0.00	95.39	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1631675559
95.95	0.01	94.84	0.00	93.80	0.00	95.39	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.663545087
95.95	0.01	94.84	0.00	93.80	0.00	95.40	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.2774195302
95.95	0.01	94.84	0.00	93.80	0.00	95.40	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.184709606
95.95	0.01	94.84	0.00	93.80	0.00	95.40	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1593524479
95.95	0.01	94.84	0.00	93.80	0.00	95.40	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3391338503
95.96	0.01	94.84	0.00	93.80	0.00	95.40	0.01			94.64	0.00	97.55	0.00	99.51	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.3978050088

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.303605765
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2294649792
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4102579681
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1615346281
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.1810715771
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.712566782
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3280537990
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1895306351
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2797981352
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.425170838
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2867148164
/workspace/coverage/cover_reg_top/0.xbar_error_random.3981927165
/workspace/coverage/cover_reg_top/0.xbar_random.4121286336
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.461325812
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.827584826
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1295449300
/workspace/coverage/cover_reg_top/0.xbar_same_source.3288766974
/workspace/coverage/cover_reg_top/0.xbar_smoke.1343899973
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3836726339
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2352213312
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.4093529063
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2777056359
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2792266896
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2113901587
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3166020062
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2847298876
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1105316616
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1565873531
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2577704228
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.3437357780
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2725359171
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2339950163
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.3131499970
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.4071833388
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2139221632
/workspace/coverage/cover_reg_top/1.xbar_error_random.1056074122
/workspace/coverage/cover_reg_top/1.xbar_random.1852183869
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.782456002
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2869650944
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.226795195
/workspace/coverage/cover_reg_top/1.xbar_same_source.1058423167
/workspace/coverage/cover_reg_top/1.xbar_smoke.3293930254
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3529031021
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2999844136
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1027145520
/workspace/coverage/cover_reg_top/1.xbar_stress_all.3572679677
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.143380337
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2783337350
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1434476597
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2860346400
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.3277914742
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2796361123
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1653422229
/workspace/coverage/cover_reg_top/10.chip_tl_errors.4150648405
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2530036368
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.2882553680
/workspace/coverage/cover_reg_top/10.xbar_error_random.135757270
/workspace/coverage/cover_reg_top/10.xbar_random.4282121088
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1939999889
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2438892047
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.531802544
/workspace/coverage/cover_reg_top/10.xbar_same_source.3752337387
/workspace/coverage/cover_reg_top/10.xbar_smoke.2420373780
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2603538870
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.3817136229
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3285374816
/workspace/coverage/cover_reg_top/10.xbar_stress_all.3661413165
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3317102764
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2292444182
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2456011982
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1387409054
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2804769949
/workspace/coverage/cover_reg_top/11.chip_csr_rw.4007762977
/workspace/coverage/cover_reg_top/11.chip_tl_errors.2624357233
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2361488552
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2950783219
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3166105879
/workspace/coverage/cover_reg_top/11.xbar_error_random.1126499669
/workspace/coverage/cover_reg_top/11.xbar_random.3865139004
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.1280041266
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3022017642
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.12249193
/workspace/coverage/cover_reg_top/11.xbar_same_source.1727461904
/workspace/coverage/cover_reg_top/11.xbar_smoke.934043991
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.3758978599
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3121932246
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.2676522450
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4229944881
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2728805472
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3630299360
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2097657238
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3178845668
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3991840210
/workspace/coverage/cover_reg_top/12.chip_csr_rw.347486060
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.3336502502
/workspace/coverage/cover_reg_top/12.chip_tl_errors.3283958611
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.30273757
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2432070679
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.602099826
/workspace/coverage/cover_reg_top/12.xbar_error_random.3416457301
/workspace/coverage/cover_reg_top/12.xbar_random.177674811
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3701206688
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1500948400
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.1964513996
/workspace/coverage/cover_reg_top/12.xbar_same_source.4247206171
/workspace/coverage/cover_reg_top/12.xbar_smoke.753405625
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3624281354
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.426761123
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3705481339
/workspace/coverage/cover_reg_top/12.xbar_stress_all.124489795
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.529306065
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.3439813461
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3876805755
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.1484285730
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.3772185707
/workspace/coverage/cover_reg_top/13.chip_csr_rw.414874771
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.197276592
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.1815578513
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3990717150
/workspace/coverage/cover_reg_top/13.xbar_error_random.857155450
/workspace/coverage/cover_reg_top/13.xbar_random.1111700124
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.837188060
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1113761760
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.518384687
/workspace/coverage/cover_reg_top/13.xbar_same_source.2606188381
/workspace/coverage/cover_reg_top/13.xbar_smoke.2277142160
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2236607698
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.3497406636
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2765230869
/workspace/coverage/cover_reg_top/13.xbar_stress_all.2668468880
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2571936315
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.607508181
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/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.161825928
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/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.716124672
/workspace/coverage/default/4.chip_sw_all_escalation_resets.3529560316
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1801838435
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/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.334189987
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/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1096193336
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/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.734380528
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563647056
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3034643931
/workspace/coverage/default/58.chip_sw_all_escalation_resets.837047774
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2313694061
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702347872
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/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3180124092
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4267107061
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199336264
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/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749259220
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/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3386266725
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/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3241732684
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.155821697
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/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529311979
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/workspace/coverage/default/68.chip_sw_all_escalation_resets.2073785600
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.595861436
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/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2110195758
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/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2419516606
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3773014612
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3495092355
/workspace/coverage/default/70.chip_sw_all_escalation_resets.2353963324
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3943232170
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/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031632924
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.251114537
/workspace/coverage/default/74.chip_sw_all_escalation_resets.18419879
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/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3014371432
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/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.506967579
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/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.4185958062
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/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.846051642
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/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1427749158
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4242899853
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/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291284811
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/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1144006275
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/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.4066767090
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1569234356
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1674674414
/workspace/coverage/default/9.chip_sw_all_escalation_resets.346648701
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.4144383232
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1152346252
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1257059285
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3328216774
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1873890759
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1943869828
/workspace/coverage/default/93.chip_sw_all_escalation_resets.1644014470
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3758875387
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1788479260
/workspace/coverage/default/96.chip_sw_all_escalation_resets.212657544
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1092582839
/workspace/coverage/default/98.chip_sw_all_escalation_resets.931961741
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2961985067
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.844645455
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1082255899
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2800884042
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3703515113
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.527295222
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3078172574
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4140628318
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3148296577

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Total test records in report: 2939

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.504766932			Jul 29 08:33:47 PM PDT 24	Jul 29 09:19:33 PM PDT 24	20187507579 ps
T2	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2056039516			Jul 29 08:50:43 PM PDT 24	Jul 29 08:56:28 PM PDT 24	4263753096 ps
T3	/workspace/coverage/default/0.chip_sw_aes_smoketest.364647029			Jul 29 08:24:24 PM PDT 24	Jul 29 08:28:06 PM PDT 24	2448207250 ps
T44	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.2330141076			Jul 29 08:42:57 PM PDT 24	Jul 29 09:43:52 PM PDT 24	14943821586 ps
T45	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.772373942			Jul 29 08:25:47 PM PDT 24	Jul 29 09:06:14 PM PDT 24	10141174098 ps
T4	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.658681915			Jul 29 08:45:53 PM PDT 24	Jul 29 08:52:12 PM PDT 24	3819051296 ps
T5	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.296488613			Jul 29 08:15:15 PM PDT 24	Jul 29 08:25:22 PM PDT 24	9125451540 ps
T88	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3511130261			Jul 29 08:43:48 PM PDT 24	Jul 29 09:06:11 PM PDT 24	9253011656 ps
T6	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1107781143			Jul 29 08:32:54 PM PDT 24	Jul 30 12:08:06 AM PDT 24	78163289089 ps
T89	/workspace/coverage/default/2.chip_sw_kmac_idle.1411779221			Jul 29 08:37:33 PM PDT 24	Jul 29 08:42:06 PM PDT 24	3315816760 ps
T220	/workspace/coverage/default/2.chip_sw_pattgen_ios.468697515			Jul 29 08:31:24 PM PDT 24	Jul 29 08:34:51 PM PDT 24	2698706360 ps
T123	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2705148500			Jul 29 08:17:00 PM PDT 24	Jul 29 08:36:15 PM PDT 24	6226967792 ps
T7	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3162791622			Jul 29 08:33:53 PM PDT 24	Jul 29 09:36:26 PM PDT 24	14440712185 ps
T46	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2570725097			Jul 29 08:30:24 PM PDT 24	Jul 29 08:41:07 PM PDT 24	5727961874 ps
T124	/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1939050185			Jul 29 08:27:29 PM PDT 24	Jul 29 08:44:05 PM PDT 24	5907766446 ps
T42	/workspace/coverage/default/0.rom_e2e_shutdown_output.944367098			Jul 29 08:30:28 PM PDT 24	Jul 29 09:41:23 PM PDT 24	27257462380 ps
T378	/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3372174327			Jul 29 08:42:45 PM PDT 24	Jul 29 08:46:21 PM PDT 24	3054637910 ps
T116	/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1452035747			Jul 29 08:37:00 PM PDT 24	Jul 29 08:44:47 PM PDT 24	5927201616 ps
T62	/workspace/coverage/default/35.chip_sw_all_escalation_resets.2627441739			Jul 29 08:46:16 PM PDT 24	Jul 29 08:55:22 PM PDT 24	5126194924 ps
T364	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.1559108488			Jul 29 08:43:33 PM PDT 24	Jul 29 08:51:29 PM PDT 24	3909259456 ps
T307	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3468077021			Jul 29 08:43:13 PM PDT 24	Jul 29 08:49:08 PM PDT 24	4326874072 ps
T265	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1427749158			Jul 29 08:53:39 PM PDT 24	Jul 29 08:59:24 PM PDT 24	3681363232 ps
T379	/workspace/coverage/default/1.chip_sw_aes_entropy.2304747040			Jul 29 08:28:45 PM PDT 24	Jul 29 08:32:21 PM PDT 24	3454594800 ps
T380	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3337851332			Jul 29 08:44:24 PM PDT 24	Jul 29 08:51:09 PM PDT 24	3627050280 ps
T381	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.890767652			Jul 29 08:31:44 PM PDT 24	Jul 29 08:41:37 PM PDT 24	5520620456 ps
T455	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2725873472			Jul 29 08:39:05 PM PDT 24	Jul 29 08:46:27 PM PDT 24	3096275028 ps
T156	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1761375881			Jul 29 08:33:18 PM PDT 24	Jul 29 09:12:18 PM PDT 24	13730187920 ps
T218	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.224591916			Jul 29 08:42:42 PM PDT 24	Jul 29 09:08:25 PM PDT 24	8322961096 ps
T117	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2040536654			Jul 29 08:26:26 PM PDT 24	Jul 29 08:37:41 PM PDT 24	8001419522 ps
T223	/workspace/coverage/default/67.chip_sw_all_escalation_resets.150060616			Jul 29 08:48:28 PM PDT 24	Jul 29 08:57:06 PM PDT 24	4925192520 ps
T47	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3694364508			Jul 29 08:26:22 PM PDT 24	Jul 29 08:35:42 PM PDT 24	5615098970 ps
T753	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2110195758			Jul 29 08:47:53 PM PDT 24	Jul 29 08:53:48 PM PDT 24	3633595624 ps
T157	/workspace/coverage/default/2.chip_plic_all_irqs_10.18640768			Jul 29 08:36:21 PM PDT 24	Jul 29 08:47:36 PM PDT 24	3879602888 ps
T48	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2652763957			Jul 29 08:13:30 PM PDT 24	Jul 29 08:17:59 PM PDT 24	3853679821 ps
T118	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3360273201			Jul 29 08:15:58 PM PDT 24	Jul 29 08:35:22 PM PDT 24	5622407597 ps
T309	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.663545087			Jul 29 08:16:59 PM PDT 24	Jul 29 08:44:59 PM PDT 24	7913919172 ps
T125	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2483224543			Jul 29 08:35:52 PM PDT 24	Jul 29 08:56:31 PM PDT 24	7640018400 ps
T67	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1898513699			Jul 29 08:35:41 PM PDT 24	Jul 29 08:46:43 PM PDT 24	3832328920 ps
T259	/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.445413378			Jul 29 08:30:10 PM PDT 24	Jul 29 08:35:15 PM PDT 24	3084132720 ps
T221	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2576665175			Jul 29 08:43:48 PM PDT 24	Jul 29 08:51:33 PM PDT 24	3494554254 ps
T389	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.734380528			Jul 29 08:47:18 PM PDT 24	Jul 29 08:52:33 PM PDT 24	4086937220 ps
T908	/workspace/coverage/default/0.chip_sw_uart_smoketest.1833416152			Jul 29 08:25:15 PM PDT 24	Jul 29 08:28:23 PM PDT 24	3090006068 ps
T253	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.140258410			Jul 29 08:45:52 PM PDT 24	Jul 29 08:52:51 PM PDT 24	4330640872 ps
T114	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2003413549			Jul 29 08:30:41 PM PDT 24	Jul 29 08:33:51 PM PDT 24	2889679558 ps
T172	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3044776323			Jul 29 08:15:03 PM PDT 24	Jul 29 08:26:42 PM PDT 24	4363596968 ps
T160	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.4275554668			Jul 29 08:15:39 PM PDT 24	Jul 29 08:25:37 PM PDT 24	4772788952 ps
T17	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1384096935			Jul 29 08:27:55 PM PDT 24	Jul 29 08:34:33 PM PDT 24	7713639344 ps
T103	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2634141872			Jul 29 08:17:53 PM PDT 24	Jul 29 08:20:34 PM PDT 24	3008901201 ps
T104	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1570549216			Jul 29 08:44:19 PM PDT 24	Jul 29 08:51:21 PM PDT 24	3944162464 ps
T105	/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.2912527884			Jul 29 08:26:45 PM PDT 24	Jul 29 08:34:25 PM PDT 24	3939268350 ps
T106	/workspace/coverage/default/2.chip_sw_aes_idle.4174630413			Jul 29 08:33:09 PM PDT 24	Jul 29 08:36:58 PM PDT 24	2408534908 ps
T107	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.848202023			Jul 29 08:51:32 PM PDT 24	Jul 29 08:58:12 PM PDT 24	3782984216 ps
T108	/workspace/coverage/default/4.chip_sw_uart_tx_rx.3833860187			Jul 29 08:41:18 PM PDT 24	Jul 29 08:54:31 PM PDT 24	4963219110 ps
T109	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.4267107061			Jul 29 08:42:16 PM PDT 24	Jul 29 09:23:58 PM PDT 24	13116583960 ps
T110	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3628576629			Jul 29 08:28:24 PM PDT 24	Jul 29 08:48:31 PM PDT 24	6606269212 ps
T111	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.544645309			Jul 29 08:39:54 PM PDT 24	Jul 29 08:43:49 PM PDT 24	2940422135 ps
T66	/workspace/coverage/default/2.chip_sw_alert_handler_escalation.981025799			Jul 29 08:37:16 PM PDT 24	Jul 29 08:47:03 PM PDT 24	4702070252 ps
T721	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.1894402982			Jul 29 08:35:21 PM PDT 24	Jul 29 08:44:06 PM PDT 24	5434002610 ps
T68	/workspace/coverage/default/0.chip_jtag_mem_access.106413208			Jul 29 08:08:43 PM PDT 24	Jul 29 08:33:51 PM PDT 24	14101849396 ps
T762	/workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.285466077			Jul 29 08:30:59 PM PDT 24	Jul 29 08:57:29 PM PDT 24	8100781100 ps
T43	/workspace/coverage/default/2.rom_e2e_shutdown_output.2244831350			Jul 29 08:46:19 PM PDT 24	Jul 29 09:40:53 PM PDT 24	23380402265 ps
T60	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.3007840538			Jul 29 08:17:47 PM PDT 24	Jul 29 08:26:37 PM PDT 24	5093443000 ps
T189	/workspace/coverage/default/2.rom_e2e_asm_init_rma.677621060			Jul 29 08:44:12 PM PDT 24	Jul 29 09:37:04 PM PDT 24	14938961540 ps
T14	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.378449924			Jul 29 08:45:23 PM PDT 24	Jul 29 08:53:06 PM PDT 24	4109964152 ps
T61	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2530407674			Jul 29 08:46:35 PM PDT 24	Jul 29 09:02:20 PM PDT 24	14364951845 ps
T15	/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.671937902			Jul 29 08:32:53 PM PDT 24	Jul 29 08:40:23 PM PDT 24	3916066160 ps
T909	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2575611477			Jul 29 08:26:29 PM PDT 24	Jul 29 08:34:56 PM PDT 24	4497588400 ps
T356	/workspace/coverage/default/40.chip_sw_all_escalation_resets.25993849			Jul 29 08:45:30 PM PDT 24	Jul 29 08:54:34 PM PDT 24	5301180510 ps
T173	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2237641467			Jul 29 08:28:18 PM PDT 24	Jul 29 09:12:16 PM PDT 24	11457965384 ps
T752	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013849373			Jul 29 08:45:11 PM PDT 24	Jul 29 08:52:10 PM PDT 24	4115687728 ps
T768	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2291284811			Jul 29 08:50:33 PM PDT 24	Jul 29 08:57:23 PM PDT 24	3633831392 ps
T460	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2122184151			Jul 29 08:30:01 PM PDT 24	Jul 29 08:34:16 PM PDT 24	3469056876 ps
T69	/workspace/coverage/default/0.chip_tap_straps_testunlock0.81213259			Jul 29 08:15:24 PM PDT 24	Jul 29 08:17:44 PM PDT 24	2509265054 ps
T360	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.198567412			Jul 29 08:15:05 PM PDT 24	Jul 29 09:02:15 PM PDT 24	31384839028 ps
T145	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.112584855			Jul 29 08:42:29 PM PDT 24	Jul 29 09:09:11 PM PDT 24	13571404769 ps
T357	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3127588729			Jul 29 08:52:16 PM PDT 24	Jul 29 09:01:20 PM PDT 24	5354195604 ps
T910	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2629216407			Jul 29 08:39:17 PM PDT 24	Jul 29 08:44:10 PM PDT 24	2697768920 ps
T148	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.100015246			Jul 29 08:14:44 PM PDT 24	Jul 29 08:27:53 PM PDT 24	10469090753 ps
T146	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.220915008			Jul 29 08:38:18 PM PDT 24	Jul 29 08:50:29 PM PDT 24	5123619936 ps
T911	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.3138473659			Jul 29 08:37:33 PM PDT 24	Jul 29 08:41:01 PM PDT 24	3312208581 ps
T399	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4062394609			Jul 29 08:34:24 PM PDT 24	Jul 29 09:34:19 PM PDT 24	15347739608 ps
T70	/workspace/coverage/default/3.chip_tap_straps_rma.2648494140			Jul 29 08:40:29 PM PDT 24	Jul 29 08:49:30 PM PDT 24	5828382419 ps
T377	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.914929649			Jul 29 08:31:48 PM PDT 24	Jul 29 09:39:05 PM PDT 24	15448484020 ps
T16	/workspace/coverage/default/1.chip_sw_gpio.3880568773			Jul 29 08:27:58 PM PDT 24	Jul 29 08:36:04 PM PDT 24	3740327025 ps
T126	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.3952128153			Jul 29 08:16:14 PM PDT 24	Jul 30 02:02:11 AM PDT 24	142895581304 ps
T751	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1702347872			Jul 29 08:42:14 PM PDT 24	Jul 29 08:49:32 PM PDT 24	4031551568 ps
T407	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.769145143			Jul 29 08:47:12 PM PDT 24	Jul 29 08:54:35 PM PDT 24	4081903004 ps
T274	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.365238482			Jul 29 08:30:04 PM PDT 24	Jul 29 09:42:36 PM PDT 24	14210773119 ps
T759	/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1563647056			Jul 29 08:47:55 PM PDT 24	Jul 29 08:56:18 PM PDT 24	3684338088 ps
T120	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3952445157			Jul 29 08:33:25 PM PDT 24	Jul 29 08:45:49 PM PDT 24	20313417362 ps
T320	/workspace/coverage/default/1.chip_plic_all_irqs_0.1809154648			Jul 29 08:30:52 PM PDT 24	Jul 29 08:51:17 PM PDT 24	5586706712 ps
T143	/workspace/coverage/default/2.chip_sw_power_idle_load.3816658504			Jul 29 08:40:05 PM PDT 24	Jul 29 08:47:29 PM PDT 24	4212078104 ps
T741	/workspace/coverage/default/2.chip_sw_hmac_oneshot.2142462140			Jul 29 08:37:31 PM PDT 24	Jul 29 08:43:39 PM PDT 24	3293651710 ps
T224	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3421551247			Jul 29 08:15:33 PM PDT 24	Jul 29 08:37:04 PM PDT 24	8734442844 ps
T912	/workspace/coverage/default/1.chip_sw_aes_idle.3029783556			Jul 29 08:30:27 PM PDT 24	Jul 29 08:33:38 PM PDT 24	2783584324 ps
T368	/workspace/coverage/default/73.chip_sw_all_escalation_resets.3327594173			Jul 29 08:50:26 PM PDT 24	Jul 29 08:57:47 PM PDT 24	4513104350 ps
T219	/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1257059285			Jul 29 08:44:41 PM PDT 24	Jul 29 09:05:08 PM PDT 24	8169127404 ps
T372	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2466872099			Jul 29 08:37:31 PM PDT 24	Jul 29 08:47:48 PM PDT 24	4944001800 ps
T373	/workspace/coverage/default/3.chip_sw_uart_tx_rx.1260378735			Jul 29 08:40:41 PM PDT 24	Jul 29 08:50:15 PM PDT 24	4445597252 ps
T162	/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119619587			Jul 29 08:40:34 PM PDT 24	Jul 29 08:47:00 PM PDT 24	4155770680 ps
T374	/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3904375108			Jul 29 08:15:16 PM PDT 24	Jul 29 08:22:01 PM PDT 24	4688246532 ps
T375	/workspace/coverage/default/0.chip_sw_example_concurrency.1364584156			Jul 29 08:13:10 PM PDT 24	Jul 29 08:16:23 PM PDT 24	2467991856 ps
T376	/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3489480652			Jul 29 08:48:34 PM PDT 24	Jul 29 08:56:43 PM PDT 24	3527606934 ps
T318	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4193533727			Jul 29 08:34:42 PM PDT 24	Jul 29 08:55:57 PM PDT 24	11194115933 ps
T178	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.447765364			Jul 29 08:31:22 PM PDT 24	Jul 29 09:58:35 PM PDT 24	43164228545 ps
T212	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.595861436			Jul 29 08:49:57 PM PDT 24	Jul 29 08:55:40 PM PDT 24	3989664912 ps
T742	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.3176939685			Jul 29 08:16:31 PM PDT 24	Jul 29 08:20:32 PM PDT 24	2649478410 ps
T147	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2810802640			Jul 29 08:14:54 PM PDT 24	Jul 29 08:24:50 PM PDT 24	3888974192 ps
T170	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2397956545			Jul 29 08:28:32 PM PDT 24	Jul 29 08:30:44 PM PDT 24	2486289297 ps
T393	/workspace/coverage/default/75.chip_sw_all_escalation_resets.187839845			Jul 29 08:50:13 PM PDT 24	Jul 29 08:59:23 PM PDT 24	5469665640 ps
T913	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.891177693			Jul 29 08:41:45 PM PDT 24	Jul 29 08:54:56 PM PDT 24	4418836367 ps
T914	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.862104399			Jul 29 08:44:41 PM PDT 24	Jul 29 09:49:09 PM PDT 24	15271445752 ps
T319	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1033122762			Jul 29 08:28:19 PM PDT 24	Jul 29 08:47:35 PM PDT 24	10246138400 ps
T915	/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.820113492			Jul 29 08:30:30 PM PDT 24	Jul 29 09:21:14 PM PDT 24	11636171598 ps
T539	/workspace/coverage/default/66.chip_sw_all_escalation_resets.2786697193			Jul 29 08:48:22 PM PDT 24	Jul 29 08:59:14 PM PDT 24	5839110184 ps
T749	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3825939139			Jul 29 08:30:01 PM PDT 24	Jul 29 08:47:45 PM PDT 24	8075157258 ps
T119	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.3169556109			Jul 29 08:28:48 PM PDT 24	Jul 29 09:50:17 PM PDT 24	28769543574 ps
T540	/workspace/coverage/default/86.chip_sw_all_escalation_resets.4050109277			Jul 29 08:50:50 PM PDT 24	Jul 29 08:59:48 PM PDT 24	6335115350 ps
T311	/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.444838089			Jul 29 08:43:06 PM PDT 24	Jul 29 08:59:59 PM PDT 24	13374780083 ps
T121	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.134541844			Jul 29 08:17:59 PM PDT 24	Jul 29 08:38:21 PM PDT 24	5591400428 ps
T18	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1892270666			Jul 29 08:28:05 PM PDT 24	Jul 29 08:59:16 PM PDT 24	21717819544 ps
T916	/workspace/coverage/default/1.chip_sw_csrng_smoketest.517648895			Jul 29 08:31:51 PM PDT 24	Jul 29 08:36:39 PM PDT 24	3136413752 ps
T343	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2738168213			Jul 29 08:14:46 PM PDT 24	Jul 29 08:26:17 PM PDT 24	4269051973 ps
T76	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.865585229			Jul 29 08:28:51 PM PDT 24	Jul 29 08:40:04 PM PDT 24	5392612930 ps
T917	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4128608895			Jul 29 08:27:03 PM PDT 24	Jul 29 08:37:03 PM PDT 24	3703178974 ps
T176	/workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.224620179			Jul 29 08:37:54 PM PDT 24	Jul 29 08:47:23 PM PDT 24	4697549472 ps
T181	/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.2196164127			Jul 29 08:15:28 PM PDT 24	Jul 29 08:17:27 PM PDT 24	2922819602 ps
T171	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.4265022262			Jul 29 08:34:23 PM PDT 24	Jul 29 08:36:14 PM PDT 24	2955088419 ps
T11	/workspace/coverage/default/1.chip_sw_power_virus.3692461097			Jul 29 08:36:58 PM PDT 24	Jul 29 08:59:17 PM PDT 24	5824851592 ps
T174	/workspace/coverage/default/39.chip_sw_all_escalation_resets.1557404777			Jul 29 08:47:18 PM PDT 24	Jul 29 08:57:47 PM PDT 24	5178537340 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3612348015			Jul 29 08:13:51 PM PDT 24	Jul 29 08:21:36 PM PDT 24	3701779704 ps
T164	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.325697372			Jul 29 08:44:53 PM PDT 24	Jul 29 08:51:10 PM PDT 24	3909722424 ps
T226	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1001569642			Jul 29 08:37:42 PM PDT 24	Jul 29 08:45:48 PM PDT 24	4962487162 ps
T369	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1351320989			Jul 29 08:45:53 PM PDT 24	Jul 29 08:53:29 PM PDT 24	4600810080 ps
T229	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3887945193			Jul 29 08:31:51 PM PDT 24	Jul 29 08:51:23 PM PDT 24	9033893560 ps
T275	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2797393033			Jul 29 08:29:39 PM PDT 24	Jul 29 09:43:30 PM PDT 24	14904902940 ps
T918	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.447166297			Jul 29 08:13:07 PM PDT 24	Jul 29 08:16:34 PM PDT 24	3049284318 ps
T919	/workspace/coverage/default/1.chip_sw_uart_smoketest.1077392039			Jul 29 08:34:46 PM PDT 24	Jul 29 08:39:28 PM PDT 24	2458715490 ps
T149	/workspace/coverage/default/2.chip_sw_otbn_smoketest.59430492			Jul 29 08:39:41 PM PDT 24	Jul 29 09:04:15 PM PDT 24	7244882512 ps
T237	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.2283331635			Jul 29 08:39:26 PM PDT 24	Jul 29 09:04:39 PM PDT 24	18380157467 ps
T20	/workspace/coverage/default/0.chip_sw_usbdev_config_host.2743283575			Jul 29 08:13:20 PM PDT 24	Jul 29 08:42:16 PM PDT 24	8277035052 ps
T59	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2515676028			Jul 29 08:39:14 PM PDT 24	Jul 29 08:46:42 PM PDT 24	7317137992 ps
T920	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3180124092			Jul 29 08:42:02 PM PDT 24	Jul 29 08:51:24 PM PDT 24	6636251420 ps
T128	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1816874806			Jul 29 08:31:09 PM PDT 24	Jul 29 08:37:45 PM PDT 24	5364895428 ps
T312	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.716124672			Jul 29 08:42:48 PM PDT 24	Jul 29 08:48:54 PM PDT 24	3521571468 ps
T79	/workspace/coverage/default/83.chip_sw_all_escalation_resets.2515531249			Jul 29 08:50:52 PM PDT 24	Jul 29 09:00:06 PM PDT 24	4896461140 ps
T92	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1834123430			Jul 29 08:50:26 PM PDT 24	Jul 29 08:57:44 PM PDT 24	4075190304 ps
T22	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.519603701			Jul 29 08:36:04 PM PDT 24	Jul 29 09:21:03 PM PDT 24	20414937241 ps
T93	/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3836535546			Jul 29 08:39:14 PM PDT 24	Jul 29 08:43:27 PM PDT 24	2386207396 ps
T94	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1550513429			Jul 29 08:16:06 PM PDT 24	Jul 29 08:25:58 PM PDT 24	5026647820 ps
T95	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3391338503			Jul 29 08:31:08 PM PDT 24	Jul 29 10:05:05 PM PDT 24	23739840360 ps
T23	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2794461974			Jul 29 08:15:41 PM PDT 24	Jul 29 08:22:06 PM PDT 24	3794057820 ps
T96	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3774688797			Jul 29 08:29:20 PM PDT 24	Jul 29 08:35:43 PM PDT 24	3207775290 ps
T97	/workspace/coverage/default/1.rom_volatile_raw_unlock.2292272337			Jul 29 08:30:43 PM PDT 24	Jul 29 08:33:00 PM PDT 24	3186882968 ps
T98	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1495179527			Jul 29 08:30:11 PM PDT 24	Jul 29 08:40:33 PM PDT 24	5198393689 ps
T295	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4187009083			Jul 29 08:51:09 PM PDT 24	Jul 29 08:58:29 PM PDT 24	4035254528 ps
T296	/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2302411684			Jul 29 08:40:16 PM PDT 24	Jul 29 08:46:44 PM PDT 24	7015917336 ps
T276	/workspace/coverage/default/1.rom_e2e_shutdown_output.1860372725			Jul 29 08:35:04 PM PDT 24	Jul 29 09:35:25 PM PDT 24	22281641400 ps
T213	/workspace/coverage/default/30.chip_sw_all_escalation_resets.986305697			Jul 29 08:45:12 PM PDT 24	Jul 29 08:55:45 PM PDT 24	5696741300 ps
T297	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2968892			Jul 29 08:14:19 PM PDT 24	Jul 29 08:17:13 PM PDT 24	2854313908 ps
T71	/workspace/coverage/default/4.chip_tap_straps_dev.819727649			Jul 29 08:41:00 PM PDT 24	Jul 29 09:01:57 PM PDT 24	12355030881 ps
T298	/workspace/coverage/default/2.rom_volatile_raw_unlock.4004740569			Jul 29 08:40:51 PM PDT 24	Jul 29 08:43:04 PM PDT 24	2211441909 ps
T179	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2170759227			Jul 29 08:13:48 PM PDT 24	Jul 29 09:51:34 PM PDT 24	46990936250 ps
T299	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2789988372			Jul 29 08:31:51 PM PDT 24	Jul 29 09:20:01 PM PDT 24	34216347735 ps
T87	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2294268151			Jul 29 08:13:41 PM PDT 24	Jul 30 12:06:14 AM PDT 24	79070215129 ps
T122	/workspace/coverage/default/1.chip_sw_edn_boot_mode.2188931417			Jul 29 08:32:30 PM PDT 24	Jul 29 08:42:54 PM PDT 24	2884388588 ps
T144	/workspace/coverage/default/0.chip_sw_power_idle_load.3101328479			Jul 29 08:16:40 PM PDT 24	Jul 29 08:26:35 PM PDT 24	4009950260 ps
T394	/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3475783954			Jul 29 08:17:11 PM PDT 24	Jul 29 08:24:08 PM PDT 24	3361260917 ps
T153	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1112730716			Jul 29 08:30:18 PM PDT 24	Jul 29 11:15:50 PM PDT 24	58669936962 ps
T344	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.691695098			Jul 29 08:39:24 PM PDT 24	Jul 29 08:54:56 PM PDT 24	4821006033 ps
T798	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2462330525			Jul 29 08:44:20 PM PDT 24	Jul 29 08:50:35 PM PDT 24	3456448320 ps
T256	/workspace/coverage/default/1.chip_sw_power_sleep_load.3368846528			Jul 29 08:30:44 PM PDT 24	Jul 29 08:36:55 PM PDT 24	4394028048 ps
T921	/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1099862694			Jul 29 08:33:23 PM PDT 24	Jul 29 08:37:42 PM PDT 24	3262562468 ps
T390	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2223993944			Jul 29 08:28:22 PM PDT 24	Jul 29 09:42:17 PM PDT 24	18710033400 ps
T922	/workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.3282843807			Jul 29 08:15:45 PM PDT 24	Jul 29 09:50:15 PM PDT 24	27941256704 ps
T361	/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.3637457757			Jul 29 08:32:03 PM PDT 24	Jul 29 08:38:50 PM PDT 24	3833142848 ps
T330	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.578486514			Jul 29 08:30:36 PM PDT 24	Jul 29 08:59:53 PM PDT 24	7508806164 ps
T277	/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1066833727			Jul 29 08:22:22 PM PDT 24	Jul 29 09:28:28 PM PDT 24	14392422675 ps
T325	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1568598168			Jul 29 08:25:28 PM PDT 24	Jul 29 08:37:34 PM PDT 24	4624397160 ps
T709	/workspace/coverage/default/99.chip_sw_all_escalation_resets.2961985067			Jul 29 08:51:03 PM PDT 24	Jul 29 09:01:15 PM PDT 24	6146927876 ps
T186	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3893462501			Jul 29 08:38:42 PM PDT 24	Jul 29 08:51:51 PM PDT 24	8183295879 ps
T755	/workspace/coverage/default/6.chip_sw_all_escalation_resets.722864174			Jul 29 08:42:23 PM PDT 24	Jul 29 08:55:13 PM PDT 24	5222304976 ps
T310	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.2729950987			Jul 29 08:35:22 PM PDT 24	Jul 29 09:06:51 PM PDT 24	8406643360 ps
T760	/workspace/coverage/default/82.chip_sw_all_escalation_resets.1492307165			Jul 29 08:51:04 PM PDT 24	Jul 29 08:59:34 PM PDT 24	4955396404 ps
T923	/workspace/coverage/default/2.rom_keymgr_functest.2340038604			Jul 29 08:40:14 PM PDT 24	Jul 29 08:52:05 PM PDT 24	4718178856 ps
T924	/workspace/coverage/default/2.chip_sw_csrng_kat_test.1586196071			Jul 29 08:34:12 PM PDT 24	Jul 29 08:37:29 PM PDT 24	2875939674 ps
T335	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1486613199			Jul 29 08:26:58 PM PDT 24	Jul 29 08:41:51 PM PDT 24	4974168780 ps
T346	/workspace/coverage/default/0.chip_sival_flash_info_access.1971266299			Jul 29 08:13:42 PM PDT 24	Jul 29 08:17:37 PM PDT 24	3152594308 ps
T308	/workspace/coverage/default/70.chip_sw_all_escalation_resets.2353963324			Jul 29 08:48:25 PM PDT 24	Jul 29 08:57:00 PM PDT 24	5179838308 ps
T750	/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3524722566			Jul 29 08:15:51 PM PDT 24	Jul 29 08:32:28 PM PDT 24	7826326704 ps
T925	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.229476152			Jul 29 08:31:50 PM PDT 24	Jul 29 09:29:25 PM PDT 24	14325252648 ps
T248	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.698647407			Jul 29 08:14:31 PM PDT 24	Jul 29 08:25:06 PM PDT 24	4909684600 ps
T249	/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3581848652			Jul 29 08:27:56 PM PDT 24	Jul 29 08:36:49 PM PDT 24	3428083136 ps
T743	/workspace/coverage/default/11.chip_sw_all_escalation_resets.748919061			Jul 29 08:44:07 PM PDT 24	Jul 29 08:56:00 PM PDT 24	6278750464 ps
T63	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1354374531			Jul 29 08:40:03 PM PDT 24	Jul 29 08:44:15 PM PDT 24	4134242032 ps
T401	/workspace/coverage/default/2.chip_sw_kmac_app_rom.1921756019			Jul 29 08:36:06 PM PDT 24	Jul 29 08:40:11 PM PDT 24	2704252600 ps
T154	/workspace/coverage/default/2.rom_raw_unlock.473309868			Jul 29 08:39:30 PM PDT 24	Jul 29 08:43:41 PM PDT 24	5076501744 ps
T744	/workspace/coverage/default/59.chip_sw_all_escalation_resets.3420833551			Jul 29 08:47:16 PM PDT 24	Jul 29 08:54:11 PM PDT 24	4918117132 ps
T926	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.901374692			Jul 29 08:14:36 PM PDT 24	Jul 29 08:23:46 PM PDT 24	5653469450 ps
T131	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.860434123			Jul 29 08:30:14 PM PDT 24	Jul 29 08:45:43 PM PDT 24	7046361430 ps
T462	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2108480528			Jul 29 08:30:59 PM PDT 24	Jul 29 08:46:01 PM PDT 24	5905003132 ps
T8	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3185717799			Jul 29 08:37:36 PM PDT 24	Jul 29 08:44:09 PM PDT 24	2760241873 ps
T350	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2213348691			Jul 29 08:31:08 PM PDT 24	Jul 29 08:41:06 PM PDT 24	4702788586 ps
T261	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.971959097			Jul 29 08:27:27 PM PDT 24	Jul 29 09:04:53 PM PDT 24	24874812214 ps
T35	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2429176367			Jul 29 08:29:35 PM PDT 24	Jul 29 08:35:39 PM PDT 24	5167771812 ps
T927	/workspace/coverage/default/0.chip_sw_coremark.1536875303			Jul 29 08:18:04 PM PDT 24	Jul 30 12:27:25 AM PDT 24	72063415322 ps
T313	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989939909			Jul 29 08:46:59 PM PDT 24	Jul 29 08:52:44 PM PDT 24	3643170730 ps
T928	/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.569276456			Jul 29 08:16:18 PM PDT 24	Jul 29 08:25:26 PM PDT 24	4081652750 ps
T929	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2454954689			Jul 29 08:28:48 PM PDT 24	Jul 29 09:26:05 PM PDT 24	14966647747 ps
T180	/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2561154054			Jul 29 08:28:00 PM PDT 24	Jul 29 09:56:17 PM PDT 24	47861597626 ps
T227	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.714080672			Jul 29 08:31:32 PM PDT 24	Jul 29 08:39:42 PM PDT 24	3967887160 ps
T72	/workspace/coverage/default/0.chip_sw_usbdev_pullup.3224076544			Jul 29 08:14:00 PM PDT 24	Jul 29 08:18:59 PM PDT 24	3545402570 ps
T930	/workspace/coverage/default/4.chip_tap_straps_prod.2987307190			Jul 29 08:41:34 PM PDT 24	Jul 29 09:00:37 PM PDT 24	9951815623 ps
T458	/workspace/coverage/default/2.chip_sw_flash_crash_alert.3973805284			Jul 29 08:39:35 PM PDT 24	Jul 29 08:49:53 PM PDT 24	5147402160 ps
T756	/workspace/coverage/default/56.chip_sw_all_escalation_resets.3239997585			Jul 29 08:48:17 PM PDT 24	Jul 29 08:59:42 PM PDT 24	4950324052 ps
T187	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.551170942			Jul 29 08:30:46 PM PDT 24	Jul 29 08:35:01 PM PDT 24	3274680593 ps
T250	/workspace/coverage/default/65.chip_sw_all_escalation_resets.1746233296			Jul 29 08:48:37 PM PDT 24	Jul 29 08:59:00 PM PDT 24	6093399116 ps
T268	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3364846180			Jul 29 08:26:14 PM PDT 24	Jul 29 08:39:10 PM PDT 24	6153243884 ps
T260	/workspace/coverage/default/2.chip_sw_rv_timer_irq.145916506			Jul 29 08:35:56 PM PDT 24	Jul 29 08:40:23 PM PDT 24	2490729172 ps
T269	/workspace/coverage/default/0.rom_e2e_jtag_inject_dev.1756137361			Jul 29 08:26:43 PM PDT 24	Jul 29 09:12:45 PM PDT 24	24314302055 ps
T214	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2417133572			Jul 29 08:16:54 PM PDT 24	Jul 29 08:42:32 PM PDT 24	7774092928 ps
T270	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2538327564			Jul 29 08:31:57 PM PDT 24	Jul 29 08:33:44 PM PDT 24	3014726673 ps
T271	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3987018580			Jul 29 08:30:59 PM PDT 24	Jul 29 09:01:28 PM PDT 24	7866456344 ps
T272	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.236504915			Jul 29 08:29:53 PM PDT 24	Jul 29 09:53:09 PM PDT 24	23729619184 ps
T166	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1657182332			Jul 29 08:34:45 PM PDT 24	Jul 30 12:01:54 AM PDT 24	254750029314 ps
T273	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.1083845104			Jul 29 08:15:11 PM PDT 24	Jul 29 08:23:34 PM PDT 24	4160021400 ps
T80	/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.2350310207			Jul 29 08:45:29 PM PDT 24	Jul 29 08:52:24 PM PDT 24	3412474234 ps
T353	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3467783514			Jul 29 08:41:59 PM PDT 24	Jul 29 08:51:47 PM PDT 24	4403373640 ps
T834	/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.775436552			Jul 29 08:42:16 PM PDT 24	Jul 29 08:49:19 PM PDT 24	4205741144 ps
T931	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.776994825			Jul 29 08:26:52 PM PDT 24	Jul 29 08:38:31 PM PDT 24	5093627008 ps
T932	/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.615481469			Jul 29 08:37:18 PM PDT 24	Jul 29 08:42:39 PM PDT 24	2645224432 ps
T776	/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2679585797			Jul 29 08:46:42 PM PDT 24	Jul 29 08:53:56 PM PDT 24	3889147166 ps
T127	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3437844781			Jul 29 08:28:54 PM PDT 24	Jul 29 09:27:54 PM PDT 24	21401991249 ps
T933	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2618332687			Jul 29 08:26:14 PM PDT 24	Jul 29 08:43:09 PM PDT 24	7632091827 ps
T736	/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.208116025			Jul 29 08:47:00 PM PDT 24	Jul 29 08:53:49 PM PDT 24	3630538178 ps
T225	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.84228797			Jul 29 08:36:09 PM PDT 24	Jul 29 09:27:20 PM PDT 24	12704541872 ps
T737	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1488036829			Jul 29 08:44:07 PM PDT 24	Jul 29 08:53:29 PM PDT 24	3734136480 ps
T188	/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3433312678			Jul 29 08:38:45 PM PDT 24	Jul 29 08:43:30 PM PDT 24	3256816996 ps
T934	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3584115310			Jul 29 08:34:13 PM PDT 24	Jul 29 08:58:14 PM PDT 24	15593872820 ps
T771	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.3420521379			Jul 29 08:47:30 PM PDT 24	Jul 29 08:55:17 PM PDT 24	4192184700 ps
T935	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2341748963			Jul 29 08:26:43 PM PDT 24	Jul 29 08:34:30 PM PDT 24	3982450134 ps
T191	/workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.4025934873			Jul 29 08:22:23 PM PDT 24	Jul 29 08:36:10 PM PDT 24	7269758728 ps
T729	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1288984421			Jul 29 08:28:15 PM PDT 24	Jul 29 08:32:20 PM PDT 24	3262956860 ps
T182	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2732913777			Jul 29 08:27:00 PM PDT 24	Jul 29 09:14:24 PM PDT 24	33545102992 ps
T936	/workspace/coverage/default/2.chip_sw_aes_entropy.1155916683			Jul 29 08:33:59 PM PDT 24	Jul 29 08:37:47 PM PDT 24	2825809644 ps
T937	/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2854701042			Jul 29 08:25:48 PM PDT 24	Jul 29 08:46:33 PM PDT 24	9236096859 ps
T938	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3181018348			Jul 29 08:32:21 PM PDT 24	Jul 29 08:51:44 PM PDT 24	5236249037 ps
T939	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2465062012			Jul 29 08:44:34 PM PDT 24	Jul 29 09:29:24 PM PDT 24	11007200085 ps
T940	/workspace/coverage/default/2.chip_sw_example_flash.1301702653			Jul 29 08:33:38 PM PDT 24	Jul 29 08:38:56 PM PDT 24	2370817560 ps
T761	/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2875831805			Jul 29 08:48:44 PM PDT 24	Jul 29 08:56:11 PM PDT 24	4483658050 ps