dashboard | hierarchy | modlist | groups | tests | asserts

Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 4 0 4 100.00
Crosses 1 0 1 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error 2 0 2 100.00 100 1 1 2
cp_opcode 1 0 1 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_d_chan_cov_cg_cc 1 0 1 100.00 100 1 1 0

Go back
Group Instances:
tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.uart2_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.uart3_agent.cov::m_tl_d_chan_cov_cg
tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_tl_d_chan_cov_cg

Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 129740 1 T73 15 T74 33 T75 150
auto[1] 64634 1 T73 8 T74 1 T75 51



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 48896 1 T73 3 T74 4 T75 26



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 136997 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 57377 1 T73 9 T74 13 T75 71



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 15150 1 T73 2 T74 4 T75 11


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 128890 1 T73 9 T74 21 T75 141
auto[1] 71049 1 T73 7 T74 6 T75 28



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 50743 1 T73 5 T74 4 T75 18



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 140780 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 59159 1 T73 6 T74 4 T75 32



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 16006 1 T73 2 T74 1 T75 4


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 130889 1 T73 21 T74 17 T75 127
auto[1] 67702 1 T73 1 T74 7 T75 60



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 49769 1 T73 5 T74 7 T75 22



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 140084 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 58507 1 T73 2 T74 2 T75 59



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 15532 1 T75 6 T152 3 T463 1


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 137714 1 T73 18 T74 11 T75 89
auto[1] 74985 1 T74 17 T75 69 T152 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 53377 1 T73 8 T74 4 T75 20



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 149938 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 62761 1 T73 5 T74 7 T75 44



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 16583 1 T73 2 T75 6 T152 4


Summary for Variable cp_error

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_error

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 123921 1 T73 12 T74 14 T75 96
auto[1] 65758 1 T73 1 T74 11 T75 69



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] 48311 1 T73 2 T74 3 T75 12



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 132317 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 57362 1 T73 8 T74 5 T75 40



Summary for Cross tl_d_chan_cov_cg_cc

Samples crossed: cp_opcode cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for tl_d_chan_cov_cg_cc

Bins
cp_opcodecp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x1] biggest_size 15237 1 T73 2 T152 2 T463 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%