Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	496	1			T545	1		T434	1		T419	1
all_values[1]	540	1			T419	3		T546	1		T415	3
all_values[2]	471	1			T415	4		T429	3		T877	1
all_values[3]	514	1			T255	1		T538	1		T419	1
all_values[4]	500	1			T538	3		T419	3		T546	1
all_values[5]	485	1			T255	2		T419	7		T546	1
all_values[6]	443	1			T434	1		T419	1		T551	2
all_values[7]	495	1			T434	1		T538	1		T419	1
all_values[8]	556	1			T255	2		T419	3		T546	1
all_values[9]	490	1			T537	1		T419	5		T546	1
all_values[10]	495	1			T419	2		T546	1		T415	4
all_values[11]	520	1			T545	1		T555	1		T537	1
all_values[12]	495	1			T419	4		T551	1		T415	4
all_values[13]	448	1			T537	2		T538	2		T419	3
all_values[14]	491	1			T255	1		T434	1		T537	1
all_values[15]	488	1			T255	1		T545	1		T434	1
all_values[16]	532	1			T255	1		T419	7		T546	1
all_values[17]	499	1			T419	2		T415	4		T429	5
all_values[18]	507	1			T537	1		T538	3		T419	3
all_values[19]	553	1			T419	6		T546	1		T415	5
all_values[20]	495	1			T255	1		T419	2		T546	2
all_values[21]	517	1			T255	1		T537	1		T538	1
all_values[22]	563	1			T537	2		T419	4		T546	1
all_values[23]	484	1			T537	1		T419	4		T546	2
all_values[24]	484	1			T434	1		T419	9		T415	2
all_values[25]	485	1			T538	2		T419	1		T546	1
all_values[26]	521	1			T255	1		T434	1		T537	1
all_values[27]	481	1			T255	2		T537	1		T538	3
all_values[28]	490	1			T255	2		T555	1		T538	1
all_values[29]	499	1			T545	1		T434	3		T538	1
all_values[30]	459	1			T545	1		T538	1		T419	2
all_values[31]	499	1			T537	2		T538	2		T419	3
all_values[32]	493	1			T434	1		T538	1		T419	1
all_values[33]	489	1			T255	1		T545	1		T537	2
all_values[34]	490	1			T555	1		T419	2		T415	7
all_values[35]	505	1			T537	1		T538	2		T419	1
all_values[36]	488	1			T537	1		T538	1		T419	4
all_values[37]	493	1			T555	1		T546	1		T415	3
all_values[38]	527	1			T255	1		T434	1		T419	1
all_values[39]	449	1			T537	1		T538	1		T419	4
all_values[40]	501	1			T537	1		T419	2		T415	4
all_values[41]	487	1			T434	1		T537	1		T419	3
all_values[42]	475	1			T419	4		T546	2		T415	3
all_values[43]	478	1			T537	1		T419	4		T546	3
all_values[44]	457	1			T434	1		T537	1		T546	2
all_values[45]	525	1			T255	1		T537	1		T419	4
all_values[46]	459	1			T434	1		T419	3		T415	5
all_values[47]	477	1			T255	1		T538	2		T419	2
all_values[48]	481	1			T538	1		T419	6		T415	1
all_values[49]	502	1			T537	1		T538	1		T419	3