Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3515	1			T75	5		T255	3		T440	4
all_values[1]	3545	1			T75	6		T152	1		T255	2
all_values[2]	3750	1			T75	2		T152	1		T255	1
all_values[3]	3758	1			T75	3		T152	3		T255	1
all_values[4]	3617	1			T75	1		T152	3		T255	1
all_values[5]	3691	1			T75	2		T152	1		T440	2
all_values[6]	3570	1			T75	9		T152	1		T255	1
all_values[7]	3625	1			T75	1		T255	3		T440	1
all_values[8]	3488	1			T75	5		T255	2		T440	6
all_values[9]	3627	1			T75	2		T152	3		T255	1
all_values[10]	3517	1			T75	4		T255	2		T440	2
all_values[11]	3559	1			T75	2		T152	1		T255	4
all_values[12]	3621	1			T75	3		T152	1		T255	1
all_values[13]	3681	1			T75	4		T440	4		T537	7
all_values[14]	3538	1			T152	2		T255	1		T440	1
all_values[15]	3619	1			T255	1		T440	2		T537	3
all_values[16]	3600	1			T75	1		T152	3		T255	2
all_values[17]	3751	1			T75	4		T255	2		T537	8
all_values[18]	3506	1			T75	1		T152	2		T255	3
all_values[19]	3546	1			T75	2		T255	2		T537	5
all_values[20]	3604	1			T75	3		T152	1		T255	3
all_values[21]	3585	1			T75	4		T152	1		T255	2
all_values[22]	3688	1			T75	4		T152	1		T255	2
all_values[23]	3620	1			T75	5		T152	1		T255	2
all_values[24]	3682	1			T152	2		T440	3		T537	1
all_values[25]	3619	1			T75	1		T255	3		T440	2
all_values[26]	3515	1			T75	3		T152	1		T255	3
all_values[27]	3525	1			T75	2		T255	1		T440	4
all_values[28]	3660	1			T440	1		T537	4		T436	6
all_values[29]	3534	1			T75	5		T152	1		T255	1
all_values[30]	3614	1			T75	2		T152	4		T440	1
all_values[31]	3661	1			T75	1		T152	1		T440	4
all_values[32]	3468	1			T75	2		T152	2		T440	1
all_values[33]	3605	1			T75	3		T152	1		T537	7
all_values[34]	3678	1			T75	1		T440	1		T537	2
all_values[35]	3662	1			T75	2		T152	1		T255	3
all_values[36]	3478	1			T75	3		T152	2		T255	1
all_values[37]	3490	1			T75	7		T152	3		T255	2
all_values[38]	3567	1			T75	1		T152	3		T255	1
all_values[39]	3690	1			T75	2		T152	5		T255	4
all_values[40]	3532	1			T75	3		T440	2		T537	4
all_values[41]	3602	1			T75	3		T152	2		T440	4
all_values[42]	3615	1			T75	4		T152	1		T255	2
all_values[43]	3640	1			T75	2		T255	2		T440	3
all_values[44]	3502	1			T75	5		T152	3		T255	3
all_values[45]	3657	1			T75	4		T255	3		T440	3
all_values[46]	3612	1			T75	3		T152	1		T255	2
all_values[47]	3610	1			T75	2		T152	1		T255	3
all_values[48]	3642	1			T75	3		T152	2		T255	2
all_values[49]	3524	1			T75	2		T152	2		T255	1
all_values[50]	3710	1			T75	2		T255	1		T440	1
all_values[51]	3730	1			T75	4		T255	1		T440	3
all_values[52]	3668	1			T75	1		T152	1		T255	1
all_values[53]	3653	1			T75	6		T152	1		T255	1
all_values[54]	3609	1			T75	2		T255	3		T440	1
all_values[55]	3630	1			T75	3		T152	1		T255	1
all_values[56]	3596	1			T75	4		T152	1		T255	1
all_values[57]	3552	1			T75	2		T152	1		T255	1
all_values[58]	3668	1			T75	2		T152	1		T255	2
all_values[59]	3691	1			T75	3		T440	2		T537	3
all_values[60]	3582	1			T75	1		T255	1		T440	2
all_values[61]	3512	1			T75	4		T152	2		T255	1
all_values[62]	3597	1			T255	3		T440	2		T537	1
all_values[63]	3601	1			T75	4		T152	1		T255	2