Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.flash_ctrl__prim_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	148861	1			T70	30		T71	40		T72	46
values[2]	5377	1			T122	2		T255	2		T557	1
values[3]	2834	1			T558	2		T479	146		T544	1
values[4]	1887	1			T558	1		T479	64		T510	3
values[5]	1475	1			T558	3		T479	41		T510	1
values[6]	1367	1			T558	2		T479	41		T510	2
values[7]	1228	1			T558	4		T479	16		T510	1
values[8]	1070	1			T558	2		T479	8		T510	1
values[9]	971	1			T558	4		T479	2		T510	3
values[10]	754	1			T558	5		T479	8		T510	4
values[11]	779	1			T558	3		T479	12		T510	5
values[12]	641	1			T558	3		T479	15		T510	6
values[13]	586	1			T558	6		T479	15		T510	4
values[14]	517	1			T558	4		T479	34		T510	1
values[15]	496	1			T558	6		T479	40		T510	2
values[16]	468	1			T558	1		T479	33		T510	2
values[17]	457	1			T558	6		T479	42		T510	1
values[18]	470	1			T558	5		T479	28		T510	1
values[19]	473	1			T558	5		T479	25		T510	5
values[20]	400	1			T558	6		T479	23		T510	2
values[21]	295	1			T558	2		T479	21		T510	1
values[22]	251	1			T558	1		T479	13		T510	2
values[23]	217	1			T558	3		T479	11		T510	1
values[24]	195	1			T558	1		T479	17		T510	4
values[25]	227	1			T558	5		T479	12		T510	4
values[26]	143	1			T558	2		T479	6		T510	3
values[27]	117	1			T558	1		T479	6		T510	7
values[28]	149	1			T558	2		T479	16		T510	4
values[29]	180	1			T558	1		T479	15		T510	4
values[30]	166	1			T558	2		T479	3		T510	6
values[31]	167	1			T558	3		T510	4		T885	28
values[32]	125	1			T558	3		T510	2		T885	20
values[33]	165	1			T558	2		T510	1		T885	51
values[34]	155	1			T558	1		T510	4		T885	53
values[35]	125	1			T558	2		T510	1		T885	21
values[36]	133	1			T558	3		T510	1		T885	6
values[37]	116	1			T558	3		T510	7		T885	3
values[38]	109	1			T558	3		T510	9		T866	1
values[39]	84	1			T558	7		T510	3		T866	1
values[40]	85	1			T558	6		T510	3		T866	1
values[41]	75	1			T558	6		T510	3		T866	1
values[42]	90	1			T558	5		T510	3		T866	1
values[43]	88	1			T558	3		T510	2		T866	1
values[44]	53	1			T558	1		T510	1		T866	1
values[45]	61	1			T558	3		T510	6		T866	1
values[46]	87	1			T558	3		T510	8		T866	1
values[47]	53	1			T558	2		T510	2		T866	1
values[48]	63	1			T558	2		T510	2		T866	1
values[49]	62	1			T558	1		T510	2		T866	1
values[50]	73	1			T558	1		T510	6		T866	1
values[51]	61	1			T558	3		T510	3		T866	1
values[52]	59	1			T558	2		T510	2		T866	1
values[53]	58	1			T558	1		T510	2		T866	1
values[54]	60	1			T558	2		T510	2		T866	1
values[55]	49	1			T558	1		T510	2		T866	1
values[56]	60	1			T558	1		T510	1		T866	1
values[57]	75	1			T558	3		T510	2		T866	1
values[58]	61	1			T558	5		T510	1		T866	1
values[59]	65	1			T558	3		T510	1		T866	1
values[60]	58	1			T558	1		T510	4		T866	1
values[61]	51	1			T558	2		T510	2		T866	1
values[62]	55	1			T558	4		T510	1		T866	1
values[63]	50	1			T558	2		T510	2		T866	1
values[64]	54	1			T558	1		T510	1		T866	1
values[65]	50	1			T558	1		T510	3		T866	1
values[66]	54	1			T558	1		T510	4		T866	1
values[67]	53	1			T558	3		T510	1		T866	1
values[68]	57	1			T558	1		T510	1		T866	1
values[69]	70	1			T558	4		T510	5		T866	1
values[70]	59	1			T558	3		T510	2		T866	1
values[71]	65	1			T558	3		T510	1		T866	1
values[72]	58	1			T558	1		T510	2		T866	1
values[73]	56	1			T558	1		T510	3		T866	1
values[74]	56	1			T558	3		T510	1		T866	1
values[75]	64	1			T558	3		T510	3		T866	1
values[76]	59	1			T558	1		T510	4		T866	1
values[77]	56	1			T558	2		T510	4		T866	1
values[78]	68	1			T558	7		T510	1		T866	4
values[79]	81	1			T558	4		T510	1		T866	7
values[80]	69	1			T558	4		T510	4		T866	4
values[81]	95	1			T558	4		T510	4		T866	2
values[82]	67	1			T558	4		T510	3		T866	1
values[83]	60	1			T558	4		T510	1		T866	2
values[84]	69	1			T558	3		T510	1		T866	3
values[85]	69	1			T558	1		T510	3		T866	4
values[86]	65	1			T558	4		T510	2		T866	6
values[87]	59	1			T558	4		T510	1		T866	2
values[88]	85	1			T558	2		T510	2		T866	6
values[89]	67	1			T558	1		T510	3		T866	1
values[90]	68	1			T558	2		T510	3		T866	2
values[91]	77	1			T558	1		T510	5		T866	2
values[92]	94	1			T558	3		T510	11		T866	6
values[93]	94	1			T558	3		T510	7		T866	5
values[94]	65	1			T558	1		T510	4		T866	1
values[95]	73	1			T558	1		T510	5		T866	2
values[96]	96	1			T558	3		T510	5		T866	2
values[97]	92	1			T558	5		T510	6		T866	1
values[98]	81	1			T558	3		T510	4		T866	4
values[99]	85	1			T558	11		T510	5		T866	3
values[100]	91	1			T558	6		T510	5		T866	1
values[101]	91	1			T558	6		T510	2		T866	1
values[102]	78	1			T558	2		T510	2		T866	3
values[103]	100	1			T558	4		T510	3		T866	3
values[104]	102	1			T558	11		T510	8		T866	5
values[105]	111	1			T558	9		T510	5		T866	7
values[106]	110	1			T558	1		T510	3		T866	6
values[107]	88	1			T558	3		T510	1		T866	5
values[108]	105	1			T558	9		T510	4		T866	1
values[109]	100	1			T558	4		T510	9		T866	3
values[110]	106	1			T558	4		T510	4		T866	2
values[111]	101	1			T558	7		T510	1		T866	2
values[112]	102	1			T558	6		T510	4		T866	3
values[113]	119	1			T558	11		T510	2		T866	2
values[114]	104	1			T558	8		T510	3		T866	1
values[115]	108	1			T558	11		T510	4		T866	1
values[116]	109	1			T558	5		T510	5		T866	1
values[117]	94	1			T558	4		T510	9		T866	1
values[118]	103	1			T558	5		T510	10		T866	1
values[119]	137	1			T558	4		T510	10		T866	2
values[120]	129	1			T558	5		T510	7		T866	1
values[121]	127	1			T558	2		T510	6		T866	1
values[122]	126	1			T558	4		T510	7		T866	2
values[123]	138	1			T558	8		T510	6		T866	1
values[124]	231	1			T558	34		T510	4		T866	1
values[125]	314	1			T558	32		T510	16		T866	1
values[126]	673	1			T558	39		T510	21		T866	10
values[127]	2504	1			T558	26		T510	19		T866	91
values[128]	4832	1			T558	7		T510	2		T866	200