Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	95.52	93.83	95.38		94.55	97.53	99.61

Total tests in report: 2937

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
39.56	39.56	44.90	44.90	42.97	42.97	31.64	31.64			57.96	57.96	59.79	59.79	0.14	0.14	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1848970300
50.83	11.26	57.61	12.71	56.71	13.74	36.79	5.15			67.42	9.46	84.97	25.17	1.47	1.33	/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2198030863
56.58	5.75	57.61	0.00	58.61	1.90	36.79	0.00			67.42	0.00	84.97	0.00	34.07	32.60	/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.2205432070
61.53	4.95	68.03	10.42	65.86	7.25	39.23	2.44			77.00	9.58	84.97	0.00	34.07	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3460365095
65.28	3.75	68.03	0.00	66.82	0.96	39.26	0.02			77.05	0.06	84.97	0.00	55.53	21.45	/workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.3669075445
68.49	3.22	73.35	5.32	70.88	4.05	42.83	3.57			78.87	1.82	89.51	4.55	55.53	0.00	/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3564229094
71.50	3.00	77.60	4.25	72.21	1.33	46.24	3.41			79.03	0.16	89.51	0.00	64.38	8.85	/workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.18326251
73.77	2.28	80.56	2.96	75.47	3.26	49.44	3.20			82.33	3.29	89.86	0.35	64.96	0.59	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4131939149
75.86	2.09	80.56	0.00	75.47	0.00	61.93	12.49			82.33	0.00	89.86	0.00	65.01	0.05	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3074950577
77.82	1.96	80.56	0.00	75.80	0.33	61.93	0.00			82.39	0.06	89.86	0.00	76.38	11.37	/workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3812870269
79.69	1.86	83.68	3.12	79.58	3.78	62.30	0.37			86.31	3.92	89.86	0.00	76.38	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2967405698
81.30	1.61	84.28	0.59	80.07	0.50	70.29	7.99			86.72	0.41	90.03	0.17	76.38	0.00	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3968767379
82.53	1.23	84.56	0.29	80.23	0.16	76.71	6.42			86.90	0.18	90.38	0.35	76.38	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3754294049
83.58	1.05	86.41	1.85	81.25	1.02	78.98	2.27			87.69	0.80	90.73	0.35	76.38	0.00	/workspace/coverage/default/1.chip_sw_power_virus.2574255404
84.54	0.97	86.41	0.00	81.25	0.00	78.98	0.00			87.69	0.00	90.73	0.00	82.18	5.79	/workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.3613338559
85.44	0.90	87.65	1.24	82.26	1.02	79.24	0.26			88.94	1.25	92.31	1.57	82.22	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.482247357
86.27	0.83	88.38	0.73	82.45	0.18	79.26	0.01			89.16	0.22	96.15	3.85	82.22	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1835503700
87.02	0.75	89.84	1.46	83.54	1.09	80.38	1.12			89.92	0.76	96.15	0.00	82.28	0.06	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3658008823
87.72	0.70	91.09	1.24	84.48	0.94	81.29	0.91			91.04	1.12	96.15	0.00	82.28	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2459534467
88.42	0.70	91.10	0.01	84.49	0.01	85.42	4.14			91.04	0.00	96.15	0.00	82.33	0.05	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.11432395
89.05	0.63	91.63	0.54	86.57	2.09	85.43	0.01			91.81	0.76	96.15	0.00	82.69	0.36	/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.160298614
89.55	0.51	91.63	0.00	86.57	0.00	85.43	0.00			91.81	0.00	96.15	0.00	85.72	3.03	/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.2966528526
89.99	0.44	92.26	0.63	87.16	0.59	86.16	0.73			92.30	0.49	96.33	0.17	85.72	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.2664933268
90.42	0.43	92.26	0.00	87.29	0.13	86.16	0.00			92.32	0.02	96.33	0.00	88.14	2.42	/workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1523269658
90.84	0.42	92.26	0.00	87.29	0.00	86.16	0.00			92.32	0.00	96.33	0.00	90.67	2.53	/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2368172876
91.23	0.39	92.82	0.55	87.58	0.29	87.29	1.12			92.61	0.29	96.33	0.00	90.76	0.09	/workspace/coverage/default/1.chip_jtag_csr_rw.3079458556
91.59	0.36	92.82	0.00	87.58	0.00	88.33	1.05			92.61	0.00	96.33	0.00	91.87	1.10	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1153984907
91.92	0.33	92.82	0.00	87.58	0.00	90.29	1.96			92.61	0.00	96.33	0.00	91.88	0.01	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4072791286
92.22	0.30	92.83	0.01	89.35	1.77	90.29	0.00			92.61	0.00	96.33	0.00	91.93	0.05	/workspace/coverage/cover_reg_top/21.chip_tl_errors.3683152780
92.51	0.29	92.83	0.00	89.39	0.05	90.29	0.00			92.61	0.00	96.33	0.00	93.63	1.70	/workspace/coverage/cover_reg_top/77.xbar_access_same_device.2200747961
92.77	0.26	92.89	0.06	89.46	0.07	90.33	0.04			92.62	0.02	96.33	0.00	94.98	1.35	/workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3786166046
93.02	0.25	92.89	0.00	89.46	0.00	90.33	0.00			92.62	0.00	96.33	0.00	96.46	1.48	/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.4263671253
93.26	0.24	93.44	0.55	89.86	0.40	90.57	0.24			92.88	0.25	96.33	0.00	96.46	0.00	/workspace/coverage/default/2.chip_sw_gpio.2805266917
93.44	0.19	93.72	0.28	90.10	0.24	90.83	0.26			93.18	0.30	96.33	0.00	96.50	0.04	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2283778065
93.59	0.14	93.73	0.01	90.50	0.40	90.84	0.01			93.63	0.45	96.33	0.00	96.50	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.799284437
93.70	0.12	93.89	0.17	90.75	0.26	91.12	0.28			93.63	0.00	96.33	0.00	96.50	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1364530220
93.82	0.12	94.01	0.12	90.84	0.08	91.32	0.20			93.70	0.06	96.50	0.17	96.56	0.06	/workspace/coverage/default/80.chip_sw_all_escalation_resets.715537131
93.93	0.11	94.12	0.11	90.99	0.15	91.61	0.29			93.78	0.08	96.50	0.00	96.57	0.01	/workspace/coverage/default/2.chip_jtag_csr_rw.3738704093
94.04	0.11	94.12	0.00	91.10	0.12	91.61	0.00			93.78	0.00	96.50	0.00	97.10	0.53	/workspace/coverage/cover_reg_top/17.xbar_stress_all.1630572402
94.14	0.10	94.12	0.00	91.10	0.00	92.21	0.60			93.78	0.00	96.50	0.00	97.10	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3827595605
94.22	0.09	94.12	0.00	91.17	0.07	92.21	0.00			93.79	0.02	96.50	0.00	97.53	0.43	/workspace/coverage/cover_reg_top/91.xbar_access_same_device.66299733
94.31	0.08	94.13	0.01	91.40	0.23	92.22	0.01			94.05	0.26	96.50	0.00	97.53	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1663870970
94.39	0.08	94.13	0.00	91.40	0.01	92.69	0.47			94.05	0.00	96.50	0.00	97.53	0.00	/workspace/coverage/default/67.chip_sw_all_escalation_resets.3226343985
94.46	0.08	94.13	0.00	91.86	0.46	92.69	0.00			94.05	0.00	96.50	0.00	97.53	0.00	/workspace/coverage/cover_reg_top/18.chip_tl_errors.331649416
94.53	0.07	94.16	0.03	91.93	0.07	92.80	0.10			94.09	0.04	96.68	0.17	97.53	0.00	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2308463571
94.60	0.07	94.16	0.00	91.93	0.00	93.16	0.36			94.09	0.00	96.68	0.00	97.58	0.05	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3189413241
94.67	0.06	94.16	0.00	91.95	0.02	93.52	0.36			94.09	0.00	96.68	0.00	97.58	0.00	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.546196908
94.73	0.06	94.16	0.00	91.96	0.01	93.52	0.00			94.09	0.00	96.68	0.00	97.93	0.35	/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.3680009205
94.78	0.06	94.24	0.07	92.12	0.16	93.52	0.00			94.20	0.11	96.68	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2920210079
94.83	0.05	94.33	0.09	92.17	0.05	93.66	0.13			94.23	0.03	96.68	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2009944538
94.88	0.04	94.33	0.00	92.17	0.00	93.66	0.00			94.23	0.00	96.68	0.00	98.19	0.26	/workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2154822940
94.92	0.04	94.33	0.00	92.17	0.00	93.91	0.25			94.23	0.00	96.68	0.00	98.19	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3327943765
94.96	0.04	94.34	0.01	92.18	0.01	93.92	0.01			94.26	0.02	96.85	0.17	98.20	0.01	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3156438580
95.00	0.04	94.34	0.01	92.20	0.01	93.93	0.01			94.26	0.01	97.03	0.17	98.21	0.01	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3382655008
95.03	0.04	94.35	0.01	92.21	0.01	93.94	0.01			94.27	0.01	97.20	0.17	98.23	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.3411307158
95.07	0.04	94.35	0.01	92.22	0.01	93.94	0.00			94.28	0.01	97.38	0.17	98.24	0.01	/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.3136401051
95.10	0.03	94.35	0.00	92.25	0.03	94.06	0.12			94.28	0.00	97.38	0.00	98.28	0.05	/workspace/coverage/default/1.chip_sw_alert_test.3442341479
95.13	0.03	94.35	0.00	92.25	0.00	94.26	0.20			94.28	0.00	97.38	0.00	98.28	0.00	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3084077861
95.16	0.03	94.35	0.00	92.42	0.18	94.26	0.00			94.28	0.00	97.38	0.00	98.30	0.01	/workspace/coverage/cover_reg_top/6.chip_tl_errors.1401045205
95.19	0.03	94.35	0.00	92.42	0.00	94.26	0.00			94.28	0.00	97.55	0.17	98.30	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1524583029
95.22	0.03	94.47	0.12	92.44	0.01	94.28	0.02			94.29	0.01	97.55	0.00	98.30	0.00	/workspace/coverage/default/2.rom_e2e_self_hash.4040918753
95.25	0.03	94.47	0.00	92.60	0.16	94.28	0.00			94.29	0.00	97.55	0.00	98.30	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.3203345745
95.27	0.03	94.49	0.01	92.64	0.04	94.38	0.10			94.30	0.01	97.55	0.00	98.30	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3098436734
95.30	0.03	94.56	0.07	92.64	0.00	94.46	0.08			94.30	0.01	97.55	0.00	98.30	0.00	/workspace/coverage/default/4.chip_tap_straps_testunlock0.3627146453
95.33	0.03	94.56	0.00	92.67	0.03	94.46	0.00			94.32	0.02	97.55	0.00	98.40	0.11	/workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.2308739566
95.35	0.02	94.62	0.07	92.72	0.05	94.46	0.00			94.35	0.03	97.55	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1570180852
95.37	0.02	94.70	0.07	92.72	0.00	94.53	0.07			94.35	0.00	97.55	0.00	98.40	0.00	/workspace/coverage/cover_reg_top/96.xbar_same_source.4036765725
95.40	0.02	94.76	0.07	92.77	0.05	94.53	0.00			94.37	0.02	97.55	0.00	98.40	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3226735278
95.42	0.02	94.83	0.07	92.82	0.05	94.53	0.00			94.39	0.02	97.55	0.00	98.40	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3301773490
95.44	0.02	94.83	0.01	92.87	0.06	94.53	0.00			94.45	0.06	97.55	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3081111879
95.46	0.02	94.84	0.01	92.89	0.01	94.61	0.08			94.46	0.01	97.55	0.00	98.40	0.00	/workspace/coverage/default/0.chip_sw_usbdev_dpi.1226074485
95.48	0.02	94.84	0.00	92.95	0.07	94.61	0.00			94.47	0.02	97.55	0.00	98.43	0.02	/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2706712038
95.49	0.02	94.84	0.00	92.95	0.00	94.71	0.11			94.47	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1901983424
95.51	0.02	94.84	0.01	92.98	0.03	94.79	0.07			94.47	0.00	97.55	0.00	98.43	0.00	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2384263140
95.53	0.02	94.89	0.04	93.00	0.02	94.79	0.01			94.51	0.03	97.55	0.00	98.43	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1753187521
95.54	0.02	94.89	0.00	93.06	0.06	94.79	0.00			94.51	0.00	97.55	0.00	98.46	0.04	/workspace/coverage/cover_reg_top/61.xbar_stress_all.3345849296
95.56	0.02	94.89	0.00	93.09	0.03	94.85	0.06			94.51	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2718963566
95.57	0.01	94.89	0.00	93.09	0.00	94.85	0.00			94.51	0.00	97.55	0.00	98.54	0.08	/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.2609669087
95.59	0.01	94.91	0.02	93.15	0.06	94.85	0.00			94.51	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1293473035
95.60	0.01	94.91	0.00	93.22	0.07	94.85	0.00			94.51	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_20.554549210
95.61	0.01	94.91	0.00	93.23	0.01	94.91	0.06			94.51	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3501251696
95.62	0.01	94.91	0.00	93.23	0.01	94.91	0.00			94.51	0.00	97.55	0.00	98.60	0.06	/workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4219548991
95.63	0.01	94.91	0.00	93.23	0.00	94.97	0.06			94.51	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3852102951
95.64	0.01	94.91	0.00	93.23	0.00	95.03	0.06			94.51	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1454499053
95.65	0.01	94.91	0.00	93.29	0.05	95.03	0.00			94.51	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.2260992315
95.65	0.01	94.91	0.00	93.34	0.05	95.03	0.00			94.51	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1176434830
95.66	0.01	94.91	0.00	93.34	0.00	95.07	0.05			94.51	0.00	97.55	0.00	98.60	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2465653165
95.67	0.01	94.91	0.00	93.37	0.04	95.07	0.00			94.51	0.00	97.55	0.00	98.61	0.01	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.534213020
95.68	0.01	94.91	0.00	93.42	0.05	95.07	0.00			94.51	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.3762015772
95.69	0.01	94.91	0.00	93.42	0.00	95.12	0.04			94.51	0.00	97.55	0.00	98.61	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.2947778028
95.69	0.01	94.91	0.01	93.43	0.02	95.13	0.01			94.52	0.01	97.55	0.00	98.61	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3680184128
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95.72	0.01	94.92	0.00	93.50	0.00	95.15	0.00			94.53	0.00	97.55	0.00	98.65	0.04	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2944616726
95.72	0.01	94.92	0.00	93.50	0.00	95.15	0.00			94.53	0.00	97.55	0.00	98.68	0.04	/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2599375401
95.73	0.01	94.92	0.00	93.53	0.03	95.15	0.00			94.53	0.00	97.55	0.00	98.68	0.00	/workspace/coverage/cover_reg_top/14.chip_tl_errors.3093030752
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95.76	0.01	94.92	0.00	93.63	0.02	95.20	0.00			94.53	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3355989761
95.77	0.01	94.92	0.00	93.65	0.02	95.20	0.00			94.53	0.00	97.55	0.00	98.74	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.955101992
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95.77	0.01	94.92	0.00	93.66	0.00	95.22	0.02			94.53	0.00	97.55	0.00	98.75	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.3935430879
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95.79	0.01	94.92	0.00	93.71	0.00	95.28	0.01			94.53	0.00	97.55	0.00	98.78	0.01	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1080294829
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95.81	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	98.88	0.01	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3990886439
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95.82	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	98.93	0.01	/workspace/coverage/default/13.chip_sw_all_escalation_resets.2836843969
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95.83	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	98.97	0.01	/workspace/coverage/default/15.chip_sw_all_escalation_resets.1058672055
95.83	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	98.98	0.01	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828917455
95.83	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	98.99	0.01	/workspace/coverage/default/16.chip_sw_all_escalation_resets.4015314726
95.83	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.00	0.01	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3517710226
95.84	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.01	0.01	/workspace/coverage/default/18.chip_sw_all_escalation_resets.239502867
95.84	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.02	0.01	/workspace/coverage/default/19.chip_sw_all_escalation_resets.2539155727
95.84	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.04	0.01	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1491184202
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95.85	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.10	0.01	/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382047005
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95.86	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.14	0.01	/workspace/coverage/default/26.chip_sw_all_escalation_resets.658076717
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95.92	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.258621132
95.92	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/61.chip_sw_all_escalation_resets.1288763491
95.92	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3500385895
95.92	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.53	0.01	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1906067226
95.92	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.54	0.01	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699404524
95.93	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.55	0.01	/workspace/coverage/default/7.chip_sw_all_escalation_resets.1983016217
95.93	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.57	0.01	/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3313344054
95.93	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.58	0.01	/workspace/coverage/default/73.chip_sw_all_escalation_resets.2660994187
95.93	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.59	0.01	/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3642292067
95.93	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.60	0.01	/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1935947341
95.94	0.01	94.93	0.00	93.71	0.00	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.01	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657137297
95.94	0.01	94.93	0.00	93.72	0.01	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/27.chip_tl_errors.958154765
95.94	0.01	94.93	0.00	93.73	0.01	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_gpio.1596265314
95.94	0.01	94.93	0.00	93.74	0.01	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2046641095
95.94	0.01	94.93	0.00	93.75	0.01	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1252038379
95.94	0.01	94.93	0.00	93.76	0.01	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2224859267
95.95	0.01	94.93	0.00	93.77	0.01	95.29	0.00			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3171970849
95.95	0.01	94.93	0.01	93.77	0.00	95.29	0.01			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2938604204
95.95	0.01	94.93	0.00	93.77	0.00	95.30	0.01			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2103758477
95.95	0.01	94.93	0.00	93.77	0.00	95.31	0.01			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2951073979
95.95	0.01	94.94	0.01	93.77	0.00	95.31	0.01			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.550741887
95.95	0.01	94.94	0.01	93.77	0.00	95.32	0.01			94.53	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2542761602
95.96	0.01	94.94	0.00	93.77	0.00	95.32	0.00			94.54	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3774328063
95.96	0.01	94.94	0.00	93.77	0.00	95.32	0.00			94.55	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4059363166
95.96	0.01	94.94	0.00	93.78	0.01	95.32	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/13.chip_tl_errors.3099269673
95.96	0.01	94.94	0.00	93.78	0.01	95.32	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2604567717
95.96	0.01	94.94	0.00	93.78	0.00	95.33	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.1545327391
95.96	0.01	94.94	0.00	93.78	0.00	95.33	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.782235425
95.96	0.01	94.94	0.01	93.79	0.01	95.33	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.163627864
95.96	0.01	94.94	0.00	93.79	0.00	95.34	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2907280936
95.96	0.01	94.94	0.00	93.79	0.00	95.34	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1944088546
95.97	0.01	94.94	0.00	93.79	0.00	95.35	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.20268768
95.97	0.01	94.94	0.00	93.79	0.00	95.35	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1499470937
95.97	0.01	94.94	0.00	93.79	0.00	95.36	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.415934361
95.97	0.01	94.94	0.00	93.79	0.00	95.36	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.348094576
95.97	0.01	94.94	0.00	93.79	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/10.chip_tl_errors.4112069172
95.97	0.01	94.94	0.00	93.80	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.4017126016
95.97	0.01	94.94	0.00	93.80	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/64.xbar_error_random.3976226935
95.97	0.01	94.94	0.00	93.80	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.4190580276
95.97	0.01	94.94	0.00	93.81	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.1485820929
95.97	0.01	94.94	0.00	93.81	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/92.xbar_error_random.2571091280
95.97	0.01	94.94	0.00	93.81	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.520726696
95.97	0.01	94.94	0.00	93.82	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1836306545
95.97	0.01	94.94	0.00	93.82	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2386179642
95.97	0.01	94.94	0.00	93.82	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.300962258
95.97	0.01	94.94	0.00	93.83	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1092757251
95.97	0.01	94.94	0.00	93.83	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.827645951
95.98	0.01	94.94	0.00	93.83	0.01	95.36	0.00			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.720367553
95.98	0.01	94.94	0.00	93.83	0.00	95.36	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.823841988
95.98	0.01	94.94	0.00	93.83	0.00	95.37	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_aes_enc.471702525
95.98	0.01	94.94	0.00	93.83	0.00	95.37	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.516957575
95.98	0.01	94.94	0.00	93.83	0.00	95.37	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.5353360
95.98	0.01	94.94	0.00	93.83	0.00	95.37	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2514183003
95.98	0.01	94.94	0.00	93.83	0.00	95.37	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.389868583
95.98	0.01	94.94	0.00	93.83	0.00	95.38	0.01			94.55	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2051277323

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1646984451
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.2598253781
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1473243216
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3715005785
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.3731031737
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.546214277
/workspace/coverage/cover_reg_top/0.chip_tl_errors.580254611
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.203878283
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3673068866
/workspace/coverage/cover_reg_top/0.xbar_error_random.3733524248
/workspace/coverage/cover_reg_top/0.xbar_random.401441471
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3765341393
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3184031636
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2734945339
/workspace/coverage/cover_reg_top/0.xbar_same_source.1196616608
/workspace/coverage/cover_reg_top/0.xbar_smoke.1358161733
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.458211567
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.844269865
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3588862194
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2739622230
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3658439615
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2795964599
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.2901966754
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3221112515
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2236172462
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2735063795
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2553164524
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1573734826
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.3302138831
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.2560091458
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2766028376
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1875235549
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.707124857
/workspace/coverage/cover_reg_top/1.xbar_error_random.182352020
/workspace/coverage/cover_reg_top/1.xbar_random.288010138
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2275808889
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2774165963
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3264715562
/workspace/coverage/cover_reg_top/1.xbar_same_source.736562686
/workspace/coverage/cover_reg_top/1.xbar_smoke.193501096
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3477284158
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3338350387
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2045823947
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2421993970
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.12985334
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4036525245
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3161653406
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2013400639
/workspace/coverage/cover_reg_top/10.chip_csr_rw.2476956402
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4079224822
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3041123946
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3150924087
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1850790818
/workspace/coverage/cover_reg_top/10.xbar_error_random.3193750733
/workspace/coverage/cover_reg_top/10.xbar_random.2496803418
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.645773641
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3671651671
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1350812080
/workspace/coverage/cover_reg_top/10.xbar_same_source.450522444
/workspace/coverage/cover_reg_top/10.xbar_smoke.2865203438
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.569174337
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2722550974
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.4120239713
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2162190155
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.3557587557
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.2861297154
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1767062294
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3769213089
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3457028815
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.778347415
/workspace/coverage/cover_reg_top/11.chip_tl_errors.989251221
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.4098140421
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.4092252135
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2460493470
/workspace/coverage/cover_reg_top/11.xbar_error_random.3213742018
/workspace/coverage/cover_reg_top/11.xbar_random.1293268101
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4170385330
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.2856915340
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1786147301
/workspace/coverage/cover_reg_top/11.xbar_same_source.2165207986
/workspace/coverage/cover_reg_top/11.xbar_smoke.691816064
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2348925267
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3008098293
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3073931146
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2109767623
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.908455807
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.226205195
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2162956069
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3212246534
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3686038220
/workspace/coverage/cover_reg_top/12.chip_csr_rw.567818331
/workspace/coverage/cover_reg_top/12.chip_tl_errors.1115959978
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.732726515
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.747697621
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.186666100
/workspace/coverage/cover_reg_top/12.xbar_error_random.1423604309
/workspace/coverage/cover_reg_top/12.xbar_random.237788850
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.412758903
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.311473908
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2401937597
/workspace/coverage/cover_reg_top/12.xbar_same_source.557266756
/workspace/coverage/cover_reg_top/12.xbar_smoke.3156432978
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.3941789048
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.3385735402
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2596205978
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/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1849783986
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/workspace/coverage/default/60.chip_sw_all_escalation_resets.2483101804
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/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1998503463
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1416504128
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/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2172261003
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/workspace/coverage/default/70.chip_sw_all_escalation_resets.351179330
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/workspace/coverage/default/84.chip_sw_all_escalation_resets.3111351069
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/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.373598977
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749717650
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4193621119
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4088475513
/workspace/coverage/default/89.chip_sw_all_escalation_resets.2581156162
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4009362834
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2776819592
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2086014776
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.864602499
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3891270229
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4103132525
/workspace/coverage/default/92.chip_sw_all_escalation_resets.37325494
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3756705934
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1691918328
/workspace/coverage/default/95.chip_sw_all_escalation_resets.4194541135
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1405379253
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3964305140
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1448843769
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1752671910
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1489889998
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1147307075
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/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2195269982
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3350151470
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3001041271
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.161434762

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Total test records in report: 2937

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_spi_device_pass_through.4041536673			Jul 30 07:58:44 PM PDT 24	Jul 30 08:09:47 PM PDT 24	6076578053 ps
T2	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4164455345			Jul 30 07:52:47 PM PDT 24	Jul 30 07:59:07 PM PDT 24	4590467982 ps
T3	/workspace/coverage/default/55.chip_sw_all_escalation_resets.886708227			Jul 30 08:28:39 PM PDT 24	Jul 30 08:39:54 PM PDT 24	5877192428 ps
T6	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2268594481			Jul 30 08:10:54 PM PDT 24	Jul 30 08:21:11 PM PDT 24	9930157100 ps
T7	/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3084077861			Jul 30 08:09:40 PM PDT 24	Jul 30 08:12:07 PM PDT 24	2559858894 ps
T8	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3968767379			Jul 30 07:59:55 PM PDT 24	Jul 30 09:36:05 PM PDT 24	18093814881 ps
T4	/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1848970300			Jul 30 07:55:57 PM PDT 24	Jul 30 11:34:18 PM PDT 24	78032489220 ps
T80	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3056623399			Jul 30 07:52:17 PM PDT 24	Jul 30 08:00:02 PM PDT 24	5106751590 ps
T5	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.2636134848			Jul 30 08:00:12 PM PDT 24	Jul 30 08:33:27 PM PDT 24	8874857696 ps
T81	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1581266407			Jul 30 08:03:22 PM PDT 24	Jul 30 08:11:01 PM PDT 24	3506206880 ps
T43	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4072791286			Jul 30 07:53:26 PM PDT 24	Jul 30 09:02:17 PM PDT 24	44665380309 ps
T195	/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1747695963			Jul 30 08:10:11 PM PDT 24	Jul 30 08:19:10 PM PDT 24	4176754260 ps
T20	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.1378257633			Jul 30 07:58:46 PM PDT 24	Jul 30 08:05:56 PM PDT 24	3524327048 ps
T262	/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3658008823			Jul 30 08:29:55 PM PDT 24	Jul 30 08:35:16 PM PDT 24	3918178140 ps
T250	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2051277323			Jul 30 08:05:57 PM PDT 24	Jul 30 08:11:06 PM PDT 24	3131407688 ps
T37	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1132613468			Jul 30 08:00:58 PM PDT 24	Jul 30 08:06:58 PM PDT 24	3526718539 ps
T114	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2384263140			Jul 30 08:19:23 PM PDT 24	Jul 30 08:27:51 PM PDT 24	3684233925 ps
T56	/workspace/coverage/default/80.chip_sw_all_escalation_resets.715537131			Jul 30 08:29:39 PM PDT 24	Jul 30 08:36:58 PM PDT 24	5443549444 ps
T115	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.804392423			Jul 30 07:51:37 PM PDT 24	Jul 30 08:00:54 PM PDT 24	4129529500 ps
T274	/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.1930072106			Jul 30 08:14:47 PM PDT 24	Jul 30 08:23:03 PM PDT 24	4142918078 ps
T109	/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.396823728			Jul 30 08:18:33 PM PDT 24	Jul 30 08:22:28 PM PDT 24	3102987041 ps
T44	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1454499053			Jul 30 08:04:54 PM PDT 24	Jul 30 08:12:15 PM PDT 24	5515086770 ps
T119	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.546196908			Jul 30 08:02:19 PM PDT 24	Jul 30 08:32:14 PM PDT 24	7411858068 ps
T275	/workspace/coverage/default/0.chip_sw_hmac_smoketest.3840516225			Jul 30 07:55:46 PM PDT 24	Jul 30 08:01:46 PM PDT 24	3218514872 ps
T276	/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2503966773			Jul 30 07:52:39 PM PDT 24	Jul 30 07:57:30 PM PDT 24	2878958160 ps
T42	/workspace/coverage/default/1.rom_e2e_smoke.2229868932			Jul 30 08:15:47 PM PDT 24	Jul 30 09:27:32 PM PDT 24	15353373312 ps
T40	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1725985408			Jul 30 07:58:20 PM PDT 24	Jul 30 09:32:55 PM PDT 24	23154571230 ps
T331	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1295329209			Jul 30 08:26:07 PM PDT 24	Jul 30 08:32:41 PM PDT 24	4278266036 ps
T57	/workspace/coverage/default/4.chip_sw_data_integrity_escalation.2308463571			Jul 30 08:19:12 PM PDT 24	Jul 30 08:32:49 PM PDT 24	6192921434 ps
T125	/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2283778065			Jul 30 08:19:26 PM PDT 24	Jul 30 08:33:02 PM PDT 24	6219875688 ps
T142	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3990662841			Jul 30 08:08:15 PM PDT 24	Jul 30 08:18:10 PM PDT 24	4113884290 ps
T223	/workspace/coverage/default/46.chip_sw_all_escalation_resets.543464817			Jul 30 08:29:49 PM PDT 24	Jul 30 08:39:54 PM PDT 24	5283895808 ps
T75	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1886019301			Jul 30 08:00:12 PM PDT 24	Jul 30 08:06:02 PM PDT 24	3106022330 ps
T116	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3198309166			Jul 30 07:54:50 PM PDT 24	Jul 30 08:04:55 PM PDT 24	3740206616 ps
T298	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3668341893			Jul 30 08:28:46 PM PDT 24	Jul 30 08:35:01 PM PDT 24	4311258700 ps
T148	/workspace/coverage/default/1.rom_keymgr_functest.1391831794			Jul 30 08:06:54 PM PDT 24	Jul 30 08:17:56 PM PDT 24	5071717720 ps
T110	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1904369340			Jul 30 07:57:18 PM PDT 24	Jul 30 08:29:53 PM PDT 24	9460374363 ps
T149	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.4131939149			Jul 30 07:58:28 PM PDT 24	Jul 30 08:19:43 PM PDT 24	8925640842 ps
T155	/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.765777794			Jul 30 08:23:19 PM PDT 24	Jul 30 08:30:11 PM PDT 24	3451884192 ps
T15	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3680184128			Jul 30 07:51:35 PM PDT 24	Jul 30 08:01:01 PM PDT 24	4261524824 ps
T171	/workspace/coverage/default/0.chip_sw_flash_init.81945945			Jul 30 07:50:59 PM PDT 24	Jul 30 08:21:07 PM PDT 24	17278513688 ps
T324	/workspace/coverage/default/0.chip_plic_all_irqs_20.2459534467			Jul 30 07:56:03 PM PDT 24	Jul 30 08:11:37 PM PDT 24	5047847100 ps
T166	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.1095186207			Jul 30 08:00:02 PM PDT 24	Jul 30 09:25:08 PM PDT 24	15647732562 ps
T238	/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1364338637			Jul 30 08:12:55 PM PDT 24	Jul 30 08:24:20 PM PDT 24	8423384737 ps
T323	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.275739318			Jul 30 07:54:25 PM PDT 24	Jul 30 08:39:59 PM PDT 24	11280587302 ps
T227	/workspace/coverage/default/68.chip_sw_all_escalation_resets.1906067226			Jul 30 08:28:23 PM PDT 24	Jul 30 08:39:06 PM PDT 24	5875468500 ps
T225	/workspace/coverage/default/2.rom_e2e_self_hash.4040918753			Jul 30 08:24:30 PM PDT 24	Jul 30 10:01:06 PM PDT 24	26553591204 ps
T391	/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.4257081564			Jul 30 08:26:39 PM PDT 24	Jul 30 08:33:48 PM PDT 24	3084902040 ps
T121	/workspace/coverage/default/1.chip_sw_otbn_randomness.913949070			Jul 30 07:59:06 PM PDT 24	Jul 30 08:13:44 PM PDT 24	5514406732 ps
T768	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1849783986			Jul 30 08:22:05 PM PDT 24	Jul 30 08:28:51 PM PDT 24	3923323060 ps
T382	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3044277678			Jul 30 08:00:05 PM PDT 24	Jul 30 09:54:07 PM PDT 24	23887194928 ps
T184	/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.2658107210			Jul 30 08:01:43 PM PDT 24	Jul 30 08:07:35 PM PDT 24	4038074244 ps
T407	/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.4113743729			Jul 30 08:14:16 PM PDT 24	Jul 30 08:38:55 PM PDT 24	12068668860 ps
T402	/workspace/coverage/default/2.rom_e2e_asm_init_rma.3150522984			Jul 30 08:21:50 PM PDT 24	Jul 30 09:13:41 PM PDT 24	15316409461 ps
T224	/workspace/coverage/default/12.chip_sw_all_escalation_resets.4032831017			Jul 30 08:22:00 PM PDT 24	Jul 30 08:33:14 PM PDT 24	5851654354 ps
T113	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3754294049			Jul 30 07:52:49 PM PDT 24	Jul 30 09:25:56 PM PDT 24	47512767104 ps
T392	/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.258621132			Jul 30 08:26:47 PM PDT 24	Jul 30 08:34:08 PM PDT 24	4142816872 ps
T164	/workspace/coverage/default/2.rom_volatile_raw_unlock.2032491428			Jul 30 08:18:20 PM PDT 24	Jul 30 08:20:36 PM PDT 24	2887300627 ps
T931	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2913704280			Jul 30 08:06:33 PM PDT 24	Jul 30 08:12:47 PM PDT 24	3300112722 ps
T932	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3180411119			Jul 30 08:09:27 PM PDT 24	Jul 30 08:14:05 PM PDT 24	3160293085 ps
T339	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.118021537			Jul 30 07:56:54 PM PDT 24	Jul 30 08:00:23 PM PDT 24	2486660022 ps
T185	/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.222486329			Jul 30 08:13:23 PM PDT 24	Jul 30 08:23:07 PM PDT 24	3827367960 ps
T215	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2975374572			Jul 30 07:50:56 PM PDT 24	Jul 30 08:04:44 PM PDT 24	5401200512 ps
T455	/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1334917027			Jul 30 08:15:04 PM PDT 24	Jul 30 08:25:36 PM PDT 24	4528234500 ps
T143	/workspace/coverage/default/1.chip_sw_otbn_smoketest.2552960556			Jul 30 08:09:00 PM PDT 24	Jul 30 08:49:58 PM PDT 24	9977215220 ps
T356	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.307508861			Jul 30 08:02:57 PM PDT 24	Jul 30 08:07:56 PM PDT 24	2897487952 ps
T552	/workspace/coverage/default/54.chip_sw_all_escalation_resets.1080294829			Jul 30 08:26:42 PM PDT 24	Jul 30 08:37:30 PM PDT 24	6006486472 ps
T267	/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.131880263			Jul 30 08:13:14 PM PDT 24	Jul 30 09:32:00 PM PDT 24	18952630070 ps
T137	/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2343116302			Jul 30 07:54:20 PM PDT 24	Jul 30 07:58:36 PM PDT 24	3258928782 ps
T111	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.358577566			Jul 30 07:56:02 PM PDT 24	Jul 30 07:58:43 PM PDT 24	2319185625 ps
T408	/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.681207054			Jul 30 08:28:08 PM PDT 24	Jul 30 08:36:37 PM PDT 24	3568643552 ps
T388	/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.397372053			Jul 30 08:23:05 PM PDT 24	Jul 30 08:30:21 PM PDT 24	3306797840 ps
T158	/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.977381177			Jul 30 08:27:29 PM PDT 24	Jul 30 08:33:45 PM PDT 24	3435967780 ps
T381	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1427036353			Jul 30 08:04:52 PM PDT 24	Jul 30 08:27:24 PM PDT 24	7081648521 ps
T330	/workspace/coverage/default/2.chip_sw_hmac_enc.2167092037			Jul 30 08:13:01 PM PDT 24	Jul 30 08:17:02 PM PDT 24	2861327680 ps
T226	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.11432395			Jul 30 08:02:32 PM PDT 24	Jul 30 08:25:15 PM PDT 24	7381390470 ps
T14	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2920210079			Jul 30 07:51:59 PM PDT 24	Jul 30 07:57:24 PM PDT 24	4255693872 ps
T96	/workspace/coverage/default/1.chip_sw_flash_ctrl_access.2774538657			Jul 30 07:56:27 PM PDT 24	Jul 30 08:15:46 PM PDT 24	5848902248 ps
T25	/workspace/coverage/default/2.chip_sw_gpio.2805266917			Jul 30 08:08:58 PM PDT 24	Jul 30 08:18:43 PM PDT 24	4025861628 ps
T97	/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2670595231			Jul 30 08:01:10 PM PDT 24	Jul 30 08:05:33 PM PDT 24	2545318416 ps
T98	/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3235072652			Jul 30 07:55:35 PM PDT 24	Jul 30 07:58:32 PM PDT 24	3138639934 ps
T99	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1119911544			Jul 30 08:18:22 PM PDT 24	Jul 30 08:26:49 PM PDT 24	6788718898 ps
T100	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1604484226			Jul 30 08:18:31 PM PDT 24	Jul 30 08:26:09 PM PDT 24	3380940520 ps
T101	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.854287162			Jul 30 08:27:23 PM PDT 24	Jul 30 08:34:30 PM PDT 24	4607970488 ps
T61	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4090049395			Jul 30 08:16:14 PM PDT 24	Jul 30 08:23:24 PM PDT 24	4303171112 ps
T102	/workspace/coverage/default/4.chip_sw_all_escalation_resets.557301833			Jul 30 08:21:07 PM PDT 24	Jul 30 08:32:38 PM PDT 24	4981331384 ps
T437	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1022027576			Jul 30 07:54:14 PM PDT 24	Jul 30 08:07:44 PM PDT 24	5638602806 ps
T194	/workspace/coverage/default/1.chip_tap_straps_dev.3735853799			Jul 30 08:05:01 PM PDT 24	Jul 30 08:07:23 PM PDT 24	3280466174 ps
T438	/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1693954841			Jul 30 08:17:59 PM PDT 24	Jul 30 08:40:36 PM PDT 24	7485998905 ps
T439	/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1173258356			Jul 30 07:55:16 PM PDT 24	Jul 30 07:58:50 PM PDT 24	3007722320 ps
T138	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2480540985			Jul 30 08:10:28 PM PDT 24	Jul 30 08:19:00 PM PDT 24	8829105296 ps
T62	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.3904972104			Jul 30 08:04:55 PM PDT 24	Jul 30 08:13:04 PM PDT 24	5215413603 ps
T440	/workspace/coverage/default/2.chip_sw_example_flash.1595472474			Jul 30 08:07:31 PM PDT 24	Jul 30 08:11:32 PM PDT 24	3007395710 ps
T365	/workspace/coverage/default/7.chip_sw_all_escalation_resets.1983016217			Jul 30 08:21:15 PM PDT 24	Jul 30 08:32:17 PM PDT 24	6151838440 ps
T54	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3301773490			Jul 30 08:07:19 PM PDT 24	Jul 30 08:14:06 PM PDT 24	5353443984 ps
T411	/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3431718636			Jul 30 08:27:46 PM PDT 24	Jul 30 08:36:30 PM PDT 24	3876583736 ps
T412	/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.284311165			Jul 30 08:23:35 PM PDT 24	Jul 30 08:31:22 PM PDT 24	4073111100 ps
T177	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.399594954			Jul 30 08:03:08 PM PDT 24	Jul 30 08:17:35 PM PDT 24	7188102668 ps
T357	/workspace/coverage/default/49.chip_sw_all_escalation_resets.2833548108			Jul 30 08:26:16 PM PDT 24	Jul 30 08:35:31 PM PDT 24	4391709380 ps
T208	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.334725693			Jul 30 07:53:57 PM PDT 24	Jul 30 07:57:54 PM PDT 24	3294880346 ps
T334	/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2870070722			Jul 30 08:20:56 PM PDT 24	Jul 30 08:57:37 PM PDT 24	13434850668 ps
T403	/workspace/coverage/default/0.rom_e2e_asm_init_rma.1856084765			Jul 30 08:01:32 PM PDT 24	Jul 30 09:14:44 PM PDT 24	14989918596 ps
T350	/workspace/coverage/default/2.chip_sival_flash_info_access.128651196			Jul 30 08:07:45 PM PDT 24	Jul 30 08:13:13 PM PDT 24	3581018446 ps
T364	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.600499222			Jul 30 07:53:30 PM PDT 24	Jul 30 08:02:47 PM PDT 24	3933268292 ps
T933	/workspace/coverage/default/1.chip_sw_hmac_oneshot.981275999			Jul 30 08:02:56 PM PDT 24	Jul 30 08:06:57 PM PDT 24	2796162642 ps
T263	/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2016204832			Jul 30 07:51:42 PM PDT 24	Jul 30 08:12:20 PM PDT 24	12927232815 ps
T393	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2274591693			Jul 30 08:00:17 PM PDT 24	Jul 30 09:24:43 PM PDT 24	18515644616 ps
T104	/workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3501251696			Jul 30 07:56:44 PM PDT 24	Jul 30 08:31:48 PM PDT 24	15444252268 ps
T443	/workspace/coverage/default/48.chip_sw_all_escalation_resets.3279563272			Jul 30 08:27:10 PM PDT 24	Jul 30 08:40:50 PM PDT 24	6561780838 ps
T105	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1450746203			Jul 30 08:10:42 PM PDT 24	Jul 30 08:23:17 PM PDT 24	20034262120 ps
T447	/workspace/coverage/default/0.chip_sw_aes_enc.471702525			Jul 30 07:52:01 PM PDT 24	Jul 30 07:56:12 PM PDT 24	3216715320 ps
T448	/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2143864304			Jul 30 08:20:45 PM PDT 24	Jul 30 10:00:20 PM PDT 24	27103611620 ps
T325	/workspace/coverage/default/43.chip_sw_all_escalation_resets.3943764080			Jul 30 08:26:55 PM PDT 24	Jul 30 08:36:43 PM PDT 24	6034040600 ps
T277	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1697575008			Jul 30 07:52:23 PM PDT 24	Jul 30 07:59:29 PM PDT 24	3357693377 ps
T351	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.4284830246			Jul 30 08:09:26 PM PDT 24	Jul 30 08:19:46 PM PDT 24	4370321826 ps
T449	/workspace/coverage/default/1.chip_sw_hmac_smoketest.2588347721			Jul 30 08:06:49 PM PDT 24	Jul 30 08:13:23 PM PDT 24	3447004520 ps
T450	/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1290720732			Jul 30 08:06:54 PM PDT 24	Jul 30 08:14:22 PM PDT 24	3271160024 ps
T209	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3973158750			Jul 30 08:01:35 PM PDT 24	Jul 30 08:06:24 PM PDT 24	2909263046 ps
T752	/workspace/coverage/default/1.chip_sw_aes_entropy.2285699995			Jul 30 08:02:57 PM PDT 24	Jul 30 08:07:44 PM PDT 24	2983040328 ps
T790	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3500385895			Jul 30 08:30:28 PM PDT 24	Jul 30 08:39:52 PM PDT 24	6538233768 ps
T108	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2549778766			Jul 30 07:54:18 PM PDT 24	Jul 30 08:15:10 PM PDT 24	8535696226 ps
T26	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3399543797			Jul 30 07:55:57 PM PDT 24	Jul 30 08:00:44 PM PDT 24	3880537688 ps
T268	/workspace/coverage/default/25.chip_sw_all_escalation_resets.2938604204			Jul 30 08:26:21 PM PDT 24	Jul 30 08:35:50 PM PDT 24	5625018490 ps
T934	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4206152865			Jul 30 08:16:11 PM PDT 24	Jul 30 08:27:11 PM PDT 24	4736882410 ps
T172	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3189413241			Jul 30 08:10:12 PM PDT 24	Jul 30 08:16:00 PM PDT 24	5018590910 ps
T217	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3142429718			Jul 30 07:59:21 PM PDT 24	Jul 30 08:13:20 PM PDT 24	5050975752 ps
T63	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1151670528			Jul 30 07:56:45 PM PDT 24	Jul 30 08:05:55 PM PDT 24	4834736496 ps
T139	/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1564252615			Jul 30 07:59:12 PM PDT 24	Jul 30 08:05:59 PM PDT 24	6959955662 ps
T218	/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2948993665			Jul 30 07:53:29 PM PDT 24	Jul 30 08:08:09 PM PDT 24	8912415484 ps
T264	/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.4085433788			Jul 30 07:56:51 PM PDT 24	Jul 30 08:03:30 PM PDT 24	3386123048 ps
T174	/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.230120552			Jul 30 07:52:10 PM PDT 24	Jul 30 07:56:19 PM PDT 24	2985925135 ps
T717	/workspace/coverage/default/0.chip_sw_aes_masking_off.3317773640			Jul 30 07:54:12 PM PDT 24	Jul 30 07:58:53 PM PDT 24	3180968090 ps
T935	/workspace/coverage/default/0.chip_sw_csrng_kat_test.3235574868			Jul 30 07:55:43 PM PDT 24	Jul 30 08:00:17 PM PDT 24	2633102122 ps
T321	/workspace/coverage/default/59.chip_sw_all_escalation_resets.2357695599			Jul 30 08:26:33 PM PDT 24	Jul 30 08:37:53 PM PDT 24	4906841128 ps
T936	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.429724177			Jul 30 08:03:36 PM PDT 24	Jul 30 08:14:39 PM PDT 24	4851978008 ps
T21	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2009944538			Jul 30 08:01:18 PM PDT 24	Jul 30 08:21:04 PM PDT 24	22226111318 ps
T16	/workspace/coverage/default/0.chip_sw_usbdev_pullup.2634432331			Jul 30 07:53:51 PM PDT 24	Jul 30 07:57:20 PM PDT 24	2845467360 ps
T117	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.383926996			Jul 30 08:04:45 PM PDT 24	Jul 30 08:14:35 PM PDT 24	5185669846 ps
T231	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1900932300			Jul 30 07:57:35 PM PDT 24	Jul 30 08:23:18 PM PDT 24	8335557960 ps
T937	/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3297378590			Jul 30 07:51:07 PM PDT 24	Jul 30 07:55:42 PM PDT 24	2915457928 ps
T228	/workspace/coverage/default/24.chip_sw_all_escalation_resets.1705388100			Jul 30 08:25:15 PM PDT 24	Jul 30 08:35:58 PM PDT 24	5016964768 ps
T938	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3074279699			Jul 30 07:54:36 PM PDT 24	Jul 30 08:13:55 PM PDT 24	5739671806 ps
T232	/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2316140497			Jul 30 08:13:22 PM PDT 24	Jul 30 08:44:28 PM PDT 24	8029951470 ps
T456	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3429356770			Jul 30 08:04:21 PM PDT 24	Jul 30 08:08:34 PM PDT 24	3220270280 ps
T326	/workspace/coverage/default/1.chip_plic_all_irqs_20.554549210			Jul 30 08:04:20 PM PDT 24	Jul 30 08:18:16 PM PDT 24	4770923208 ps
T383	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.2743420990			Jul 30 07:57:11 PM PDT 24	Jul 30 09:17:11 PM PDT 24	15541921860 ps
T939	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1499579536			Jul 30 08:09:34 PM PDT 24	Jul 30 08:24:13 PM PDT 24	4253546520 ps
T41	/workspace/coverage/default/1.rom_e2e_shutdown_output.1377251798			Jul 30 08:10:56 PM PDT 24	Jul 30 09:16:45 PM PDT 24	29216605495 ps
T780	/workspace/coverage/default/69.chip_sw_all_escalation_resets.3828567499			Jul 30 08:28:01 PM PDT 24	Jul 30 08:39:54 PM PDT 24	4799797198 ps
T366	/workspace/coverage/default/86.chip_sw_all_escalation_resets.3156438580			Jul 30 08:31:31 PM PDT 24	Jul 30 08:41:31 PM PDT 24	5428093182 ps
T338	/workspace/coverage/default/2.chip_sw_otbn_randomness.312525076			Jul 30 08:11:22 PM PDT 24	Jul 30 08:29:48 PM PDT 24	5498755798 ps
T216	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.923532978			Jul 30 08:20:49 PM PDT 24	Jul 30 08:30:37 PM PDT 24	4628561544 ps
T457	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3022660575			Jul 30 08:13:37 PM PDT 24	Jul 30 08:19:05 PM PDT 24	3754629960 ps
T940	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3797529154			Jul 30 08:12:28 PM PDT 24	Jul 30 09:22:03 PM PDT 24	14199582270 ps
T368	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3320860457			Jul 30 08:10:53 PM PDT 24	Jul 30 08:37:41 PM PDT 24	9549368604 ps
T820	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1090568294			Jul 30 08:26:53 PM PDT 24	Jul 30 08:35:15 PM PDT 24	4270724964 ps
T327	/workspace/coverage/default/1.chip_plic_all_irqs_0.3460365095			Jul 30 08:05:56 PM PDT 24	Jul 30 08:23:52 PM PDT 24	6386814250 ps
T458	/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.789218526			Jul 30 07:52:50 PM PDT 24	Jul 30 07:55:54 PM PDT 24	2210018664 ps
T222	/workspace/coverage/default/1.chip_tap_straps_prod.1770664607			Jul 30 08:05:53 PM PDT 24	Jul 30 08:08:51 PM PDT 24	2737390234 ps
T229	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.403949104			Jul 30 08:01:39 PM PDT 24	Jul 30 08:09:34 PM PDT 24	5334162936 ps
T219	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1089400871			Jul 30 07:58:27 PM PDT 24	Jul 30 08:11:34 PM PDT 24	4777771912 ps
T941	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.403359371			Jul 30 08:07:26 PM PDT 24	Jul 30 08:11:20 PM PDT 24	2704425735 ps
T942	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.2780331757			Jul 30 08:19:43 PM PDT 24	Jul 30 09:32:41 PM PDT 24	21438777060 ps
T943	/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1399618470			Jul 30 08:23:24 PM PDT 24	Jul 30 08:25:52 PM PDT 24	2938671966 ps
T826	/workspace/coverage/default/22.chip_sw_all_escalation_resets.215366085			Jul 30 08:22:29 PM PDT 24	Jul 30 08:32:54 PM PDT 24	4923312632 ps
T766	/workspace/coverage/default/2.chip_sw_all_escalation_resets.1491184202			Jul 30 08:09:00 PM PDT 24	Jul 30 08:21:32 PM PDT 24	4561026830 ps
T944	/workspace/coverage/default/1.chip_sw_aes_enc.473590707			Jul 30 08:01:50 PM PDT 24	Jul 30 08:07:21 PM PDT 24	3566804226 ps
T718	/workspace/coverage/default/2.chip_sw_aes_masking_off.1613318218			Jul 30 08:12:05 PM PDT 24	Jul 30 08:19:34 PM PDT 24	2560859179 ps
T206	/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1861191271			Jul 30 08:10:10 PM PDT 24	Jul 31 12:00:36 AM PDT 24	79194503184 ps
T220	/workspace/coverage/default/4.chip_sw_uart_tx_rx.725155162			Jul 30 08:20:38 PM PDT 24	Jul 30 08:30:38 PM PDT 24	4170461878 ps
T175	/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.285564694			Jul 30 08:09:33 PM PDT 24	Jul 30 08:27:01 PM PDT 24	11174043022 ps
T186	/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.3220696871			Jul 30 07:51:50 PM PDT 24	Jul 30 07:58:56 PM PDT 24	3572211466 ps
T945	/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.56835320			Jul 30 08:19:29 PM PDT 24	Jul 30 08:24:58 PM PDT 24	3139033812 ps
T764	/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4272435802			Jul 30 08:24:53 PM PDT 24	Jul 30 08:31:35 PM PDT 24	4083302120 ps
T183	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3327943765			Jul 30 07:55:24 PM PDT 24	Jul 30 09:30:16 PM PDT 24	44031866495 ps
T157	/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2122991931			Jul 30 08:10:38 PM PDT 24	Jul 30 08:42:40 PM PDT 24	11716262102 ps
T946	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3636014679			Jul 30 07:51:13 PM PDT 24	Jul 30 08:07:10 PM PDT 24	8649289836 ps
T854	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.919093902			Jul 30 08:24:12 PM PDT 24	Jul 30 08:31:58 PM PDT 24	4515799878 ps
T947	/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1017352409			Jul 30 08:22:48 PM PDT 24	Jul 30 08:46:38 PM PDT 24	8311439656 ps
T221	/workspace/coverage/default/2.chip_sw_uart_tx_rx.2128586361			Jul 30 08:08:22 PM PDT 24	Jul 30 08:19:21 PM PDT 24	4894051868 ps
T754	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3517710226			Jul 30 08:22:04 PM PDT 24	Jul 30 08:28:40 PM PDT 24	4027968060 ps
T948	/workspace/coverage/default/0.rom_keymgr_functest.424699806			Jul 30 07:55:32 PM PDT 24	Jul 30 08:05:41 PM PDT 24	5503655432 ps
T165	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3827595605			Jul 30 07:53:17 PM PDT 24	Jul 30 09:46:22 PM PDT 24	50977110084 ps
T173	/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.335656254			Jul 30 08:10:06 PM PDT 24	Jul 30 08:28:31 PM PDT 24	10242583760 ps
T213	/workspace/coverage/default/76.chip_sw_all_escalation_resets.2155140510			Jul 30 08:29:58 PM PDT 24	Jul 30 08:38:23 PM PDT 24	4979388462 ps
T949	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4265943525			Jul 30 07:56:02 PM PDT 24	Jul 30 08:25:25 PM PDT 24	16326024841 ps
T444	/workspace/coverage/default/20.chip_sw_all_escalation_resets.3382655008			Jul 30 08:23:00 PM PDT 24	Jul 30 08:33:42 PM PDT 24	4479213106 ps
T409	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3264242940			Jul 30 08:24:56 PM PDT 24	Jul 30 08:39:36 PM PDT 24	5910280876 ps
T230	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3074950577			Jul 30 07:54:13 PM PDT 24	Jul 30 09:05:16 PM PDT 24	13175741584 ps
T150	/workspace/coverage/default/0.chip_plic_all_irqs_10.2664933268			Jul 30 07:53:20 PM PDT 24	Jul 30 08:02:14 PM PDT 24	3466792330 ps
T757	/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1972149571			Jul 30 08:24:55 PM PDT 24	Jul 30 08:32:15 PM PDT 24	4062105744 ps
T17	/workspace/coverage/default/0.chip_sw_usbdev_config_host.1304229515			Jul 30 07:52:29 PM PDT 24	Jul 30 08:29:02 PM PDT 24	7382914100 ps
T950	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.99084158			Jul 30 07:58:52 PM PDT 24	Jul 30 08:30:47 PM PDT 24	22338689560 ps
T260	/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1709423297			Jul 30 07:58:32 PM PDT 24	Jul 30 08:02:20 PM PDT 24	3335058746 ps
T233	/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3189439267			Jul 30 08:12:40 PM PDT 24	Jul 30 08:35:55 PM PDT 24	7272753524 ps
T951	/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1388560148			Jul 30 08:16:09 PM PDT 24	Jul 30 08:36:58 PM PDT 24	5586755098 ps
T952	/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2172261003			Jul 30 08:21:33 PM PDT 24	Jul 30 08:41:24 PM PDT 24	13953775828 ps
T341	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1945091179			Jul 30 08:19:45 PM PDT 24	Jul 30 08:30:04 PM PDT 24	4180420680 ps
T953	/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3248659686			Jul 30 08:08:18 PM PDT 24	Jul 30 08:19:02 PM PDT 24	4646778808 ps
T179	/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.296340042			Jul 30 08:04:09 PM PDT 24	Jul 30 08:08:18 PM PDT 24	2884036484 ps
T312	/workspace/coverage/default/1.chip_sw_csrng_kat_test.4125834949			Jul 30 08:02:29 PM PDT 24	Jul 30 08:07:28 PM PDT 24	2889491594 ps
T313	/workspace/coverage/default/0.chip_sw_kmac_app_rom.2938251204			Jul 30 07:55:44 PM PDT 24	Jul 30 07:59:17 PM PDT 24	2935242200 ps
T314	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3778454935			Jul 30 07:59:57 PM PDT 24	Jul 30 09:07:12 PM PDT 24	15405044600 ps
T112	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2718963566			Jul 30 07:52:59 PM PDT 24	Jul 30 08:06:22 PM PDT 24	5339575510 ps
T315	/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2776819592			Jul 30 08:22:50 PM PDT 24	Jul 30 09:41:29 PM PDT 24	19560979540 ps
T234	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.71281134			Jul 30 08:13:33 PM PDT 24	Jul 30 09:02:13 PM PDT 24	13406596312 ps
T316	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.3756743896			Jul 30 07:54:04 PM PDT 24	Jul 30 08:03:23 PM PDT 24	5675038358 ps
T153	/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1413988488			Jul 30 08:01:07 PM PDT 24	Jul 30 11:33:04 PM PDT 24	255753946254 ps
T317	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.5077844			Jul 30 08:10:06 PM PDT 24	Jul 30 08:19:34 PM PDT 24	4680810216 ps
T358	/workspace/coverage/default/8.chip_sw_all_escalation_resets.3496737140			Jul 30 08:21:51 PM PDT 24	Jul 30 08:31:29 PM PDT 24	4823140262 ps
T144	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1037830782			Jul 30 07:51:49 PM PDT 24	Jul 30 09:00:14 PM PDT 24	17172863608 ps
T954	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3355300007			Jul 30 08:15:36 PM PDT 24	Jul 30 08:19:08 PM PDT 24	2912947910 ps
T9	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2967405698			Jul 30 07:59:32 PM PDT 24	Jul 30 08:04:58 PM PDT 24	3361408059 ps
T795	/workspace/coverage/default/0.chip_sw_flash_crash_alert.3740264081			Jul 30 07:56:24 PM PDT 24	Jul 30 08:09:24 PM PDT 24	4947072296 ps
T322	/workspace/coverage/default/78.chip_sw_all_escalation_resets.624394908			Jul 30 08:28:37 PM PDT 24	Jul 30 08:41:18 PM PDT 24	5924110438 ps
T64	/workspace/coverage/default/3.chip_tap_straps_rma.1892345443			Jul 30 08:18:23 PM PDT 24	Jul 30 08:24:45 PM PDT 24	4675955363 ps
T955	/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2721083895			Jul 30 08:20:21 PM PDT 24	Jul 30 08:31:20 PM PDT 24	4549302664 ps
T956	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.4146105866			Jul 30 08:22:07 PM PDT 24	Jul 30 08:38:27 PM PDT 24	9220019280 ps
T957	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.917850533			Jul 30 08:01:39 PM PDT 24	Jul 30 08:23:37 PM PDT 24	7801958296 ps
T779	/workspace/coverage/default/17.chip_sw_all_escalation_resets.2140233882			Jul 30 08:22:50 PM PDT 24	Jul 30 08:32:19 PM PDT 24	4471831400 ps
T958	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2545435883			Jul 30 07:53:21 PM PDT 24	Jul 30 08:11:50 PM PDT 24	7506645969 ps
T240	/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1461662811			Jul 30 08:04:42 PM PDT 24	Jul 30 08:39:04 PM PDT 24	25497708170 ps
T120	/workspace/coverage/default/2.chip_sw_entropy_src_csrng.1043000549			Jul 30 08:14:59 PM PDT 24	Jul 30 08:35:39 PM PDT 24	5622075718 ps
T278	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2246466234			Jul 30 08:10:30 PM PDT 24	Jul 30 08:12:30 PM PDT 24	2797450497 ps
T959	/workspace/coverage/default/1.chip_sw_edn_auto_mode.2465653165			Jul 30 08:01:25 PM PDT 24	Jul 30 08:31:29 PM PDT 24	6322303722 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.4078863039			Jul 30 08:15:55 PM PDT 24	Jul 30 08:42:35 PM PDT 24	24399798018 ps
T425	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.415934361			Jul 30 07:51:02 PM PDT 24	Jul 30 07:59:59 PM PDT 24	8376421612 ps
T347	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1492707129			Jul 30 08:16:35 PM PDT 24	Jul 30 08:30:02 PM PDT 24	4807654076 ps
T106	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4215560664			Jul 30 08:07:55 PM PDT 24	Jul 30 09:30:18 PM PDT 24	23655077896 ps
T426	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1748982024			Jul 30 07:53:20 PM PDT 24	Jul 30 08:03:35 PM PDT 24	5001407042 ps
T55	/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.482247357			Jul 30 08:16:16 PM PDT 24	Jul 30 08:23:47 PM PDT 24	7116053094 ps
T427	/workspace/coverage/default/1.rom_e2e_asm_init_dev.4070515667			Jul 30 08:16:20 PM PDT 24	Jul 30 09:22:23 PM PDT 24	15910213894 ps
T428	/workspace/coverage/default/35.chip_sw_all_escalation_resets.4206586422			Jul 30 08:24:56 PM PDT 24	Jul 30 08:33:53 PM PDT 24	5480959660 ps
T429	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2531696515			Jul 30 07:59:50 PM PDT 24	Jul 30 09:12:25 PM PDT 24	14377628665 ps
T430	/workspace/coverage/default/1.chip_sw_example_rom.1793495815			Jul 30 07:53:59 PM PDT 24	Jul 30 07:56:12 PM PDT 24	2275066478 ps
T145	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1122268028			Jul 30 07:52:05 PM PDT 24	Jul 30 08:53:18 PM PDT 24	18702334559 ps
T452	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.607845303			Jul 30 08:19:07 PM PDT 24	Jul 30 08:23:49 PM PDT 24	3547934168 ps
T73	/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.186782760			Jul 30 08:05:09 PM PDT 24	Jul 30 08:15:07 PM PDT 24	4893371320 ps
T178	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.188873179			Jul 30 07:54:29 PM PDT 24	Jul 30 08:05:14 PM PDT 24	3616031580 ps
T960	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3286702911			Jul 30 07:59:29 PM PDT 24	Jul 30 08:12:15 PM PDT 24	4146386404 ps
T214	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.831506757			Jul 30 08:12:20 PM PDT 24	Jul 30 08:44:57 PM PDT 24	8247845616 ps
T961	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.1009921226			Jul 30 07:58:43 PM PDT 24	Jul 30 08:06:23 PM PDT 24	9395866828 ps
T159	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2862408413			Jul 30 07:51:20 PM PDT 24	Jul 30 07:58:49 PM PDT 24	3100923776 ps
T962	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2808337015			Jul 30 08:14:54 PM PDT 24	Jul 30 08:57:57 PM PDT 24	26412473726 ps
T65	/workspace/coverage/default/2.chip_jtag_mem_access.1655285033			Jul 30 08:08:07 PM PDT 24	Jul 30 08:33:09 PM PDT 24	13977330492 ps
T69	/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1516596470			Jul 30 07:53:48 PM PDT 24	Jul 30 08:00:20 PM PDT 24	7710876256 ps
T361	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.761582440			Jul 30 07:51:02 PM PDT 24	Jul 30 07:55:21 PM PDT 24	3025886679 ps
T963	/workspace/coverage/default/1.rom_e2e_asm_init_rma.3499091495			Jul 30 08:12:02 PM PDT 24	Jul 30 09:22:24 PM PDT 24	15123954995 ps
T855	/workspace/coverage/default/70.chip_sw_all_escalation_resets.351179330			Jul 30 08:28:59 PM PDT 24	Jul 30 08:41:55 PM PDT 24	5062649608 ps
T782	/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1504094840			Jul 30 08:26:28 PM PDT 24	Jul 30 08:32:54 PM PDT 24	4197339528 ps