Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	149787	1			T70	18		T71	50		T72	42
values[2]	4874	1			T122	1		T254	1		T557	3
values[3]	2469	1			T555	1		T709	1		T888	32
values[4]	1908	1			T555	1		T888	23		T480	79
values[5]	1684	1			T555	1		T888	17		T480	58
values[6]	1484	1			T555	1		T888	7		T480	45
values[7]	1321	1			T555	1		T480	29		T871	2
values[8]	1060	1			T555	1		T480	9		T871	1
values[9]	896	1			T555	1		T480	10		T464	9
values[10]	774	1			T555	1		T480	1		T464	9
values[11]	816	1			T555	1		T464	5		T470	13
values[12]	747	1			T555	1		T464	6		T470	24
values[13]	805	1			T555	1		T464	9		T470	24
values[14]	758	1			T555	1		T464	10		T470	12
values[15]	669	1			T555	1		T464	16		T470	19
values[16]	656	1			T555	1		T464	3		T470	23
values[17]	603	1			T555	1		T464	5		T470	17
values[18]	585	1			T555	1		T464	4		T470	8
values[19]	586	1			T555	1		T464	10		T470	7
values[20]	501	1			T555	1		T464	24		T470	11
values[21]	440	1			T555	1		T464	40		T470	9
values[22]	378	1			T555	1		T464	49		T470	10
values[23]	299	1			T555	1		T464	21		T475	1
values[24]	233	1			T555	1		T464	8		T475	1
values[25]	214	1			T555	1		T464	13		T475	1
values[26]	208	1			T555	1		T464	6		T475	1
values[27]	225	1			T555	1		T464	5		T475	1
values[28]	199	1			T555	1		T475	1		T472	16
values[29]	205	1			T555	1		T475	1		T472	9
values[30]	198	1			T555	1		T475	1		T472	11
values[31]	176	1			T555	1		T475	1		T472	4
values[32]	157	1			T555	1		T475	1		T472	1
values[33]	145	1			T555	1		T475	1		T472	6
values[34]	138	1			T555	1		T475	1		T472	3
values[35]	142	1			T555	1		T475	1		T505	4
values[36]	132	1			T555	1		T475	1		T505	1
values[37]	102	1			T555	1		T475	1		T505	1
values[38]	91	1			T555	1		T475	1		T505	2
values[39]	85	1			T555	1		T475	1		T505	1
values[40]	90	1			T555	1		T475	1		T505	1
values[41]	103	1			T555	1		T475	1		T505	1
values[42]	124	1			T555	1		T475	1		T505	3
values[43]	101	1			T555	1		T475	1		T505	1
values[44]	103	1			T555	1		T475	1		T505	2
values[45]	90	1			T555	1		T475	1		T505	3
values[46]	85	1			T555	1		T475	1		T505	1
values[47]	89	1			T555	1		T475	1		T505	2
values[48]	62	1			T555	1		T475	1		T505	1
values[49]	70	1			T555	1		T475	1		T505	5
values[50]	83	1			T555	1		T475	1		T505	1
values[51]	64	1			T555	1		T475	1		T505	6
values[52]	70	1			T555	1		T475	1		T505	3
values[53]	65	1			T555	2		T475	1		T505	3
values[54]	82	1			T555	1		T475	1		T505	2
values[55]	59	1			T555	1		T475	1		T505	2
values[56]	58	1			T555	1		T475	1		T505	3
values[57]	60	1			T555	1		T475	1		T505	1
values[58]	57	1			T555	1		T475	1		T505	1
values[59]	67	1			T555	1		T475	1		T505	3
values[60]	63	1			T555	1		T475	1		T505	1
values[61]	64	1			T555	1		T475	2		T505	1
values[62]	60	1			T555	2		T475	1		T505	3
values[63]	54	1			T555	1		T475	1		T505	2
values[64]	53	1			T555	1		T475	1		T505	2
values[65]	69	1			T555	1		T475	1		T505	3
values[66]	51	1			T555	1		T475	1		T505	1
values[67]	61	1			T555	1		T475	1		T505	1
values[68]	54	1			T555	1		T475	1		T505	1
values[69]	57	1			T555	1		T475	1		T505	3
values[70]	58	1			T555	1		T475	1		T505	2
values[71]	60	1			T555	1		T475	1		T505	3
values[72]	72	1			T555	1		T475	1		T505	3
values[73]	70	1			T555	1		T475	1		T505	1
values[74]	68	1			T555	1		T475	1		T505	3
values[75]	55	1			T555	1		T475	1		T505	1
values[76]	62	1			T555	1		T475	1		T505	1
values[77]	75	1			T555	1		T475	1		T505	1
values[78]	67	1			T555	1		T475	1		T505	2
values[79]	68	1			T555	1		T475	1		T505	1
values[80]	64	1			T555	1		T475	1		T505	2
values[81]	69	1			T555	1		T475	1		T505	4
values[82]	70	1			T555	1		T475	1		T505	6
values[83]	84	1			T555	1		T475	1		T505	3
values[84]	82	1			T555	1		T475	1		T505	3
values[85]	64	1			T555	1		T475	1		T505	1
values[86]	87	1			T555	1		T475	1		T505	5
values[87]	62	1			T555	1		T475	1		T505	4
values[88]	64	1			T555	1		T475	1		T505	1
values[89]	65	1			T555	1		T475	1		T505	2
values[90]	76	1			T555	1		T475	1		T505	1
values[91]	74	1			T555	1		T475	1		T505	3
values[92]	82	1			T555	1		T475	1		T505	3
values[93]	83	1			T555	1		T475	1		T505	1
values[94]	87	1			T555	1		T475	1		T505	1
values[95]	97	1			T555	1		T475	1		T505	2
values[96]	86	1			T555	1		T475	1		T505	1
values[97]	91	1			T555	1		T475	1		T505	1
values[98]	85	1			T555	1		T475	1		T505	3
values[99]	99	1			T555	1		T475	1		T505	1
values[100]	92	1			T555	1		T475	1		T505	4
values[101]	91	1			T555	1		T475	1		T505	6
values[102]	84	1			T555	1		T475	1		T505	3
values[103]	83	1			T555	1		T475	1		T505	2
values[104]	85	1			T555	1		T475	1		T505	1
values[105]	72	1			T555	1		T475	1		T505	1
values[106]	73	1			T555	1		T475	1		T505	2
values[107]	76	1			T555	1		T475	1		T505	3
values[108]	89	1			T555	1		T475	1		T505	7
values[109]	74	1			T555	1		T475	1		T505	7
values[110]	100	1			T555	1		T475	1		T505	8
values[111]	113	1			T555	1		T475	1		T505	1
values[112]	84	1			T555	1		T475	1		T505	3
values[113]	77	1			T555	1		T475	1		T505	1
values[114]	86	1			T555	1		T475	1		T505	4
values[115]	106	1			T555	1		T475	1		T505	3
values[116]	91	1			T555	1		T475	1		T505	1
values[117]	120	1			T555	1		T475	1		T505	4
values[118]	116	1			T555	1		T475	1		T505	7
values[119]	93	1			T555	1		T475	3		T505	2
values[120]	107	1			T555	1		T475	1		T505	6
values[121]	118	1			T555	1		T475	4		T505	7
values[122]	124	1			T555	1		T475	2		T505	8
values[123]	126	1			T555	1		T475	1		T505	9
values[124]	229	1			T555	1		T475	2		T505	28
values[125]	404	1			T555	1		T475	2		T505	56
values[126]	744	1			T555	18		T475	15		T505	50
values[127]	2694	1			T555	119		T475	108		T505	37
values[128]	4953	1			T555	246		T475	289		T505	2