Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_timer_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	134995	1			T70	22		T71	43		T72	45
values[2]	9527	1			T71	1		T122	2		T557	1
values[3]	3918	1			T555	1		T479	181		T668	40
values[4]	2364	1			T555	2		T479	112		T668	19
values[5]	1610	1			T555	1		T479	73		T668	18
values[6]	1028	1			T555	1		T479	34		T668	6
values[7]	708	1			T555	1		T479	32		T517	13
values[8]	516	1			T555	1		T479	29		T517	6
values[9]	387	1			T555	1		T479	14		T517	8
values[10]	419	1			T555	1		T517	6		T874	1
values[11]	329	1			T555	1		T517	5		T874	1
values[12]	322	1			T555	1		T517	6		T874	1
values[13]	286	1			T555	1		T517	13		T874	1
values[14]	268	1			T555	1		T517	10		T874	1
values[15]	272	1			T555	1		T517	6		T874	1
values[16]	303	1			T555	1		T517	4		T874	1
values[17]	235	1			T555	1		T517	10		T874	1
values[18]	233	1			T555	1		T517	5		T874	1
values[19]	241	1			T555	1		T517	16		T874	1
values[20]	274	1			T555	1		T517	9		T874	1
values[21]	276	1			T555	1		T517	2		T874	1
values[22]	235	1			T555	1		T517	4		T874	1
values[23]	258	1			T555	1		T517	5		T874	1
values[24]	322	1			T555	1		T517	3		T874	1
values[25]	272	1			T555	1		T517	4		T874	1
values[26]	285	1			T555	1		T517	7		T874	1
values[27]	259	1			T555	1		T517	5		T874	1
values[28]	286	1			T555	1		T517	12		T874	1
values[29]	265	1			T555	1		T517	11		T874	1
values[30]	275	1			T555	1		T517	18		T874	1
values[31]	254	1			T555	1		T517	3		T874	1
values[32]	237	1			T555	1		T517	9		T874	1
values[33]	283	1			T555	1		T517	8		T874	1
values[34]	253	1			T555	1		T517	14		T874	1
values[35]	251	1			T555	1		T517	3		T874	1
values[36]	225	1			T555	1		T517	3		T874	1
values[37]	272	1			T555	1		T517	12		T874	1
values[38]	258	1			T555	1		T517	8		T874	1
values[39]	289	1			T555	1		T517	8		T874	1
values[40]	235	1			T555	1		T517	3		T874	1
values[41]	263	1			T555	1		T517	5		T874	1
values[42]	247	1			T555	1		T517	7		T874	1
values[43]	257	1			T555	1		T517	4		T874	1
values[44]	224	1			T555	1		T517	11		T874	1
values[45]	236	1			T555	1		T517	2		T874	1
values[46]	225	1			T555	1		T517	5		T874	1
values[47]	228	1			T555	1		T517	4		T874	1
values[48]	262	1			T555	1		T517	10		T874	1
values[49]	238	1			T555	1		T517	3		T874	1
values[50]	238	1			T555	1		T517	6		T874	1
values[51]	269	1			T555	1		T517	5		T874	1
values[52]	308	1			T555	1		T517	4		T874	1
values[53]	226	1			T555	1		T517	3		T874	1
values[54]	211	1			T555	1		T874	1		T496	5
values[55]	244	1			T555	1		T874	1		T496	10
values[56]	226	1			T555	1		T874	1		T496	5
values[57]	246	1			T555	1		T874	1		T496	17
values[58]	265	1			T555	1		T874	1		T496	13
values[59]	193	1			T555	1		T874	1		T496	16
values[60]	226	1			T555	1		T874	1		T496	5
values[61]	206	1			T555	2		T874	1		T496	3
values[62]	169	1			T555	1		T874	1		T496	5
values[63]	225	1			T555	1		T874	1		T496	14
values[64]	172	1			T555	1		T874	1		T496	4
values[65]	201	1			T555	1		T874	1		T496	4
values[66]	163	1			T555	1		T874	1		T496	8
values[67]	166	1			T555	1		T874	1		T496	5
values[68]	106	1			T555	1		T874	1		T496	5
values[69]	158	1			T555	1		T874	1		T496	6
values[70]	88	1			T555	1		T874	1		T496	4
values[71]	113	1			T555	1		T874	1		T496	4
values[72]	117	1			T555	1		T874	1		T496	4
values[73]	82	1			T555	1		T874	2		T543	6
values[74]	78	1			T555	1		T874	1		T543	7
values[75]	74	1			T555	1		T874	1		T543	8
values[76]	51	1			T555	1		T874	1		T543	3
values[77]	48	1			T555	1		T874	1		T469	1
values[78]	45	1			T555	2		T874	1		T469	1
values[79]	37	1			T555	1		T874	1		T469	1
values[80]	35	1			T555	3		T874	1		T469	1
values[81]	40	1			T555	3		T874	1		T469	1
values[82]	36	1			T555	1		T874	1		T469	1
values[83]	50	1			T555	3		T874	1		T469	1
values[84]	44	1			T555	1		T874	2		T469	1
values[85]	50	1			T555	2		T874	1		T469	2
values[86]	58	1			T555	2		T874	4		T469	2
values[87]	49	1			T555	2		T874	5		T469	9
values[88]	53	1			T555	1		T874	9		T469	3
values[89]	52	1			T555	1		T874	1		T469	4
values[90]	63	1			T555	2		T874	6		T469	2
values[91]	41	1			T555	2		T874	1		T469	3
values[92]	38	1			T555	1		T874	2		T469	1
values[93]	48	1			T555	3		T874	1		T469	1
values[94]	45	1			T555	4		T874	3		T469	1
values[95]	47	1			T555	2		T874	3		T469	5
values[96]	43	1			T555	3		T874	1		T469	1
values[97]	42	1			T555	1		T874	3		T469	7
values[98]	51	1			T555	2		T874	1		T469	4
values[99]	41	1			T555	1		T874	1		T469	4
values[100]	39	1			T555	3		T874	1		T469	1
values[101]	45	1			T555	5		T874	2		T469	1
values[102]	32	1			T555	1		T874	1		T469	2
values[103]	46	1			T555	1		T874	4		T469	5
values[104]	40	1			T555	2		T874	3		T469	1
values[105]	49	1			T555	2		T874	3		T469	2
values[106]	56	1			T555	1		T874	3		T469	1
values[107]	56	1			T555	2		T874	1		T469	4
values[108]	46	1			T555	2		T874	2		T469	1
values[109]	48	1			T555	4		T874	4		T469	1
values[110]	40	1			T555	3		T874	2		T469	2
values[111]	33	1			T555	1		T874	2		T469	2
values[112]	42	1			T555	4		T874	3		T469	1
values[113]	49	1			T555	1		T874	1		T469	3
values[114]	49	1			T555	1		T874	1		T469	1
values[115]	48	1			T555	3		T874	2		T469	1
values[116]	40	1			T555	1		T874	6		T469	2
values[117]	55	1			T555	1		T874	4		T469	1
values[118]	56	1			T555	6		T874	4		T469	1
values[119]	41	1			T555	2		T874	1		T469	1
values[120]	44	1			T555	2		T874	1		T469	2
values[121]	49	1			T555	1		T874	3		T469	1
values[122]	35	1			T555	1		T874	1		T469	4
values[123]	38	1			T555	1		T874	1		T469	2
values[124]	39	1			T555	1		T874	1		T469	2
values[125]	42	1			T555	1		T874	2		T469	1
values[126]	50	1			T555	1		T874	1		T469	3
values[127]	676	1			T555	30		T874	31		T469	35
values[128]	6557	1			T555	267		T874	329		T469	313