Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.spi_device_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	136635	1			T70	25		T71	47		T72	55
values[2]	10328	1			T71	1		T72	1		T122	7
values[3]	4171	1			T554	5		T555	1		T566	1
values[4]	2424	1			T554	14		T555	1		T566	1
values[5]	1571	1			T554	15		T555	1		T566	1
values[6]	1131	1			T554	9		T555	1		T566	1
values[7]	861	1			T554	5		T555	1		T566	1
values[8]	725	1			T554	10		T555	1		T566	1
values[9]	597	1			T554	11		T555	1		T566	1
values[10]	437	1			T554	5		T555	1		T566	1
values[11]	410	1			T554	8		T555	1		T566	1
values[12]	416	1			T554	6		T555	1		T566	1
values[13]	346	1			T554	6		T555	1		T566	1
values[14]	349	1			T554	12		T555	1		T566	1
values[15]	290	1			T554	9		T555	1		T566	1
values[16]	300	1			T554	2		T555	1		T566	1
values[17]	308	1			T554	5		T555	1		T566	1
values[18]	290	1			T554	9		T555	1		T566	1
values[19]	346	1			T554	19		T555	1		T566	1
values[20]	307	1			T554	7		T555	1		T566	1
values[21]	298	1			T554	12		T555	1		T566	1
values[22]	289	1			T554	13		T555	1		T566	1
values[23]	282	1			T554	3		T555	1		T566	1
values[24]	281	1			T554	2		T555	1		T566	1
values[25]	259	1			T554	5		T555	1		T566	1
values[26]	279	1			T554	9		T555	1		T566	1
values[27]	330	1			T554	3		T555	1		T566	1
values[28]	291	1			T554	10		T555	1		T566	1
values[29]	263	1			T554	18		T555	1		T566	1
values[30]	245	1			T554	22		T555	1		T566	1
values[31]	282	1			T554	3		T555	1		T566	1
values[32]	317	1			T554	5		T555	1		T566	1
values[33]	286	1			T554	6		T555	1		T566	1
values[34]	271	1			T554	3		T555	1		T566	1
values[35]	330	1			T554	6		T555	1		T566	1
values[36]	251	1			T554	4		T555	1		T566	1
values[37]	250	1			T554	7		T555	1		T566	1
values[38]	297	1			T554	14		T555	1		T566	1
values[39]	288	1			T554	13		T555	1		T566	1
values[40]	273	1			T554	12		T555	1		T566	1
values[41]	284	1			T554	14		T555	1		T566	1
values[42]	295	1			T554	7		T555	1		T566	1
values[43]	295	1			T554	16		T555	1		T566	1
values[44]	243	1			T554	4		T555	1		T566	1
values[45]	262	1			T554	2		T555	1		T566	1
values[46]	258	1			T554	6		T555	1		T566	1
values[47]	260	1			T554	4		T555	1		T566	1
values[48]	244	1			T554	4		T555	1		T566	1
values[49]	253	1			T554	8		T555	1		T566	1
values[50]	257	1			T554	2		T555	1		T566	1
values[51]	229	1			T554	3		T555	1		T566	1
values[52]	228	1			T554	5		T555	1		T566	1
values[53]	187	1			T554	4		T555	1		T566	1
values[54]	247	1			T554	23		T555	1		T566	1
values[55]	275	1			T554	13		T555	1		T566	1
values[56]	227	1			T554	22		T555	1		T566	1
values[57]	227	1			T554	8		T555	1		T566	1
values[58]	245	1			T554	3		T555	1		T566	1
values[59]	246	1			T554	8		T555	1		T566	1
values[60]	221	1			T554	10		T555	1		T566	1
values[61]	181	1			T554	4		T555	1		T566	1
values[62]	158	1			T554	3		T555	1		T566	1
values[63]	147	1			T554	8		T555	1		T566	1
values[64]	198	1			T554	5		T555	1		T566	1
values[65]	181	1			T554	3		T555	1		T566	1
values[66]	141	1			T554	5		T555	1		T566	1
values[67]	147	1			T554	4		T555	1		T566	1
values[68]	139	1			T554	7		T555	1		T566	1
values[69]	117	1			T555	1		T566	1		T464	5
values[70]	111	1			T555	1		T566	1		T464	4
values[71]	100	1			T555	1		T566	1		T464	3
values[72]	100	1			T555	1		T566	1		T464	3
values[73]	93	1			T555	1		T566	1		T464	5
values[74]	73	1			T555	2		T566	1		T464	4
values[75]	76	1			T555	1		T566	1		T464	5
values[76]	74	1			T555	1		T566	1		T464	3
values[77]	75	1			T555	1		T566	1		T464	4
values[78]	100	1			T555	1		T566	1		T464	5
values[79]	91	1			T555	1		T566	1		T464	5
values[80]	77	1			T555	1		T566	1		T464	5
values[81]	69	1			T555	1		T566	1		T464	2
values[82]	68	1			T555	1		T566	1		T464	5
values[83]	76	1			T555	1		T566	1		T464	5
values[84]	74	1			T555	1		T566	1		T464	3
values[85]	75	1			T555	1		T566	1		T464	5
values[86]	67	1			T555	1		T566	1		T464	6
values[87]	79	1			T555	1		T566	1		T464	3
values[88]	71	1			T555	1		T566	1		T464	6
values[89]	91	1			T555	1		T566	1		T464	11
values[90]	96	1			T555	1		T566	1		T464	5
values[91]	84	1			T555	1		T566	1		T464	8
values[92]	76	1			T555	1		T566	2		T464	7
values[93]	97	1			T555	1		T566	2		T464	4
values[94]	88	1			T555	1		T566	1		T464	8
values[95]	81	1			T555	1		T566	2		T464	8
values[96]	118	1			T555	1		T566	8		T464	16
values[97]	101	1			T555	1		T566	2		T464	9
values[98]	88	1			T555	1		T566	1		T464	5
values[99]	128	1			T555	1		T566	3		T464	6
values[100]	111	1			T555	1		T566	3		T464	13
values[101]	99	1			T555	1		T566	1		T464	5
values[102]	96	1			T555	1		T566	1		T464	2
values[103]	107	1			T555	2		T566	2		T464	13
values[104]	72	1			T555	1		T566	1		T464	6
values[105]	95	1			T555	1		T566	5		T464	11
values[106]	95	1			T555	1		T566	1		T464	4
values[107]	103	1			T555	1		T566	1		T464	9
values[108]	99	1			T555	1		T566	3		T464	6
values[109]	99	1			T555	1		T566	4		T464	13
values[110]	124	1			T555	1		T566	2		T464	20
values[111]	122	1			T555	1		T566	4		T464	12
values[112]	101	1			T555	1		T566	2		T464	10
values[113]	93	1			T555	1		T566	2		T464	8
values[114]	92	1			T555	1		T566	2		T464	10
values[115]	93	1			T555	1		T566	2		T464	7
values[116]	81	1			T555	1		T566	1		T464	8
values[117]	88	1			T555	1		T566	1		T464	13
values[118]	88	1			T555	1		T566	8		T464	7
values[119]	67	1			T555	1		T566	4		T464	6
values[120]	75	1			T555	1		T566	3		T464	4
values[121]	81	1			T555	1		T566	3		T464	9
values[122]	86	1			T555	1		T566	2		T464	6
values[123]	93	1			T555	1		T566	2		T464	15
values[124]	84	1			T555	1		T566	2		T464	18
values[125]	114	1			T555	2		T566	2		T464	33
values[126]	170	1			T555	2		T566	2		T464	60
values[127]	1108	1			T555	42		T566	28		T464	60
values[128]	9387	1			T555	345		T566	238		T464	19