Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	153291	1			T70	26		T71	51		T72	57
values[2]	4829	1			T122	2		T254	1		T255	1
values[3]	2607	1			T555	1		T566	1		T558	26
values[4]	2182	1			T555	1		T566	1		T558	17
values[5]	1861	1			T555	1		T566	1		T558	13
values[6]	1437	1			T555	1		T566	1		T558	11
values[7]	1210	1			T555	1		T566	1		T558	12
values[8]	936	1			T555	1		T566	1		T558	5
values[9]	742	1			T555	1		T566	1		T558	3
values[10]	755	1			T555	1		T566	1		T480	9
values[11]	573	1			T555	1		T566	1		T869	11
values[12]	478	1			T555	1		T566	1		T871	18
values[13]	488	1			T555	1		T566	1		T871	27
values[14]	435	1			T555	1		T566	1		T871	31
values[15]	367	1			T555	1		T566	1		T871	18
values[16]	330	1			T555	1		T566	1		T871	9
values[17]	298	1			T555	1		T566	1		T871	5
values[18]	350	1			T555	1		T566	1		T871	9
values[19]	298	1			T555	1		T566	1		T871	11
values[20]	238	1			T555	1		T566	1		T871	9
values[21]	219	1			T555	1		T566	1		T871	7
values[22]	229	1			T555	1		T566	1		T871	10
values[23]	191	1			T555	1		T566	1		T871	6
values[24]	135	1			T555	1		T566	1		T871	5
values[25]	147	1			T555	1		T566	1		T871	7
values[26]	164	1			T555	1		T566	1		T871	8
values[27]	147	1			T555	1		T566	1		T871	4
values[28]	133	1			T555	1		T566	1		T871	5
values[29]	140	1			T555	1		T566	1		T871	9
values[30]	146	1			T555	1		T566	1		T871	7
values[31]	161	1			T555	1		T566	1		T871	4
values[32]	148	1			T555	1		T566	1		T871	7
values[33]	119	1			T555	1		T566	1		T871	10
values[34]	118	1			T555	1		T566	1		T871	14
values[35]	103	1			T555	1		T566	1		T871	8
values[36]	105	1			T555	1		T566	1		T871	5
values[37]	84	1			T555	1		T566	1		T871	7
values[38]	69	1			T555	1		T566	1		T871	5
values[39]	78	1			T555	1		T566	1		T871	12
values[40]	82	1			T555	1		T566	1		T871	6
values[41]	103	1			T555	1		T566	1		T871	11
values[42]	99	1			T555	1		T566	1		T871	7
values[43]	114	1			T555	1		T566	1		T871	8
values[44]	111	1			T555	1		T566	1		T871	14
values[45]	98	1			T555	1		T566	1		T871	11
values[46]	87	1			T555	1		T566	1		T871	14
values[47]	89	1			T555	1		T566	1		T871	9
values[48]	88	1			T555	1		T566	1		T871	12
values[49]	87	1			T555	1		T566	1		T871	8
values[50]	71	1			T555	1		T566	1		T871	7
values[51]	93	1			T555	1		T566	1		T871	7
values[52]	91	1			T555	1		T566	1		T871	9
values[53]	76	1			T555	1		T566	1		T871	6
values[54]	72	1			T555	1		T566	1		T871	10
values[55]	73	1			T555	1		T566	1		T871	10
values[56]	66	1			T555	1		T566	1		T871	4
values[57]	66	1			T555	1		T566	1		T871	7
values[58]	80	1			T555	1		T566	1		T871	11
values[59]	80	1			T555	1		T566	1		T871	12
values[60]	76	1			T555	1		T566	1		T871	9
values[61]	75	1			T555	1		T566	1		T871	10
values[62]	80	1			T555	1		T566	1		T871	12
values[63]	69	1			T555	1		T566	1		T871	7
values[64]	69	1			T555	1		T566	1		T871	7
values[65]	72	1			T555	1		T566	1		T871	9
values[66]	71	1			T555	1		T566	1		T871	12
values[67]	58	1			T555	1		T566	1		T871	5
values[68]	80	1			T555	1		T566	3		T871	8
values[69]	82	1			T555	1		T566	5		T871	10
values[70]	78	1			T555	1		T566	1		T871	8
values[71]	75	1			T555	1		T566	2		T871	9
values[72]	85	1			T555	1		T566	7		T871	7
values[73]	80	1			T555	1		T566	2		T871	10
values[74]	80	1			T555	1		T566	8		T871	11
values[75]	108	1			T555	1		T566	25		T871	5
values[76]	91	1			T555	1		T566	6		T871	7
values[77]	78	1			T555	1		T566	3		T871	8
values[78]	88	1			T555	1		T566	7		T871	5
values[79]	93	1			T555	1		T566	4		T871	5
values[80]	95	1			T555	1		T566	3		T871	11
values[81]	110	1			T555	1		T566	1		T871	15
values[82]	76	1			T555	1		T566	1		T871	7
values[83]	81	1			T555	1		T566	5		T871	7
values[84]	89	1			T555	1		T566	1		T871	11
values[85]	100	1			T555	1		T566	7		T871	8
values[86]	103	1			T555	1		T566	3		T871	7
values[87]	104	1			T555	1		T566	5		T871	15
values[88]	108	1			T555	1		T566	1		T871	10
values[89]	104	1			T555	2		T566	1		T871	10
values[90]	95	1			T555	3		T566	2		T871	9
values[91]	116	1			T555	6		T566	1		T871	11
values[92]	106	1			T555	2		T566	1		T871	9
values[93]	97	1			T555	3		T566	2		T871	7
values[94]	113	1			T555	8		T566	3		T871	8
values[95]	113	1			T555	1		T566	1		T871	12
values[96]	103	1			T555	3		T566	2		T871	7
values[97]	116	1			T555	3		T566	2		T871	14
values[98]	120	1			T555	1		T566	2		T871	24
values[99]	110	1			T555	2		T566	1		T871	9
values[100]	126	1			T555	5		T566	2		T871	9
values[101]	118	1			T555	2		T566	3		T871	10
values[102]	105	1			T555	1		T566	2		T871	14
values[103]	115	1			T555	2		T566	3		T871	6
values[104]	117	1			T555	4		T566	1		T871	7
values[105]	119	1			T555	2		T566	2		T871	8
values[106]	135	1			T555	2		T566	4		T871	13
values[107]	147	1			T555	2		T566	1		T871	10
values[108]	148	1			T555	2		T566	2		T871	10
values[109]	137	1			T555	3		T566	2		T871	15
values[110]	117	1			T555	2		T566	1		T871	14
values[111]	121	1			T555	1		T566	3		T871	13
values[112]	114	1			T555	4		T566	1		T871	11
values[113]	162	1			T555	1		T566	1		T871	23
values[114]	151	1			T555	3		T566	2		T871	16
values[115]	146	1			T555	5		T566	1		T871	24
values[116]	153	1			T555	2		T566	1		T871	27
values[117]	144	1			T555	3		T566	4		T871	11
values[118]	129	1			T555	1		T566	4		T871	11
values[119]	138	1			T555	1		T566	1		T871	16
values[120]	103	1			T555	1		T566	2		T871	11
values[121]	136	1			T555	4		T566	2		T871	14
values[122]	140	1			T555	3		T566	2		T871	12
values[123]	188	1			T555	1		T566	4		T871	26
values[124]	237	1			T555	2		T566	2		T871	30
values[125]	463	1			T555	2		T566	1		T871	53
values[126]	984	1			T555	27		T566	15		T871	79
values[127]	3818	1			T555	112		T566	83		T871	36
values[128]	6641	1			T555	212		T566	152		T871	3