Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	135525	1			T70	25		T71	45		T72	50
values[2]	9775	1			T122	3		T256	72		T255	3
values[3]	3902	1			T256	2		T554	8		T566	1
values[4]	2348	1			T554	7		T566	1		T558	109
values[5]	1504	1			T554	8		T566	1		T558	116
values[6]	996	1			T554	5		T566	1		T558	70
values[7]	731	1			T554	4		T566	1		T558	33
values[8]	600	1			T554	8		T566	1		T558	11
values[9]	558	1			T554	9		T566	1		T558	2
values[10]	460	1			T554	6		T566	1		T558	11
values[11]	358	1			T554	4		T566	1		T558	5
values[12]	375	1			T554	9		T566	1		T502	3
values[13]	368	1			T554	10		T566	1		T502	4
values[14]	362	1			T554	10		T566	1		T502	4
values[15]	334	1			T554	14		T566	1		T502	4
values[16]	416	1			T554	8		T566	1		T502	15
values[17]	360	1			T554	10		T566	1		T502	9
values[18]	348	1			T554	9		T566	1		T502	6
values[19]	271	1			T554	7		T566	1		T502	6
values[20]	345	1			T554	4		T566	1		T502	3
values[21]	308	1			T554	7		T566	1		T502	4
values[22]	314	1			T554	18		T566	1		T502	6
values[23]	276	1			T554	10		T566	1		T502	15
values[24]	312	1			T554	4		T566	1		T502	17
values[25]	295	1			T554	4		T566	1		T502	10
values[26]	304	1			T554	5		T566	1		T502	2
values[27]	282	1			T554	4		T566	1		T502	3
values[28]	291	1			T554	21		T566	1		T502	11
values[29]	288	1			T554	16		T566	1		T502	7
values[30]	246	1			T554	2		T566	1		T502	3
values[31]	266	1			T554	4		T566	1		T502	7
values[32]	273	1			T554	4		T566	1		T502	8
values[33]	251	1			T554	3		T566	1		T502	16
values[34]	261	1			T554	8		T566	1		T502	6
values[35]	322	1			T554	5		T566	2		T502	4
values[36]	272	1			T554	6		T566	1		T502	5
values[37]	251	1			T554	10		T566	1		T502	4
values[38]	247	1			T554	11		T566	1		T502	3
values[39]	242	1			T554	8		T566	1		T502	6
values[40]	290	1			T554	2		T566	1		T502	11
values[41]	294	1			T554	3		T566	1		T502	5
values[42]	294	1			T554	8		T566	1		T502	29
values[43]	280	1			T554	16		T566	1		T502	6
values[44]	283	1			T554	7		T566	1		T502	7
values[45]	292	1			T554	16		T566	1		T502	12
values[46]	232	1			T554	1		T566	1		T502	3
values[47]	224	1			T566	1		T502	8		T876	7
values[48]	273	1			T566	1		T502	11		T876	2
values[49]	254	1			T566	1		T502	8		T876	10
values[50]	259	1			T566	1		T502	3		T876	13
values[51]	233	1			T566	1		T502	13		T876	7
values[52]	214	1			T566	1		T502	11		T876	3
values[53]	213	1			T566	1		T502	7		T876	3
values[54]	224	1			T566	2		T502	2		T876	3
values[55]	231	1			T566	2		T876	3		T605	1
values[56]	253	1			T566	1		T876	2		T605	2
values[57]	201	1			T566	1		T876	7		T605	1
values[58]	192	1			T566	1		T876	8		T605	2
values[59]	193	1			T566	1		T876	13		T605	1
values[60]	210	1			T566	1		T876	14		T605	2
values[61]	173	1			T566	1		T876	6		T605	1
values[62]	154	1			T566	1		T876	6		T605	1
values[63]	158	1			T566	1		T876	6		T605	2
values[64]	168	1			T566	1		T876	7		T605	3
values[65]	153	1			T566	1		T876	3		T605	4
values[66]	161	1			T566	1		T876	8		T605	7
values[67]	140	1			T566	1		T876	6		T605	2
values[68]	148	1			T566	1		T876	5		T605	4
values[69]	140	1			T566	1		T876	3		T605	1
values[70]	126	1			T566	1		T876	7		T605	3
values[71]	110	1			T566	1		T876	6		T605	3
values[72]	106	1			T566	1		T876	5		T605	2
values[73]	134	1			T566	1		T876	6		T605	4
values[74]	142	1			T566	1		T876	6		T605	5
values[75]	139	1			T566	1		T876	2		T605	3
values[76]	126	1			T566	1		T876	7		T605	3
values[77]	114	1			T566	1		T876	12		T605	4
values[78]	100	1			T566	1		T876	7		T605	2
values[79]	108	1			T566	1		T876	7		T605	1
values[80]	104	1			T566	1		T876	4		T605	3
values[81]	126	1			T566	1		T876	6		T605	2
values[82]	120	1			T566	1		T876	5		T605	2
values[83]	135	1			T566	1		T876	4		T605	9
values[84]	116	1			T566	1		T876	11		T605	12
values[85]	109	1			T566	1		T876	6		T605	10
values[86]	124	1			T566	1		T876	7		T605	6
values[87]	113	1			T566	1		T876	8		T605	7
values[88]	105	1			T566	1		T876	7		T605	4
values[89]	92	1			T566	1		T876	5		T605	5
values[90]	145	1			T566	1		T876	3		T605	3
values[91]	126	1			T566	1		T876	10		T605	2
values[92]	152	1			T566	1		T876	19		T605	1
values[93]	120	1			T566	2		T876	4		T605	2
values[94]	110	1			T566	1		T876	6		T605	2
values[95]	94	1			T566	1		T876	2		T605	1
values[96]	112	1			T566	1		T876	4		T605	3
values[97]	126	1			T566	1		T876	9		T605	2
values[98]	106	1			T566	1		T876	5		T605	1
values[99]	109	1			T566	1		T876	7		T605	3
values[100]	122	1			T566	1		T876	5		T605	3
values[101]	114	1			T566	1		T876	6		T605	2
values[102]	109	1			T566	1		T876	7		T605	1
values[103]	103	1			T566	1		T876	7		T605	3
values[104]	109	1			T566	1		T876	3		T605	1
values[105]	118	1			T566	1		T876	12		T605	1
values[106]	112	1			T566	1		T876	8		T605	5
values[107]	110	1			T566	1		T876	8		T605	1
values[108]	93	1			T566	1		T876	5		T605	2
values[109]	115	1			T566	2		T876	17		T605	2
values[110]	106	1			T566	4		T876	8		T605	3
values[111]	116	1			T566	2		T876	7		T605	3
values[112]	95	1			T566	1		T876	2		T605	1
values[113]	93	1			T566	1		T876	1		T469	1
values[114]	104	1			T566	1		T876	3		T469	1
values[115]	93	1			T566	3		T876	1		T469	1
values[116]	99	1			T566	2		T876	3		T469	1
values[117]	97	1			T566	2		T876	2		T469	1
values[118]	87	1			T566	2		T876	4		T469	1
values[119]	76	1			T566	1		T876	1		T469	1
values[120]	105	1			T566	5		T876	2		T469	1
values[121]	121	1			T566	3		T876	9		T469	1
values[122]	97	1			T566	2		T876	5		T469	1
values[123]	80	1			T566	3		T876	11		T469	1
values[124]	81	1			T566	3		T876	9		T469	1
values[125]	89	1			T566	1		T876	6		T469	1
values[126]	157	1			T566	2		T876	30		T469	5
values[127]	1175	1			T566	31		T876	75		T469	23
values[128]	10061	1			T566	279		T876	34		T469	287