Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart0_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139452	1			T70	20		T71	48		T72	54
values[2]	10583	1			T71	2		T122	3		T462	1
values[3]	4154	1			T554	6		T566	1		T677	34
values[4]	2351	1			T554	11		T566	1		T677	25
values[5]	1488	1			T554	8		T566	1		T677	5
values[6]	1021	1			T554	8		T566	1		T677	5
values[7]	710	1			T554	8		T566	1		T677	5
values[8]	546	1			T554	5		T566	1		T677	1
values[9]	439	1			T554	5		T566	1		T517	4
values[10]	334	1			T554	9		T566	1		T517	4
values[11]	389	1			T554	5		T566	1		T517	6
values[12]	355	1			T554	13		T566	1		T517	6
values[13]	379	1			T554	4		T566	1		T517	16
values[14]	339	1			T554	15		T566	1		T517	5
values[15]	317	1			T554	8		T566	1		T517	6
values[16]	322	1			T554	3		T566	1		T517	12
values[17]	294	1			T554	2		T566	1		T517	7
values[18]	298	1			T554	3		T566	1		T517	3
values[19]	260	1			T554	6		T566	1		T517	4
values[20]	269	1			T554	15		T566	1		T517	5
values[21]	284	1			T554	13		T566	1		T517	4
values[22]	309	1			T554	2		T566	1		T517	8
values[23]	300	1			T554	5		T566	1		T517	13
values[24]	302	1			T554	4		T566	1		T517	7
values[25]	271	1			T554	6		T566	1		T517	8
values[26]	300	1			T554	22		T566	1		T517	6
values[27]	255	1			T554	6		T566	1		T517	5
values[28]	286	1			T554	8		T566	1		T517	6
values[29]	293	1			T554	7		T566	1		T517	7
values[30]	290	1			T554	9		T566	1		T517	8
values[31]	258	1			T554	6		T566	1		T517	20
values[32]	255	1			T554	6		T566	1		T517	9
values[33]	299	1			T554	7		T566	1		T517	6
values[34]	262	1			T554	8		T566	1		T517	4
values[35]	237	1			T554	7		T566	1		T517	5
values[36]	262	1			T554	12		T566	1		T517	5
values[37]	280	1			T554	3		T566	1		T517	4
values[38]	252	1			T554	4		T566	2		T517	4
values[39]	243	1			T554	5		T566	1		T517	5
values[40]	260	1			T554	7		T566	1		T517	3
values[41]	229	1			T554	5		T566	1		T517	4
values[42]	225	1			T554	11		T566	1		T517	9
values[43]	260	1			T554	3		T566	1		T517	5
values[44]	207	1			T554	7		T566	1		T517	16
values[45]	271	1			T554	4		T566	1		T517	26
values[46]	257	1			T554	11		T566	1		T517	14
values[47]	220	1			T554	5		T566	1		T517	1
values[48]	219	1			T554	7		T566	1		T870	1
values[49]	216	1			T554	10		T566	1		T870	1
values[50]	196	1			T554	6		T566	1		T870	1
values[51]	243	1			T554	10		T566	1		T870	1
values[52]	195	1			T566	1		T870	1		T496	3
values[53]	188	1			T566	1		T870	1		T496	7
values[54]	240	1			T566	1		T870	1		T496	22
values[55]	176	1			T566	1		T870	1		T496	3
values[56]	179	1			T566	1		T870	1		T496	5
values[57]	181	1			T566	1		T870	1		T496	11
values[58]	161	1			T566	1		T870	1		T496	11
values[59]	192	1			T566	1		T870	1		T496	7
values[60]	160	1			T566	1		T870	1		T496	6
values[61]	162	1			T566	1		T870	1		T537	2
values[62]	114	1			T566	1		T870	1		T537	2
values[63]	142	1			T566	1		T870	1		T537	5
values[64]	171	1			T566	1		T870	1		T537	3
values[65]	158	1			T566	1		T870	1		T537	5
values[66]	133	1			T566	1		T870	1		T537	4
values[67]	118	1			T566	1		T870	1		T537	1
values[68]	114	1			T566	1		T870	1		T537	4
values[69]	116	1			T566	1		T870	1		T537	5
values[70]	92	1			T566	1		T870	1		T537	5
values[71]	94	1			T566	1		T870	1		T537	2
values[72]	113	1			T566	1		T870	1		T537	3
values[73]	71	1			T566	1		T870	1		T537	2
values[74]	68	1			T566	1		T870	1		T537	5
values[75]	53	1			T566	1		T870	1		T537	4
values[76]	72	1			T566	1		T870	1		T537	6
values[77]	72	1			T566	1		T870	1		T537	2
values[78]	63	1			T566	1		T870	1		T537	4
values[79]	63	1			T566	1		T870	1		T537	2
values[80]	64	1			T566	1		T870	1		T537	2
values[81]	45	1			T566	1		T870	1		T537	1
values[82]	71	1			T566	1		T870	1		T537	1
values[83]	72	1			T566	1		T870	1		T537	2
values[84]	53	1			T566	1		T870	1		T537	1
values[85]	59	1			T566	1		T870	1		T537	1
values[86]	65	1			T566	1		T870	1		T537	6
values[87]	65	1			T566	1		T870	1		T537	5
values[88]	61	1			T566	1		T870	1		T537	1
values[89]	58	1			T566	1		T870	1		T537	3
values[90]	55	1			T566	1		T870	1		T537	1
values[91]	68	1			T566	1		T870	1		T537	1
values[92]	70	1			T566	1		T870	1		T537	3
values[93]	76	1			T566	1		T870	1		T537	1
values[94]	63	1			T566	1		T870	1		T537	2
values[95]	78	1			T566	2		T870	1		T537	5
values[96]	78	1			T566	2		T870	2		T537	2
values[97]	84	1			T566	3		T870	5		T537	7
values[98]	96	1			T566	6		T870	4		T537	2
values[99]	81	1			T566	3		T870	1		T537	4
values[100]	103	1			T566	2		T870	5		T537	6
values[101]	89	1			T566	4		T870	1		T537	3
values[102]	86	1			T566	7		T870	2		T537	10
values[103]	68	1			T566	1		T870	1		T537	6
values[104]	95	1			T566	6		T870	1		T537	8
values[105]	78	1			T566	3		T870	1		T537	5
values[106]	75	1			T566	2		T870	2		T537	14
values[107]	83	1			T566	1		T870	2		T537	20
values[108]	83	1			T566	3		T870	2		T537	5
values[109]	74	1			T566	2		T870	2		T537	6
values[110]	68	1			T566	2		T870	2		T537	5
values[111]	69	1			T566	2		T870	2		T537	5
values[112]	77	1			T566	1		T870	1		T537	7
values[113]	71	1			T566	1		T870	4		T537	5
values[114]	64	1			T566	1		T870	6		T537	10
values[115]	53	1			T566	4		T870	1		T537	3
values[116]	65	1			T566	1		T870	3		T537	3
values[117]	74	1			T566	2		T870	4		T537	6
values[118]	76	1			T566	2		T870	1		T537	8
values[119]	68	1			T566	4		T870	1		T537	2
values[120]	78	1			T566	2		T870	2		T537	8
values[121]	68	1			T566	1		T870	1		T537	5
values[122]	59	1			T566	2		T870	1		T537	5
values[123]	58	1			T566	2		T870	1		T537	2
values[124]	60	1			T566	1		T870	3		T537	3
values[125]	62	1			T566	2		T870	2		T537	2
values[126]	107	1			T566	7		T870	2		T537	19
values[127]	759	1			T566	31		T870	30		T537	33
values[128]	6560	1			T566	268		T870	302		T537	7