Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.uart1_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	131478	1			T70	12		T71	46		T72	54
values[2]	8827	1			T122	7		T462	1		T255	1
values[3]	3743	1			T566	1		T677	7		T480	1
values[4]	2269	1			T566	1		T677	7		T480	3
values[5]	1433	1			T566	1		T677	11		T480	1
values[6]	895	1			T566	1		T677	3		T480	2
values[7]	757	1			T566	1		T677	14		T480	1
values[8]	561	1			T566	1		T677	4		T480	2
values[9]	492	1			T566	1		T677	8		T480	3
values[10]	419	1			T566	1		T677	5		T480	1
values[11]	365	1			T566	1		T677	12		T480	4
values[12]	311	1			T566	1		T677	7		T480	1
values[13]	285	1			T566	1		T677	6		T480	2
values[14]	303	1			T566	1		T677	5		T480	2
values[15]	256	1			T566	1		T677	13		T480	2
values[16]	265	1			T566	1		T677	14		T480	3
values[17]	241	1			T566	1		T677	3		T480	3
values[18]	279	1			T566	1		T677	5		T480	2
values[19]	240	1			T566	1		T677	5		T480	2
values[20]	227	1			T566	1		T677	8		T480	1
values[21]	237	1			T566	1		T677	11		T480	3
values[22]	210	1			T566	1		T677	9		T480	2
values[23]	228	1			T566	1		T677	9		T480	1
values[24]	249	1			T566	1		T677	4		T480	2
values[25]	271	1			T566	1		T677	2		T480	4
values[26]	238	1			T566	1		T677	7		T480	5
values[27]	241	1			T566	1		T677	4		T480	11
values[28]	229	1			T566	1		T677	7		T480	11
values[29]	209	1			T566	1		T677	3		T480	2
values[30]	240	1			T566	1		T677	13		T480	2
values[31]	205	1			T566	1		T677	5		T480	1
values[32]	196	1			T566	1		T677	3		T480	3
values[33]	171	1			T566	1		T677	5		T480	3
values[34]	236	1			T566	1		T677	14		T480	5
values[35]	238	1			T566	1		T677	29		T480	3
values[36]	191	1			T566	1		T677	10		T480	2
values[37]	246	1			T566	1		T677	8		T480	8
values[38]	250	1			T566	1		T677	9		T480	5
values[39]	257	1			T566	1		T677	6		T480	13
values[40]	247	1			T566	1		T677	7		T480	2
values[41]	276	1			T566	1		T677	6		T480	3
values[42]	240	1			T566	1		T677	4		T480	3
values[43]	226	1			T566	1		T677	8		T480	5
values[44]	243	1			T566	1		T677	8		T480	3
values[45]	213	1			T566	1		T677	4		T480	1
values[46]	246	1			T566	1		T677	3		T480	2
values[47]	207	1			T566	1		T677	3		T480	4
values[48]	211	1			T566	1		T677	4		T480	4
values[49]	250	1			T566	1		T677	5		T480	6
values[50]	245	1			T566	1		T677	5		T480	3
values[51]	222	1			T566	1		T677	8		T480	5
values[52]	197	1			T566	1		T677	6		T480	13
values[53]	184	1			T566	1		T677	5		T480	4
values[54]	245	1			T566	1		T677	5		T480	3
values[55]	208	1			T566	1		T677	2		T480	3
values[56]	204	1			T566	1		T677	11		T480	2
values[57]	203	1			T566	1		T677	16		T480	1
values[58]	217	1			T566	1		T677	7		T480	1
values[59]	186	1			T566	1		T677	5		T480	2
values[60]	183	1			T566	1		T677	5		T480	1
values[61]	163	1			T566	1		T677	4		T480	1
values[62]	183	1			T566	1		T677	3		T480	2
values[63]	203	1			T566	1		T677	8		T480	1
values[64]	206	1			T566	1		T480	4		T883	1
values[65]	151	1			T566	1		T480	3		T883	1
values[66]	132	1			T566	1		T480	1		T883	1
values[67]	127	1			T566	1		T480	7		T883	3
values[68]	152	1			T566	1		T480	11		T883	7
values[69]	106	1			T566	1		T480	6		T883	7
values[70]	104	1			T566	1		T480	4		T883	4
values[71]	153	1			T566	1		T480	2		T883	4
values[72]	126	1			T566	1		T480	1		T883	1
values[73]	146	1			T566	1		T480	1		T883	3
values[74]	118	1			T566	1		T480	4		T883	2
values[75]	113	1			T566	1		T480	3		T883	1
values[76]	132	1			T566	1		T480	2		T883	2
values[77]	111	1			T566	1		T480	1		T883	5
values[78]	126	1			T566	1		T480	3		T883	9
values[79]	113	1			T566	1		T480	7		T883	4
values[80]	126	1			T566	1		T480	13		T883	4
values[81]	129	1			T566	1		T480	7		T883	11
values[82]	110	1			T566	1		T480	9		T883	12
values[83]	101	1			T566	1		T480	8		T883	13
values[84]	97	1			T566	2		T480	3		T883	8
values[85]	116	1			T566	2		T480	10		T883	13
values[86]	105	1			T566	1		T480	11		T883	9
values[87]	99	1			T566	5		T480	2		T883	5
values[88]	108	1			T566	4		T480	3		T883	5
values[89]	106	1			T566	3		T480	4		T883	4
values[90]	101	1			T566	3		T480	5		T883	5
values[91]	109	1			T566	2		T480	9		T883	4
values[92]	101	1			T566	2		T480	7		T883	2
values[93]	115	1			T566	1		T480	8		T883	1
values[94]	103	1			T566	1		T480	8		T883	2
values[95]	102	1			T566	2		T480	9		T883	2
values[96]	104	1			T566	2		T480	8		T883	7
values[97]	98	1			T566	1		T480	3		T883	3
values[98]	90	1			T566	1		T480	3		T883	4
values[99]	101	1			T566	7		T480	3		T883	6
values[100]	91	1			T566	3		T480	7		T883	3
values[101]	77	1			T566	3		T480	2		T883	6
values[102]	89	1			T566	3		T480	7		T883	9
values[103]	77	1			T566	1		T480	4		T883	6
values[104]	97	1			T566	3		T480	8		T883	2
values[105]	96	1			T566	11		T480	8		T883	6
values[106]	98	1			T566	2		T480	22		T883	4
values[107]	106	1			T566	5		T480	19		T883	3
values[108]	86	1			T566	3		T480	2		T883	2
values[109]	97	1			T566	5		T883	2		T467	10
values[110]	75	1			T566	1		T883	4		T467	6
values[111]	95	1			T566	6		T883	2		T467	8
values[112]	71	1			T566	3		T883	3		T467	4
values[113]	78	1			T566	6		T883	6		T467	7
values[114]	71	1			T566	1		T883	8		T467	3
values[115]	69	1			T566	2		T883	4		T467	3
values[116]	82	1			T566	1		T883	7		T467	7
values[117]	79	1			T566	2		T883	6		T467	2
values[118]	105	1			T566	1		T883	3		T467	2
values[119]	93	1			T566	1		T883	6		T467	11
values[120]	71	1			T566	1		T883	2		T467	4
values[121]	85	1			T566	1		T883	2		T467	3
values[122]	72	1			T566	1		T883	4		T467	2
values[123]	93	1			T566	2		T883	4		T467	14
values[124]	84	1			T566	1		T883	6		T467	6
values[125]	86	1			T566	1		T883	1		T467	8
values[126]	147	1			T566	4		T467	11		T901	2
values[127]	854	1			T566	32		T467	17		T901	29
values[128]	7305	1			T566	261		T467	8		T901	308