Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.usbdev_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	138416	1			T70	30		T71	46		T72	53
values[2]	11279	1			T122	3		T256	72		T255	2
values[3]	5460	1			T256	47		T555	1		T566	1
values[4]	2974	1			T256	14		T555	1		T566	1
values[5]	1827	1			T256	15		T555	1		T566	1
values[6]	1247	1			T256	15		T555	1		T566	1
values[7]	885	1			T256	8		T555	1		T566	1
values[8]	779	1			T256	6		T555	1		T566	1
values[9]	719	1			T256	5		T555	1		T566	1
values[10]	540	1			T555	1		T566	1		T576	14
values[11]	469	1			T555	1		T566	1		T576	6
values[12]	389	1			T555	1		T566	1		T576	4
values[13]	442	1			T555	1		T566	1		T576	15
values[14]	358	1			T555	1		T566	1		T576	14
values[15]	359	1			T555	1		T566	1		T576	6
values[16]	357	1			T555	1		T566	1		T576	18
values[17]	316	1			T555	1		T566	1		T576	6
values[18]	319	1			T555	1		T566	1		T576	16
values[19]	359	1			T555	1		T566	1		T576	13
values[20]	313	1			T555	1		T566	1		T576	10
values[21]	257	1			T555	1		T566	1		T576	9
values[22]	269	1			T555	1		T566	1		T576	5
values[23]	292	1			T555	1		T566	1		T576	16
values[24]	308	1			T555	1		T566	1		T576	12
values[25]	322	1			T555	1		T566	1		T576	5
values[26]	266	1			T555	1		T566	1		T576	6
values[27]	242	1			T555	1		T566	1		T576	6
values[28]	248	1			T555	1		T566	1		T576	3
values[29]	306	1			T555	1		T566	1		T576	14
values[30]	265	1			T555	1		T566	1		T576	16
values[31]	220	1			T555	1		T566	1		T576	7
values[32]	248	1			T555	1		T566	1		T576	7
values[33]	259	1			T555	1		T566	1		T576	11
values[34]	305	1			T555	1		T566	1		T576	22
values[35]	282	1			T555	1		T566	1		T576	11
values[36]	228	1			T555	1		T566	1		T576	7
values[37]	255	1			T555	1		T566	1		T576	9
values[38]	233	1			T555	1		T566	1		T576	13
values[39]	313	1			T555	1		T566	1		T576	7
values[40]	251	1			T555	1		T566	1		T576	7
values[41]	245	1			T555	1		T566	1		T576	4
values[42]	263	1			T555	1		T566	1		T576	15
values[43]	241	1			T555	1		T566	1		T576	35
values[44]	189	1			T555	1		T566	1		T576	5
values[45]	211	1			T555	1		T566	1		T576	8
values[46]	219	1			T555	1		T566	1		T576	4
values[47]	206	1			T555	1		T566	1		T576	7
values[48]	185	1			T555	1		T566	1		T576	3
values[49]	169	1			T555	1		T566	1		T576	9
values[50]	157	1			T555	1		T566	1		T576	10
values[51]	140	1			T555	1		T566	1		T576	15
values[52]	170	1			T555	1		T566	1		T576	14
values[53]	127	1			T555	1		T566	1		T510	2
values[54]	99	1			T555	1		T566	1		T510	2
values[55]	103	1			T555	1		T566	1		T510	1
values[56]	81	1			T555	1		T566	1		T510	2
values[57]	81	1			T555	1		T566	1		T510	2
values[58]	80	1			T555	1		T566	1		T510	4
values[59]	61	1			T555	1		T566	1		T510	4
values[60]	59	1			T555	1		T566	1		T510	1
values[61]	65	1			T555	1		T566	1		T510	3
values[62]	80	1			T555	1		T566	1		T510	5
values[63]	76	1			T555	1		T566	1		T510	6
values[64]	82	1			T555	1		T566	1		T510	2
values[65]	85	1			T555	1		T566	1		T510	1
values[66]	101	1			T555	1		T566	1		T510	2
values[67]	96	1			T555	1		T566	1		T510	1
values[68]	96	1			T555	1		T566	1		T510	3
values[69]	82	1			T555	1		T566	1		T510	6
values[70]	82	1			T555	1		T566	1		T510	3
values[71]	82	1			T555	1		T566	1		T510	1
values[72]	91	1			T555	1		T566	1		T510	2
values[73]	83	1			T555	1		T566	1		T510	2
values[74]	99	1			T555	1		T566	1		T510	7
values[75]	79	1			T555	1		T566	1		T510	5
values[76]	72	1			T555	1		T566	1		T510	2
values[77]	76	1			T555	1		T566	2		T510	2
values[78]	102	1			T555	1		T566	4		T510	8
values[79]	86	1			T555	1		T566	4		T510	11
values[80]	86	1			T555	1		T566	7		T510	7
values[81]	71	1			T555	2		T566	3		T510	7
values[82]	70	1			T555	1		T566	1		T510	7
values[83]	80	1			T555	1		T566	4		T510	3
values[84]	78	1			T555	1		T566	8		T510	4
values[85]	83	1			T555	1		T566	1		T510	6
values[86]	83	1			T555	1		T566	5		T510	7
values[87]	94	1			T555	1		T566	2		T510	13
values[88]	90	1			T555	1		T566	8		T510	12
values[89]	87	1			T555	1		T566	1		T510	6
values[90]	87	1			T555	1		T566	5		T510	2
values[91]	73	1			T555	1		T566	4		T510	4
values[92]	61	1			T555	1		T566	1		T874	2
values[93]	77	1			T555	1		T566	1		T874	2
values[94]	89	1			T555	1		T566	3		T874	2
values[95]	93	1			T555	1		T566	1		T874	2
values[96]	89	1			T555	1		T566	1		T874	2
values[97]	70	1			T555	1		T566	2		T874	2
values[98]	67	1			T555	1		T566	1		T874	2
values[99]	60	1			T555	1		T566	2		T874	2
values[100]	80	1			T555	1		T566	8		T874	2
values[101]	54	1			T555	1		T566	1		T874	2
values[102]	68	1			T555	1		T566	3		T874	2
values[103]	71	1			T555	1		T566	2		T874	4
values[104]	69	1			T555	1		T566	2		T874	5
values[105]	60	1			T555	2		T566	1		T874	4
values[106]	52	1			T555	1		T566	2		T874	4
values[107]	74	1			T555	1		T566	3		T874	5
values[108]	62	1			T555	1		T566	3		T874	4
values[109]	57	1			T555	1		T566	1		T874	2
values[110]	69	1			T555	1		T566	4		T874	4
values[111]	72	1			T555	1		T566	3		T874	2
values[112]	59	1			T555	1		T566	2		T874	2
values[113]	69	1			T555	1		T566	2		T874	2
values[114]	74	1			T555	1		T566	2		T874	2
values[115]	62	1			T555	1		T566	1		T874	3
values[116]	57	1			T555	2		T566	1		T874	3
values[117]	60	1			T555	3		T566	2		T874	2
values[118]	67	1			T555	2		T566	2		T874	4
values[119]	56	1			T555	1		T566	3		T874	4
values[120]	76	1			T555	1		T566	1		T874	8
values[121]	54	1			T555	2		T566	1		T874	3
values[122]	62	1			T555	2		T566	1		T874	6
values[123]	63	1			T555	1		T566	1		T874	2
values[124]	64	1			T555	3		T566	2		T874	6
values[125]	65	1			T555	2		T566	3		T874	7
values[126]	125	1			T555	5		T566	3		T874	9
values[127]	1444	1			T555	77		T566	48		T874	124
values[128]	6660	1			T555	291		T566	263		T874	584