Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	515	1			T555	1		T518	5		T902	1
all_values[1]	522	1			T256	1		T554	1		T565	1
all_values[2]	461	1			T569	1		T554	1		T555	1
all_values[3]	487	1			T256	1		T569	1		T518	5
all_values[4]	466	1			T554	1		T518	3		T902	1
all_values[5]	515	1			T554	2		T555	1		T518	5
all_values[6]	523	1			T256	1		T555	1		T518	1
all_values[7]	470	1			T569	1		T518	5		T566	2
all_values[8]	505	1			T518	2		T558	1		T576	2
all_values[9]	507	1			T256	1		T554	1		T565	1
all_values[10]	477	1			T569	1		T518	15		T566	1
all_values[11]	470	1			T569	1		T518	6		T902	2
all_values[12]	476	1			T518	1		T902	1		T737	1
all_values[13]	550	1			T554	1		T518	4		T566	1
all_values[14]	457	1			T569	1		T518	2		T902	2
all_values[15]	488	1			T569	1		T518	2		T902	3
all_values[16]	496	1			T518	3		T902	2		T558	1
all_values[17]	460	1			T569	1		T518	5		T902	1
all_values[18]	498	1			T554	1		T518	6		T566	1
all_values[19]	505	1			T569	1		T518	6		T566	1
all_values[20]	485	1			T554	1		T555	1		T518	3
all_values[21]	491	1			T569	1		T555	1		T565	1
all_values[22]	505	1			T256	1		T555	1		T518	6
all_values[23]	511	1			T554	1		T518	3		T566	1
all_values[24]	471	1			T569	1		T518	6		T566	1
all_values[25]	548	1			T569	1		T554	1		T555	1
all_values[26]	477	1			T554	3		T518	7		T902	5
all_values[27]	476	1			T569	1		T555	1		T518	6
all_values[28]	489	1			T554	2		T518	3		T737	1
all_values[29]	475	1			T518	4		T902	1		T737	2
all_values[30]	462	1			T554	1		T518	9		T902	2
all_values[31]	485	1			T569	2		T554	1		T555	1
all_values[32]	497	1			T554	1		T518	4		T566	1
all_values[33]	534	1			T569	1		T554	1		T555	1
all_values[34]	511	1			T569	1		T555	1		T518	4
all_values[35]	467	1			T569	1		T555	1		T518	9
all_values[36]	472	1			T569	1		T554	2		T555	3
all_values[37]	490	1			T569	1		T554	2		T565	1
all_values[38]	485	1			T569	1		T554	2		T518	2
all_values[39]	486	1			T554	1		T565	1		T518	3
all_values[40]	490	1			T256	1		T565	1		T518	3
all_values[41]	522	1			T554	2		T555	1		T518	4
all_values[42]	524	1			T569	1		T555	1		T518	1
all_values[43]	475	1			T554	2		T518	3		T566	1
all_values[44]	435	1			T518	2		T566	1		T902	1
all_values[45]	489	1			T256	1		T554	1		T518	7
all_values[46]	502	1			T569	1		T555	1		T518	7
all_values[47]	498	1			T518	3		T558	1		T492	2
all_values[48]	502	1			T518	1		T902	2		T558	1
all_values[49]	473	1			T518	6		T902	1		T737	3