Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3426	1			T256	1		T569	6		T554	2
all_values[1]	3516	1			T256	3		T569	2		T554	3
all_values[2]	3486	1			T256	4		T569	6		T554	3
all_values[3]	3471	1			T70	3		T256	3		T569	7
all_values[4]	3492	1			T256	4		T569	6		T554	8
all_values[5]	3417	1			T569	7		T554	1		T518	39
all_values[6]	3458	1			T256	1		T569	4		T554	3
all_values[7]	3518	1			T569	11		T554	3		T518	40
all_values[8]	3499	1			T569	5		T554	4		T518	47
all_values[9]	3543	1			T256	2		T569	2		T554	4
all_values[10]	3501	1			T70	1		T256	2		T569	6
all_values[11]	3493	1			T70	2		T256	1		T569	9
all_values[12]	3460	1			T70	1		T569	5		T554	1
all_values[13]	3491	1			T256	1		T569	1		T554	5
all_values[14]	3370	1			T70	1		T256	2		T569	6
all_values[15]	3444	1			T569	5		T554	3		T518	44
all_values[16]	3536	1			T70	2		T256	1		T569	6
all_values[17]	3486	1			T256	1		T569	3		T554	6
all_values[18]	3500	1			T70	1		T256	2		T569	5
all_values[19]	3437	1			T256	3		T569	5		T554	3
all_values[20]	3498	1			T70	1		T256	1		T569	7
all_values[21]	3505	1			T70	1		T256	2		T569	6
all_values[22]	3541	1			T256	3		T569	7		T554	1
all_values[23]	3401	1			T70	1		T256	4		T569	7
all_values[24]	3386	1			T70	2		T256	1		T569	4
all_values[25]	3362	1			T70	1		T256	1		T569	8
all_values[26]	3459	1			T256	2		T569	5		T554	6
all_values[27]	3408	1			T70	2		T256	2		T569	9
all_values[28]	3418	1			T256	2		T569	8		T554	3
all_values[29]	3526	1			T256	1		T569	2		T554	3
all_values[30]	3540	1			T70	1		T256	2		T569	6
all_values[31]	3409	1			T70	2		T569	7		T554	1
all_values[32]	3387	1			T569	6		T554	4		T518	47
all_values[33]	3508	1			T70	3		T256	1		T569	7
all_values[34]	3535	1			T256	1		T569	2		T554	4
all_values[35]	3445	1			T256	4		T569	3		T554	5
all_values[36]	3449	1			T70	1		T569	5		T554	6
all_values[37]	3505	1			T70	1		T256	2		T569	6
all_values[38]	3455	1			T569	1		T518	45		T902	17
all_values[39]	3440	1			T569	2		T554	3		T518	36
all_values[40]	3518	1			T70	2		T256	2		T569	6
all_values[41]	3469	1			T70	1		T256	2		T569	3
all_values[42]	3393	1			T256	3		T569	2		T518	45
all_values[43]	3525	1			T70	1		T256	1		T569	4
all_values[44]	3509	1			T256	2		T569	4		T554	2
all_values[45]	3407	1			T70	1		T256	1		T569	5
all_values[46]	3474	1			T256	2		T569	5		T554	8
all_values[47]	3530	1			T70	1		T256	1		T569	8
all_values[48]	3473	1			T70	1		T256	2		T569	2
all_values[49]	3559	1			T70	3		T256	1		T569	3
all_values[50]	3562	1			T70	2		T256	2		T569	7
all_values[51]	3472	1			T70	2		T256	3		T569	9
all_values[52]	3479	1			T569	8		T554	7		T518	37
all_values[53]	3445	1			T256	1		T569	7		T554	2
all_values[54]	3423	1			T70	2		T569	5		T554	2
all_values[55]	3382	1			T70	1		T256	1		T569	3
all_values[56]	3440	1			T70	1		T256	1		T569	5
all_values[57]	3485	1			T256	1		T569	4		T554	1
all_values[58]	3493	1			T256	3		T569	3		T554	1
all_values[59]	3488	1			T70	1		T256	2		T569	6
all_values[60]	3479	1			T569	3		T554	7		T518	49
all_values[61]	3454	1			T256	2		T569	6		T554	4
all_values[62]	3476	1			T256	1		T569	3		T554	3
all_values[63]	3439	1			T70	2		T256	1		T569	6