Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_main__regs_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	158261	1			T81	43		T86	2		T84	613
values[2]	3906	1			T84	9		T255	1		T521	1
values[3]	1866	1			T832	96		T847	1		T655	4
values[4]	1446	1			T832	60		T847	1		T655	2
values[5]	1104	1			T832	32		T847	1		T655	1
values[6]	907	1			T832	14		T847	1		T655	4
values[7]	882	1			T832	19		T847	1		T655	2
values[8]	680	1			T832	15		T847	1		T655	1
values[9]	619	1			T832	19		T847	1		T655	3
values[10]	567	1			T832	20		T847	1		T655	4
values[11]	434	1			T832	22		T847	1		T655	1
values[12]	402	1			T832	11		T847	1		T655	1
values[13]	343	1			T832	7		T847	1		T655	3
values[14]	315	1			T832	1		T847	1		T655	4
values[15]	324	1			T847	1		T655	2		T848	1
values[16]	303	1			T847	1		T655	1		T848	1
values[17]	294	1			T847	1		T655	1		T848	1
values[18]	257	1			T847	1		T655	2		T848	1
values[19]	243	1			T847	1		T655	5		T848	1
values[20]	258	1			T847	1		T655	2		T848	1
values[21]	246	1			T847	1		T655	2		T848	1
values[22]	189	1			T847	1		T655	1		T848	1
values[23]	170	1			T847	1		T655	3		T848	1
values[24]	142	1			T847	1		T655	1		T848	1
values[25]	140	1			T847	1		T655	2		T848	1
values[26]	131	1			T847	1		T655	9		T848	1
values[27]	89	1			T847	1		T655	3		T848	1
values[28]	103	1			T847	1		T655	2		T848	1
values[29]	91	1			T847	1		T655	1		T848	1
values[30]	74	1			T847	1		T655	2		T848	1
values[31]	53	1			T847	1		T655	7		T848	1
values[32]	50	1			T847	1		T655	3		T848	1
values[33]	49	1			T847	1		T655	1		T848	1
values[34]	74	1			T847	1		T655	4		T848	1
values[35]	113	1			T847	1		T655	4		T848	1
values[36]	100	1			T847	1		T655	3		T848	1
values[37]	73	1			T847	1		T655	1		T848	1
values[38]	85	1			T847	1		T655	2		T848	1
values[39]	71	1			T847	1		T655	3		T848	2
values[40]	59	1			T847	1		T655	1		T848	1
values[41]	61	1			T847	1		T655	1		T848	1
values[42]	82	1			T847	1		T655	1		T848	1
values[43]	90	1			T847	1		T655	4		T848	1
values[44]	74	1			T847	1		T655	5		T848	1
values[45]	49	1			T847	1		T655	1		T848	1
values[46]	53	1			T847	1		T655	1		T848	1
values[47]	63	1			T847	1		T655	1		T848	1
values[48]	63	1			T847	1		T655	3		T848	1
values[49]	49	1			T847	1		T655	2		T848	1
values[50]	39	1			T847	1		T655	1		T848	1
values[51]	28	1			T847	1		T655	1		T848	1
values[52]	42	1			T847	1		T655	2		T848	1
values[53]	58	1			T847	1		T655	5		T848	1
values[54]	55	1			T847	1		T655	2		T848	1
values[55]	41	1			T847	1		T655	3		T848	1
values[56]	35	1			T847	1		T655	3		T848	1
values[57]	35	1			T847	1		T655	1		T848	1
values[58]	38	1			T847	1		T655	1		T848	1
values[59]	42	1			T847	1		T655	3		T848	1
values[60]	35	1			T847	1		T655	2		T848	1
values[61]	38	1			T847	1		T655	1		T848	1
values[62]	43	1			T847	1		T655	6		T848	1
values[63]	45	1			T847	1		T655	4		T848	1
values[64]	38	1			T847	1		T655	1		T848	1
values[65]	34	1			T847	1		T655	1		T848	1
values[66]	40	1			T847	1		T655	5		T848	1
values[67]	40	1			T847	1		T655	7		T848	1
values[68]	41	1			T847	1		T655	3		T848	1
values[69]	46	1			T847	1		T655	1		T848	1
values[70]	37	1			T847	1		T655	1		T848	1
values[71]	39	1			T847	1		T655	1		T848	1
values[72]	50	1			T847	1		T655	3		T848	1
values[73]	57	1			T847	1		T655	1		T848	1
values[74]	48	1			T847	1		T655	2		T848	1
values[75]	42	1			T847	1		T655	1		T848	1
values[76]	40	1			T847	1		T655	3		T848	1
values[77]	37	1			T847	1		T655	1		T848	1
values[78]	38	1			T847	1		T655	4		T848	1
values[79]	42	1			T847	1		T655	7		T848	1
values[80]	47	1			T847	1		T655	3		T848	1
values[81]	45	1			T847	1		T655	1		T848	1
values[82]	43	1			T847	1		T655	1		T848	1
values[83]	47	1			T847	1		T655	2		T848	1
values[84]	47	1			T847	1		T655	3		T848	1
values[85]	54	1			T847	1		T655	4		T848	1
values[86]	56	1			T847	1		T655	3		T848	1
values[87]	51	1			T847	1		T655	6		T848	1
values[88]	59	1			T847	1		T655	3		T848	1
values[89]	67	1			T847	1		T655	3		T848	1
values[90]	46	1			T847	1		T655	3		T848	1
values[91]	57	1			T847	1		T655	4		T848	1
values[92]	57	1			T847	1		T655	4		T848	1
values[93]	55	1			T847	1		T655	1		T848	1
values[94]	61	1			T847	1		T655	8		T848	1
values[95]	69	1			T847	1		T655	11		T848	1
values[96]	62	1			T847	1		T655	9		T848	1
values[97]	63	1			T847	1		T655	7		T848	1
values[98]	60	1			T847	2		T655	6		T848	1
values[99]	48	1			T847	3		T655	1		T848	1
values[100]	53	1			T847	2		T655	2		T848	1
values[101]	52	1			T847	5		T655	4		T848	1
values[102]	53	1			T847	1		T655	1		T848	2
values[103]	56	1			T847	5		T655	1		T848	1
values[104]	63	1			T847	1		T655	3		T848	2
values[105]	54	1			T847	2		T655	2		T848	1
values[106]	57	1			T847	4		T655	3		T848	1
values[107]	68	1			T847	3		T655	2		T848	2
values[108]	79	1			T847	2		T655	4		T848	2
values[109]	81	1			T847	4		T655	7		T848	3
values[110]	79	1			T847	4		T655	6		T848	3
values[111]	79	1			T847	1		T655	2		T848	10
values[112]	73	1			T847	1		T655	5		T848	2
values[113]	91	1			T847	3		T655	13		T848	3
values[114]	98	1			T847	5		T655	4		T848	1
values[115]	91	1			T847	1		T655	2		T848	1
values[116]	87	1			T847	1		T655	6		T848	2
values[117]	82	1			T847	1		T655	6		T848	2
values[118]	68	1			T847	1		T655	3		T848	1
values[119]	69	1			T847	2		T655	1		T848	1
values[120]	67	1			T847	1		T655	3		T848	2
values[121]	89	1			T847	2		T655	5		T848	2
values[122]	88	1			T847	3		T655	6		T848	2
values[123]	100	1			T847	4		T655	5		T848	5
values[124]	151	1			T847	7		T655	11		T848	1
values[125]	287	1			T847	1		T655	22		T848	1
values[126]	597	1			T847	10		T655	16		T848	18
values[127]	1634	1			T847	101		T655	13		T848	123
values[128]	2671	1			T847	166		T655	3		T848	184