Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	95.47	93.78	95.32		94.52	97.53	99.61

Total tests in report: 2936

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
43.23	43.23	55.45	55.45	49.72	49.72	27.59	27.59			67.38	67.38	59.09	59.09	0.13	0.13	/workspace/coverage/default/0.chip_plic_all_irqs_10.1073630544
53.50	10.27	61.28	5.83	67.60	17.88	28.11	0.53			77.96	10.58	84.27	25.17	1.79	1.66	/workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.817833677
61.57	8.07	73.11	11.83	68.59	0.99	32.38	4.27			78.47	0.52	84.27	0.00	32.57	30.78	/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2385495479
64.75	3.18	73.11	0.00	68.60	0.01	51.02	18.64			78.48	0.01	84.62	0.35	32.68	0.11	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1763426420
67.92	3.17	73.11	0.00	68.60	0.01	51.02	0.00			78.48	0.00	84.62	0.00	51.71	19.03	/workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.3897237637
71.09	3.16	78.30	5.20	72.50	3.90	54.60	3.58			80.25	1.77	89.16	4.55	51.71	0.00	/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3025543986
73.63	2.54	78.41	0.10	73.88	1.38	57.47	2.88			80.75	0.50	89.16	0.00	62.10	10.39	/workspace/coverage/cover_reg_top/32.xbar_stress_all.208928642
75.89	2.26	81.19	2.78	77.00	3.11	62.33	4.85			83.20	2.44	89.51	0.35	62.10	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3451915339
77.96	2.08	81.19	0.00	77.00	0.00	62.33	0.00			83.20	0.00	89.51	0.00	74.55	12.45	/workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.679283913
79.86	1.90	83.96	2.77	78.44	1.45	67.59	5.26			84.08	0.88	90.56	1.05	74.55	0.00	/workspace/coverage/default/2.chip_sw_power_virus.583871867
81.43	1.56	84.25	0.29	78.59	0.15	76.01	8.41			84.26	0.18	90.91	0.35	74.55	0.00	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2706553332
82.87	1.45	84.25	0.00	78.59	0.00	76.01	0.00			84.26	0.00	90.91	0.00	83.22	8.67	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.2443469322
84.26	1.39	86.50	2.25	80.66	2.07	77.61	1.60			86.66	2.40	90.91	0.00	83.22	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.1913934836
85.35	1.08	88.09	1.59	82.88	2.21	77.76	0.15			89.22	2.56	90.91	0.00	83.22	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.639238229
86.34	1.00	88.09	0.00	82.88	0.00	83.75	5.99			89.22	0.00	90.91	0.00	83.22	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2926490704
87.27	0.93	88.09	0.00	82.88	0.00	83.75	0.00			89.22	0.00	90.91	0.00	88.78	5.56	/workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.3687210099
88.15	0.88	89.14	1.05	83.65	0.78	84.68	0.93			90.13	0.91	92.48	1.57	88.83	0.05	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2430908654
88.96	0.81	89.85	0.71	83.80	0.15	84.69	0.01			90.28	0.15	96.33	3.85	88.83	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.1221884511
89.62	0.65	91.12	1.27	84.81	1.01	85.15	0.45			91.47	1.19	96.33	0.00	88.83	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2083441115
90.21	0.60	91.64	0.52	85.14	0.32	87.31	2.16			91.66	0.19	96.33	0.00	89.21	0.39	/workspace/coverage/default/1.chip_jtag_csr_rw.726697243
90.72	0.50	91.64	0.00	85.26	0.12	87.31	0.00			91.68	0.02	96.33	0.00	92.09	2.88	/workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.4064149222
91.13	0.41	92.47	0.83	86.11	0.85	87.49	0.19			92.28	0.61	96.33	0.00	92.10	0.01	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368529697
91.50	0.37	92.47	0.00	86.11	0.00	88.57	1.08			92.28	0.00	96.33	0.00	93.24	1.14	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2752440115
91.85	0.35	93.16	0.69	86.64	0.53	88.98	0.41			92.73	0.45	96.33	0.00	93.24	0.00	/workspace/coverage/default/0.chip_sw_gpio.2353681268
92.17	0.32	93.59	0.43	87.87	1.23	88.99	0.01			92.99	0.26	96.33	0.00	93.24	0.00	/workspace/coverage/cover_reg_top/16.chip_csr_rw.1824524235
92.47	0.30	93.59	0.01	87.98	0.12	89.56	0.57			93.01	0.02	96.33	0.00	94.35	1.10	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3506377798
92.75	0.28	93.59	0.00	88.08	0.10	89.56	0.00			93.01	0.00	96.33	0.00	95.92	1.57	/workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.3720218367
92.98	0.23	93.59	0.01	89.43	1.34	89.56	0.00			93.01	0.00	96.33	0.00	95.98	0.06	/workspace/coverage/cover_reg_top/24.chip_tl_errors.1101301333
93.21	0.23	93.60	0.01	89.43	0.01	90.87	1.31			93.01	0.00	96.33	0.00	96.03	0.05	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2047417479
93.39	0.18	93.67	0.07	89.47	0.04	91.62	0.75			93.03	0.02	96.33	0.00	96.22	0.19	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1748374313
93.55	0.16	93.68	0.01	89.92	0.45	91.63	0.01			93.55	0.52	96.33	0.00	96.22	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.555306540
93.70	0.15	93.89	0.21	90.24	0.32	91.98	0.35			93.55	0.00	96.33	0.00	96.22	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4063283620
93.84	0.14	93.89	0.00	90.24	0.00	91.98	0.00			93.55	0.00	96.33	0.00	97.06	0.85	/workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3962899660
93.96	0.11	93.89	0.00	90.29	0.05	91.98	0.00			93.57	0.02	96.33	0.00	97.69	0.62	/workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1487904459
94.07	0.11	93.89	0.00	90.68	0.39	91.98	0.00			93.60	0.03	96.33	0.00	97.93	0.25	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.3547094996
94.18	0.11	93.89	0.00	90.68	0.00	92.62	0.64			93.60	0.00	96.33	0.00	97.93	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.798478627
94.26	0.08	93.89	0.00	90.68	0.00	93.13	0.50			93.60	0.00	96.33	0.00	97.93	0.00	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3103925343
94.34	0.08	94.10	0.21	90.85	0.17	93.13	0.01			93.72	0.12	96.33	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3702048906
94.42	0.08	94.24	0.14	90.97	0.12	93.20	0.07			93.85	0.13	96.33	0.00	97.93	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2305725632
94.49	0.08	94.27	0.03	91.02	0.05	93.33	0.13			93.85	0.00	96.33	0.00	98.18	0.25	/workspace/coverage/default/1.chip_sw_alert_test.1251449249
94.57	0.07	94.27	0.00	91.46	0.45	93.33	0.00			93.85	0.00	96.33	0.00	98.18	0.00	/workspace/coverage/cover_reg_top/15.chip_tl_errors.731391621
94.64	0.07	94.27	0.00	91.67	0.20	93.33	0.00			94.06	0.21	96.33	0.00	98.18	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3679281613
94.71	0.07	94.29	0.02	91.71	0.04	93.42	0.09			94.09	0.03	96.50	0.17	98.23	0.05	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3861191091
94.76	0.05	94.32	0.03	91.73	0.02	93.47	0.06			94.13	0.03	96.68	0.17	98.23	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1290738197
94.81	0.05	94.34	0.02	91.78	0.05	93.49	0.02			94.17	0.04	96.85	0.17	98.24	0.01	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1387118045
94.86	0.05	94.39	0.06	92.01	0.23	93.49	0.01			94.18	0.02	96.85	0.00	98.24	0.00	/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1882633018
94.91	0.05	94.47	0.08	92.15	0.14	93.55	0.06			94.21	0.02	96.85	0.00	98.24	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.765018562
94.96	0.05	94.50	0.02	92.19	0.04	93.55	0.00			94.23	0.02	97.03	0.17	98.25	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1207776346
95.00	0.04	94.50	0.00	92.19	0.00	93.81	0.26			94.23	0.00	97.03	0.00	98.25	0.00	/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.3756980172
95.04	0.04	94.50	0.00	92.19	0.00	94.06	0.25			94.23	0.00	97.03	0.00	98.25	0.00	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3845503715
95.08	0.04	94.50	0.01	92.20	0.01	94.07	0.02			94.24	0.01	97.20	0.17	98.26	0.01	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2002082150
95.12	0.04	94.50	0.01	92.21	0.01	94.08	0.01			94.25	0.01	97.38	0.17	98.27	0.01	/workspace/coverage/default/4.chip_sw_all_escalation_resets.1260113759
95.15	0.04	94.58	0.07	92.21	0.00	94.21	0.13			94.26	0.01	97.38	0.00	98.27	0.00	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2081580074
95.19	0.04	94.58	0.00	92.29	0.08	94.21	0.00			94.26	0.00	97.38	0.00	98.40	0.13	/workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3337124796
95.22	0.03	94.58	0.00	92.48	0.19	94.21	0.00			94.26	0.00	97.38	0.00	98.41	0.01	/workspace/coverage/cover_reg_top/3.chip_tl_errors.2496370464
95.25	0.03	94.58	0.00	92.48	0.00	94.22	0.01			94.26	0.00	97.55	0.17	98.41	0.00	/workspace/coverage/default/0.chip_sw_data_integrity_escalation.1921926361
95.28	0.03	94.58	0.00	92.66	0.18	94.22	0.00			94.26	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.1671442576
95.31	0.03	94.59	0.02	92.71	0.05	94.30	0.09			94.28	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1842228672
95.34	0.03	94.67	0.07	92.74	0.03	94.32	0.01			94.33	0.05	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2154426327
95.36	0.03	94.67	0.00	92.74	0.00	94.47	0.15			94.33	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1178150572
95.39	0.02	94.73	0.07	92.78	0.05	94.47	0.00			94.36	0.03	97.55	0.00	98.41	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1092605514
95.41	0.02	94.74	0.01	92.78	0.00	94.59	0.12			94.37	0.01	97.55	0.00	98.41	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1813882031
95.43	0.02	94.81	0.07	92.83	0.05	94.59	0.00			94.39	0.02	97.55	0.00	98.41	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2274632722
95.45	0.02	94.81	0.00	92.90	0.07	94.59	0.00			94.44	0.06	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2496495989
95.47	0.02	94.81	0.00	92.90	0.00	94.70	0.12			94.44	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1697860940
95.49	0.02	94.81	0.00	93.01	0.11	94.70	0.00			94.44	0.00	97.55	0.00	98.41	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.3308747209
95.51	0.02	94.81	0.00	93.01	0.01	94.70	0.00			94.44	0.00	97.55	0.00	98.52	0.11	/workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.4146125510
95.52	0.02	94.81	0.00	93.12	0.11	94.70	0.00			94.44	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/cover_reg_top/5.chip_tl_errors.453730146
95.54	0.01	94.82	0.02	93.15	0.03	94.73	0.02			94.46	0.02	97.55	0.00	98.52	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1171991010
95.55	0.01	94.82	0.00	93.16	0.01	94.80	0.07			94.46	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2108259204
95.56	0.01	94.82	0.00	93.16	0.00	94.87	0.07			94.46	0.00	97.55	0.00	98.52	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1389866201
95.58	0.01	94.82	0.00	93.16	0.01	94.87	0.00			94.46	0.00	97.55	0.00	98.59	0.07	/workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.2040139659
95.59	0.01	94.82	0.00	93.23	0.07	94.87	0.00			94.46	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.2023727872
95.60	0.01	94.82	0.00	93.29	0.05	94.87	0.00			94.46	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/cover_reg_top/17.chip_tl_errors.625085491
95.61	0.01	94.84	0.02	93.29	0.01	94.88	0.01			94.47	0.02	97.55	0.00	98.59	0.00	/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1358319004
95.61	0.01	94.84	0.01	93.31	0.02	94.91	0.03			94.47	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1662747407
95.62	0.01	94.87	0.02	93.32	0.01	94.92	0.01			94.49	0.02	97.55	0.00	98.59	0.00	/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1565497003
95.63	0.01	94.87	0.00	93.33	0.01	94.96	0.04			94.49	0.00	97.55	0.00	98.59	0.00	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2531927026
95.64	0.01	94.87	0.00	93.35	0.02	94.96	0.00			94.49	0.00	97.55	0.00	98.61	0.02	/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.464943229
95.65	0.01	94.87	0.00	93.35	0.00	94.99	0.04			94.49	0.00	97.55	0.00	98.63	0.01	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2684740195
95.65	0.01	94.87	0.00	93.39	0.04	94.99	0.00			94.49	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.1648736813
95.66	0.01	94.87	0.00	93.39	0.00	95.04	0.04			94.49	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2365236050
95.67	0.01	94.87	0.01	93.41	0.01	95.06	0.02			94.49	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.401773594
95.67	0.01	94.87	0.00	93.45	0.04	95.06	0.00			94.49	0.00	97.55	0.00	98.63	0.00	/workspace/coverage/cover_reg_top/6.xbar_stress_all.2784324594
95.68	0.01	94.87	0.00	93.45	0.01	95.06	0.00			94.49	0.00	97.55	0.00	98.66	0.04	/workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.1400872038
95.69	0.01	94.88	0.01	93.46	0.01	95.06	0.01			94.50	0.01	97.55	0.00	98.67	0.01	/workspace/coverage/default/75.chip_sw_all_escalation_resets.872155379
95.69	0.01	94.88	0.00	93.47	0.01	95.06	0.00			94.50	0.00	97.55	0.00	98.70	0.02	/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.3935751708
95.70	0.01	94.88	0.00	93.49	0.03	95.06	0.00			94.50	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/cover_reg_top/20.chip_tl_errors.3321973801
95.70	0.01	94.88	0.00	93.52	0.03	95.06	0.00			94.50	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2674517698
95.71	0.01	94.88	0.00	93.52	0.00	95.09	0.03			94.50	0.00	97.55	0.00	98.70	0.00	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2723752466
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95.82	0.01	94.88	0.00	93.65	0.00	95.21	0.00			94.51	0.00	97.55	0.00	99.12	0.01	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.615706036
95.82	0.01	94.88	0.00	93.65	0.00	95.21	0.00			94.51	0.00	97.55	0.00	99.13	0.01	/workspace/coverage/default/25.chip_sw_all_escalation_resets.3225792241
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95.83	0.01	94.88	0.00	93.65	0.00	95.21	0.00			94.51	0.00	97.55	0.00	99.19	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3972970017
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95.90	0.01	94.88	0.00	93.65	0.00	95.21	0.00			94.51	0.00	97.55	0.00	99.61	0.01	/workspace/coverage/default/90.chip_sw_all_escalation_resets.2275722042
95.90	0.01	94.89	0.01	93.65	0.00	95.21	0.01			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3466807175
95.91	0.01	94.89	0.00	93.66	0.01	95.21	0.00			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/23.chip_tl_errors.2753188596
95.91	0.01	94.89	0.00	93.67	0.01	95.21	0.00			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1107550403
95.91	0.01	94.89	0.00	93.69	0.01	95.21	0.00			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2940109746
95.91	0.01	94.89	0.00	93.70	0.01	95.21	0.00			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.3646169009
95.91	0.01	94.89	0.00	93.70	0.00	95.22	0.01			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1053692338
95.91	0.01	94.89	0.00	93.70	0.00	95.23	0.01			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/78.xbar_random_large_delays.2905961147
95.92	0.01	94.89	0.00	93.70	0.00	95.24	0.01			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.224586729
95.92	0.01	94.89	0.00	93.70	0.00	95.25	0.01			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3436072647
95.92	0.01	94.89	0.00	93.70	0.00	95.26	0.01			94.51	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.532152206
95.92	0.01	94.89	0.00	93.70	0.00	95.26	0.00			94.52	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3815672584
95.92	0.01	94.89	0.00	93.70	0.00	95.26	0.00			94.52	0.01	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_tap_straps_dev.1067200243
95.92	0.01	94.89	0.00	93.70	0.01	95.26	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1895354935
95.92	0.01	94.89	0.00	93.71	0.01	95.26	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/13.xbar_access_same_device.254349067
95.93	0.01	94.89	0.00	93.72	0.01	95.26	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.67858701
95.93	0.01	94.89	0.00	93.72	0.01	95.26	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_gpio.3882128054
95.93	0.01	94.89	0.00	93.73	0.01	95.26	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2873425012
95.93	0.01	94.89	0.00	93.73	0.00	95.27	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3808393568
95.93	0.01	94.89	0.00	93.73	0.00	95.27	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2945186956
95.93	0.01	94.89	0.01	93.73	0.00	95.28	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3808315788
95.93	0.01	94.89	0.00	93.73	0.00	95.28	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.1218759891
95.93	0.01	94.89	0.00	93.73	0.00	95.29	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3493899357
95.93	0.01	94.89	0.00	93.73	0.00	95.29	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2202979942
95.93	0.01	94.89	0.00	93.73	0.00	95.30	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.973123190
95.93	0.01	94.89	0.00	93.73	0.00	95.30	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3202049026
95.94	0.01	94.89	0.00	93.73	0.00	95.31	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3982854122
95.94	0.01	94.89	0.00	93.73	0.00	95.31	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2949872080
95.94	0.01	94.89	0.00	93.73	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2431205714
95.94	0.01	94.89	0.00	93.74	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/26.chip_tl_errors.3488714660
95.94	0.01	94.89	0.00	93.74	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3149428340
95.94	0.01	94.89	0.00	93.75	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.1385629701
95.94	0.01	94.89	0.00	93.75	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/88.xbar_error_random.866724292
95.94	0.01	94.89	0.00	93.75	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.4157259651
95.94	0.01	94.89	0.00	93.76	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.2715935726
95.94	0.01	94.89	0.00	93.76	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3534312237
95.94	0.01	94.89	0.00	93.76	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2134860630
95.94	0.01	94.89	0.00	93.77	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1216983792
95.94	0.01	94.89	0.00	93.77	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3743573844
95.94	0.01	94.89	0.00	93.77	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/2.chip_jtag_csr_rw.3526945129
95.94	0.01	94.89	0.00	93.78	0.01	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2740592565
95.94	0.01	94.89	0.00	93.78	0.00	95.31	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/4.chip_tap_straps_rma.3299114853
95.95	0.01	94.89	0.01	93.78	0.00	95.31	0.00			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2004238420
95.95	0.01	94.89	0.00	93.78	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.3225311079
95.95	0.01	94.89	0.00	93.78	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.chip_sw_example_manufacturer.1604266815
95.95	0.01	94.89	0.00	93.78	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3029886778
95.95	0.01	94.89	0.00	93.78	0.00	95.32	0.01			94.52	0.00	97.55	0.00	99.61	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1116995895

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3398331849
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.4248365155
/workspace/coverage/cover_reg_top/0.chip_csr_rw.1857574863
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.4123633520
/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.4083404488
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.4042828555
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1327120150
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.394686536
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3172612498
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.3260992441
/workspace/coverage/cover_reg_top/0.xbar_error_random.3320691096
/workspace/coverage/cover_reg_top/0.xbar_random.2939284881
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.711316381
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.187227313
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.4099919829
/workspace/coverage/cover_reg_top/0.xbar_same_source.2623996021
/workspace/coverage/cover_reg_top/0.xbar_smoke.408461956
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.4134930829
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2721250235
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.509888926
/workspace/coverage/cover_reg_top/0.xbar_stress_all.1666677905
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3428503462
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.629419846
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1526553721
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1708787085
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2805443884
/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.4262538978
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.3469062800
/workspace/coverage/cover_reg_top/1.chip_csr_rw.2518904018
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.1342501537
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.940830877
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.110757100
/workspace/coverage/cover_reg_top/1.chip_tl_errors.2849469231
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.2283005012
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1318014004
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2902931798
/workspace/coverage/cover_reg_top/1.xbar_error_random.1244192203
/workspace/coverage/cover_reg_top/1.xbar_random.3462418345
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2553848636
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.368504303
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3858764961
/workspace/coverage/cover_reg_top/1.xbar_same_source.254033548
/workspace/coverage/cover_reg_top/1.xbar_smoke.2745343721
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2560204738
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2692750854
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.611550362
/workspace/coverage/cover_reg_top/1.xbar_stress_all.2876084579
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1743988104
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.3233632893
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4146713035
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.2920360468
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.2129519228
/workspace/coverage/cover_reg_top/10.chip_csr_rw.3170350287
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1232102099
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3063396843
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.3741557134
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3757238070
/workspace/coverage/cover_reg_top/10.xbar_error_random.3554502606
/workspace/coverage/cover_reg_top/10.xbar_random.2065543602
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.2923621661
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.2866931589
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.576874652
/workspace/coverage/cover_reg_top/10.xbar_same_source.1168033932
/workspace/coverage/cover_reg_top/10.xbar_smoke.1825725605
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.482191443
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2607517417
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3857714474
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2902698441
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1382802764
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2638118682
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.3794182212
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.2842124250
/workspace/coverage/cover_reg_top/11.chip_csr_rw.2281090296
/workspace/coverage/cover_reg_top/11.chip_tl_errors.1323484995
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.3590860415
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1756572741
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3923105784
/workspace/coverage/cover_reg_top/11.xbar_error_random.1032505672
/workspace/coverage/cover_reg_top/11.xbar_random.873435109
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.535676846
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4028484740
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.361046185
/workspace/coverage/cover_reg_top/11.xbar_same_source.1290444147
/workspace/coverage/cover_reg_top/11.xbar_smoke.1775432963
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.903759437
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.3471091082
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1545380750
/workspace/coverage/cover_reg_top/11.xbar_stress_all.184801259
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3340590300
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2776702501
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.327242345
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.89016956
/workspace/coverage/cover_reg_top/12.chip_csr_rw.920061564
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2927430259
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.1677018357
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1029201113
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.4137803891
/workspace/coverage/cover_reg_top/12.xbar_error_random.3989721224
/workspace/coverage/cover_reg_top/12.xbar_random.1061955930
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.806933816
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.3213749111
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.574454962
/workspace/coverage/cover_reg_top/12.xbar_same_source.4053603295
/workspace/coverage/cover_reg_top/12.xbar_smoke.582784971
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.2703470533
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.1854090245
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3634626418
/workspace/coverage/cover_reg_top/12.xbar_stress_all.1991605786
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1857033760
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1389250214
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.1421104764
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.754769105
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.2709849901
/workspace/coverage/cover_reg_top/13.chip_csr_rw.3347301119
/workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.892780452
/workspace/coverage/cover_reg_top/13.chip_tl_errors.4181931580
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.2706959265
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.1489225949
/workspace/coverage/cover_reg_top/13.xbar_error_random.610149237
/workspace/coverage/cover_reg_top/13.xbar_random.1166026966
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.324759127
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.1807402275
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1985219604
/workspace/coverage/cover_reg_top/13.xbar_same_source.784859593
/workspace/coverage/cover_reg_top/13.xbar_smoke.2743823945
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.136236256
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.893470212
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1509664923
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/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1238172409
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3064770435
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.95144779
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2859420497
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248105388
/workspace/coverage/default/36.chip_sw_all_escalation_resets.83941260
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2217868385
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.906695063
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/workspace/coverage/default/39.chip_sw_all_escalation_resets.3822976889
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.138191705
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2510518878
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/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.4277473240
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.825946438
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/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858792245
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/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.944560690
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1105739412
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/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.753999878
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.477503748
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.3023686840
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1208718472
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3511060355
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3777796749
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4084246373
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2954691970
/workspace/coverage/default/52.chip_sw_all_escalation_resets.4151196059
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.620666174
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3102336739
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3172609701
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.212996985
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3850578288
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1270464150
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.2933191101
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2432957315
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1963474907
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.227306218
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1952400336
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3578502206
/workspace/coverage/default/60.chip_sw_all_escalation_resets.1195759941
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.151732297
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3776877100
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2440131374
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1134911335
/workspace/coverage/default/63.chip_sw_all_escalation_resets.693437987
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4227354596
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3810976769
/workspace/coverage/default/65.chip_sw_all_escalation_resets.3752240179
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.2808437494
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1305302576
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032655569
/workspace/coverage/default/68.chip_sw_all_escalation_resets.3553066846
/workspace/coverage/default/69.chip_sw_all_escalation_resets.397909870
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3863947681
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2055508083
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2420049045
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2145716474
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2718656058
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.350210132
/workspace/coverage/default/70.chip_sw_all_escalation_resets.848971623
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3899844883
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3287970108
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2760559688
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1672461936
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1131086348
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2390656360
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1427747674
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.2387157202
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.377673070
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2510516749
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3706886741
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3380016512
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2478716525
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2578245234
/workspace/coverage/default/79.chip_sw_all_escalation_resets.99813477
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2655817738
/workspace/coverage/default/8.chip_sw_all_escalation_resets.1681378871
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/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3109378311
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2912942393
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2673682533
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/workspace/coverage/default/82.chip_sw_all_escalation_resets.1122924244
/workspace/coverage/default/83.chip_sw_all_escalation_resets.902426827
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/workspace/coverage/default/85.chip_sw_all_escalation_resets.947520207
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2264549285
/workspace/coverage/default/86.chip_sw_all_escalation_resets.570483357
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2782357324
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1321743693
/workspace/coverage/default/88.chip_sw_all_escalation_resets.856580303
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2353107219
/workspace/coverage/default/89.chip_sw_all_escalation_resets.515309020
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.264619649
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3201472595
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1489214666
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.827920573
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4271265619
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2722670358
/workspace/coverage/default/92.chip_sw_all_escalation_resets.2565912760
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3106195202
/workspace/coverage/default/94.chip_sw_all_escalation_resets.1899689871
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1403811820
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3632301908
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3164430661
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2248588599
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1077677341
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.421526056
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2045240816
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2425787393
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.3909217737
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1538960740

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Total test records in report: 2936

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2102228607			Jul 31 08:19:24 PM PDT 24	Jul 31 08:23:27 PM PDT 24	3461672460 ps
T2	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1100504440			Jul 31 08:30:37 PM PDT 24	Jul 31 08:38:11 PM PDT 24	6403917388 ps
T3	/workspace/coverage/default/1.chip_sw_edn_auto_mode.3845503715			Jul 31 08:24:45 PM PDT 24	Jul 31 08:41:19 PM PDT 24	4950941868 ps
T6	/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1763426420			Jul 31 08:30:34 PM PDT 24	Jul 31 08:37:59 PM PDT 24	5222592197 ps
T4	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1778069392			Jul 31 08:20:18 PM PDT 24	Jul 31 08:35:56 PM PDT 24	9190091250 ps
T5	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2831269471			Jul 31 08:29:15 PM PDT 24	Jul 31 08:41:25 PM PDT 24	3895913887 ps
T87	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2288150994			Jul 31 08:22:32 PM PDT 24	Jul 31 08:27:15 PM PDT 24	2557955709 ps
T93	/workspace/coverage/default/0.chip_sw_example_manufacturer.1604266815			Jul 31 08:12:37 PM PDT 24	Jul 31 08:15:18 PM PDT 24	2591090410 ps
T47	/workspace/coverage/default/2.rom_e2e_static_critical.4113416531			Jul 31 08:41:03 PM PDT 24	Jul 31 10:01:18 PM PDT 24	16559387944 ps
T94	/workspace/coverage/default/0.chip_plic_all_irqs_10.1073630544			Jul 31 08:16:31 PM PDT 24	Jul 31 08:25:03 PM PDT 24	3828267894 ps
T15	/workspace/coverage/default/0.chip_sw_gpio.2353681268			Jul 31 08:11:58 PM PDT 24	Jul 31 08:20:40 PM PDT 24	4220607275 ps
T205	/workspace/coverage/default/2.chip_plic_all_irqs_0.1913934836			Jul 31 08:33:28 PM PDT 24	Jul 31 08:54:30 PM PDT 24	6465895426 ps
T48	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1242322521			Jul 31 08:20:37 PM PDT 24	Jul 31 09:21:39 PM PDT 24	14986125264 ps
T7	/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.2706553332			Jul 31 08:20:12 PM PDT 24	Jul 31 09:02:38 PM PDT 24	26290506824 ps
T194	/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3605496226			Jul 31 08:25:48 PM PDT 24	Jul 31 08:31:30 PM PDT 24	3613387391 ps
T50	/workspace/coverage/default/0.chip_tap_straps_dev.2400567761			Jul 31 08:13:41 PM PDT 24	Jul 31 08:16:30 PM PDT 24	2435882444 ps
T259	/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3368529697			Jul 31 08:42:18 PM PDT 24	Jul 31 08:48:16 PM PDT 24	4003955252 ps
T129	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.636547164			Jul 31 08:32:48 PM PDT 24	Jul 31 08:37:53 PM PDT 24	2676588592 ps
T49	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.3451915339			Jul 31 08:22:29 PM PDT 24	Jul 31 09:21:42 PM PDT 24	15417190556 ps
T261	/workspace/coverage/default/0.chip_sw_aon_timer_irq.425285052			Jul 31 08:15:57 PM PDT 24	Jul 31 08:21:41 PM PDT 24	4087344000 ps
T16	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1662747407			Jul 31 08:27:28 PM PDT 24	Jul 31 08:37:54 PM PDT 24	4456993280 ps
T260	/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2770630706			Jul 31 08:45:15 PM PDT 24	Jul 31 08:52:57 PM PDT 24	4065221456 ps
T130	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.3814370585			Jul 31 08:31:25 PM PDT 24	Jul 31 08:37:09 PM PDT 24	3529614095 ps
T305	/workspace/coverage/default/0.chip_sw_aes_entropy.1604056351			Jul 31 08:13:28 PM PDT 24	Jul 31 08:17:09 PM PDT 24	2256827380 ps
T139	/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2895905793			Jul 31 08:25:36 PM PDT 24	Jul 31 08:34:35 PM PDT 24	6103873068 ps
T64	/workspace/coverage/default/99.chip_sw_all_escalation_resets.1996493859			Jul 31 08:45:01 PM PDT 24	Jul 31 08:53:39 PM PDT 24	4477398616 ps
T516	/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.2445001979			Jul 31 08:41:51 PM PDT 24	Jul 31 08:47:33 PM PDT 24	3669625652 ps
T8	/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2026676754			Jul 31 08:37:49 PM PDT 24	Jul 31 08:54:03 PM PDT 24	12567796282 ps
T185	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.166190195			Jul 31 08:31:14 PM PDT 24	Jul 31 08:51:16 PM PDT 24	7789950804 ps
T191	/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.768814138			Jul 31 08:14:20 PM PDT 24	Jul 31 08:22:02 PM PDT 24	4972116386 ps
T21	/workspace/coverage/default/1.chip_jtag_csr_rw.726697243			Jul 31 08:17:04 PM PDT 24	Jul 31 08:42:03 PM PDT 24	12443660613 ps
T248	/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.3193818854			Jul 31 08:31:45 PM PDT 24	Jul 31 08:40:47 PM PDT 24	3185309388 ps
T22	/workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2171638971			Jul 31 08:21:17 PM PDT 24	Jul 31 08:27:44 PM PDT 24	3567843140 ps
T293	/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1994237463			Jul 31 08:34:37 PM PDT 24	Jul 31 08:46:10 PM PDT 24	3894157652 ps
T143	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.2383645107			Jul 31 08:15:59 PM PDT 24	Jul 31 08:26:16 PM PDT 24	6687296840 ps
T192	/workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.3103925343			Jul 31 08:23:14 PM PDT 24	Jul 31 08:37:19 PM PDT 24	7682908006 ps
T294	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.138191705			Jul 31 08:39:46 PM PDT 24	Jul 31 08:46:05 PM PDT 24	4410973560 ps
T63	/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.1780411666			Jul 31 08:11:47 PM PDT 24	Jul 31 08:13:44 PM PDT 24	2925477984 ps
T133	/workspace/coverage/default/0.rom_volatile_raw_unlock.2339163091			Jul 31 08:15:28 PM PDT 24	Jul 31 08:17:14 PM PDT 24	2493922088 ps
T295	/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1862375071			Jul 31 08:15:21 PM PDT 24	Jul 31 08:20:25 PM PDT 24	3287968528 ps
T140	/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1135182278			Jul 31 08:22:19 PM PDT 24	Jul 31 08:43:12 PM PDT 24	6982874630 ps
T141	/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2047417479			Jul 31 08:24:08 PM PDT 24	Jul 31 08:45:01 PM PDT 24	6580397822 ps
T65	/workspace/coverage/default/94.chip_sw_all_escalation_resets.1899689871			Jul 31 08:46:56 PM PDT 24	Jul 31 08:58:11 PM PDT 24	5843979606 ps
T235	/workspace/coverage/default/1.rom_keymgr_functest.2177389790			Jul 31 08:27:03 PM PDT 24	Jul 31 08:34:50 PM PDT 24	4826292196 ps
T227	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1031852652			Jul 31 08:20:51 PM PDT 24	Jul 31 08:40:05 PM PDT 24	8057271948 ps
T66	/workspace/coverage/default/7.chip_sw_all_escalation_resets.2055508083			Jul 31 08:40:18 PM PDT 24	Jul 31 08:50:48 PM PDT 24	5173875102 ps
T249	/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1290738197			Jul 31 08:16:47 PM PDT 24	Jul 31 08:29:26 PM PDT 24	6249100636 ps
T270	/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1814947992			Jul 31 08:43:22 PM PDT 24	Jul 31 08:49:24 PM PDT 24	3583145324 ps
T271	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2248105388			Jul 31 08:43:43 PM PDT 24	Jul 31 08:49:23 PM PDT 24	4063191944 ps
T71	/workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2441958001			Jul 31 08:17:45 PM PDT 24	Jul 31 08:52:41 PM PDT 24	11149695184 ps
T272	/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.2742823463			Jul 31 08:24:05 PM PDT 24	Jul 31 08:28:29 PM PDT 24	2663826920 ps
T171	/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.2527875417			Jul 31 08:47:49 PM PDT 24	Jul 31 08:54:33 PM PDT 24	3455208550 ps
T44	/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2108259204			Jul 31 08:31:58 PM PDT 24	Jul 31 09:25:28 PM PDT 24	14781325316 ps
T70	/workspace/coverage/default/0.chip_sw_alert_handler_escalation.2950937588			Jul 31 08:17:33 PM PDT 24	Jul 31 08:28:19 PM PDT 24	5707570920 ps
T273	/workspace/coverage/default/75.chip_sw_all_escalation_resets.872155379			Jul 31 08:46:17 PM PDT 24	Jul 31 08:54:44 PM PDT 24	5414416060 ps
T274	/workspace/coverage/default/97.chip_sw_all_escalation_resets.3632301908			Jul 31 08:47:24 PM PDT 24	Jul 31 08:55:53 PM PDT 24	5000656470 ps
T519	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2059830649			Jul 31 08:35:49 PM PDT 24	Jul 31 08:46:14 PM PDT 24	6884689128 ps
T38	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2263221571			Jul 31 08:14:05 PM PDT 24	Jul 31 08:22:32 PM PDT 24	5100970564 ps
T901	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2273990827			Jul 31 08:27:30 PM PDT 24	Jul 31 08:32:00 PM PDT 24	3063746528 ps
T184	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.435509977			Jul 31 08:13:21 PM PDT 24	Jul 31 08:24:21 PM PDT 24	5888998814 ps
T724	/workspace/coverage/default/2.chip_sw_aes_idle.3877609533			Jul 31 08:32:02 PM PDT 24	Jul 31 08:35:36 PM PDT 24	2854339714 ps
T67	/workspace/coverage/default/3.chip_tap_straps_testunlock0.2081580074			Jul 31 08:36:50 PM PDT 24	Jul 31 08:51:43 PM PDT 24	7915946428 ps
T758	/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.751082165			Jul 31 08:25:44 PM PDT 24	Jul 31 08:49:00 PM PDT 24	5368071800 ps
T353	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2252535982			Jul 31 08:18:19 PM PDT 24	Jul 31 08:26:49 PM PDT 24	4396220686 ps
T178	/workspace/coverage/default/47.chip_sw_all_escalation_resets.1748374313			Jul 31 08:43:46 PM PDT 24	Jul 31 08:53:37 PM PDT 24	5815231004 ps
T134	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1842228672			Jul 31 08:39:07 PM PDT 24	Jul 31 08:59:39 PM PDT 24	8922307728 ps
T383	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2353107219			Jul 31 08:45:23 PM PDT 24	Jul 31 08:52:52 PM PDT 24	3382361674 ps
T131	/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3861191091			Jul 31 08:33:15 PM PDT 24	Jul 31 08:42:43 PM PDT 24	5023610078 ps
T342	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3561354576			Jul 31 08:17:33 PM PDT 24	Jul 31 08:20:48 PM PDT 24	2497475242 ps
T157	/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2433116832			Jul 31 08:25:56 PM PDT 24	Jul 31 08:29:41 PM PDT 24	2786527122 ps
T902	/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.3852063471			Jul 31 08:30:41 PM PDT 24	Jul 31 08:39:14 PM PDT 24	4133834714 ps
T364	/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3901083187			Jul 31 08:29:07 PM PDT 24	Jul 31 09:11:55 PM PDT 24	23653120497 ps
T72	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.2919614188			Jul 31 08:17:58 PM PDT 24	Jul 31 08:50:13 PM PDT 24	10486650582 ps
T179	/workspace/coverage/default/36.chip_sw_all_escalation_resets.83941260			Jul 31 08:41:47 PM PDT 24	Jul 31 08:51:54 PM PDT 24	6214950640 ps
T903	/workspace/coverage/default/1.chip_sw_example_concurrency.1153151685			Jul 31 08:15:23 PM PDT 24	Jul 31 08:18:30 PM PDT 24	3036171448 ps
T12	/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1384417166			Jul 31 08:14:58 PM PDT 24	Jul 31 08:24:38 PM PDT 24	4631114895 ps
T520	/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.2149650585			Jul 31 08:26:32 PM PDT 24	Jul 31 08:32:13 PM PDT 24	3439022388 ps
T904	/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.573541975			Jul 31 08:14:50 PM PDT 24	Jul 31 08:37:07 PM PDT 24	7990413959 ps
T222	/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1952400336			Jul 31 08:38:51 PM PDT 24	Jul 31 09:00:19 PM PDT 24	8386735270 ps
T17	/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.1868165743			Jul 31 08:17:13 PM PDT 24	Jul 31 08:27:33 PM PDT 24	4470003800 ps
T905	/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1019204314			Jul 31 08:37:28 PM PDT 24	Jul 31 08:41:47 PM PDT 24	2233545192 ps
T27	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3597955300			Jul 31 08:28:28 PM PDT 24	Jul 31 08:34:22 PM PDT 24	3032577780 ps
T113	/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3957886819			Jul 31 08:12:24 PM PDT 24	Jul 31 08:25:40 PM PDT 24	4516919184 ps
T114	/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.4032655569			Jul 31 08:44:23 PM PDT 24	Jul 31 08:51:14 PM PDT 24	4005003618 ps
T115	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.333826902			Jul 31 08:25:51 PM PDT 24	Jul 31 08:33:04 PM PDT 24	3777795078 ps
T116	/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4162564142			Jul 31 08:28:10 PM PDT 24	Jul 31 08:34:19 PM PDT 24	3594543504 ps
T117	/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.177716662			Jul 31 08:36:13 PM PDT 24	Jul 31 08:48:39 PM PDT 24	3870492178 ps
T118	/workspace/coverage/default/0.chip_sw_all_escalation_resets.1387118045			Jul 31 08:13:30 PM PDT 24	Jul 31 08:25:40 PM PDT 24	5040614440 ps
T73	/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1835014715			Jul 31 08:27:29 PM PDT 24	Jul 31 08:36:56 PM PDT 24	4849635269 ps
T119	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1269351609			Jul 31 08:14:30 PM PDT 24	Jul 31 08:19:14 PM PDT 24	3034460087 ps
T82	/workspace/coverage/default/2.chip_jtag_mem_access.2916946591			Jul 31 08:26:27 PM PDT 24	Jul 31 08:55:03 PM PDT 24	13456658696 ps
T142	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3436072647			Jul 31 08:12:05 PM PDT 24	Jul 31 08:22:34 PM PDT 24	7892678017 ps
T45	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1435320309			Jul 31 08:19:51 PM PDT 24	Jul 31 10:01:32 PM PDT 24	23845384464 ps
T62	/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2263163368			Jul 31 08:39:33 PM PDT 24	Jul 31 08:54:36 PM PDT 24	9089864702 ps
T375	/workspace/coverage/default/53.chip_sw_all_escalation_resets.3102336739			Jul 31 08:44:43 PM PDT 24	Jul 31 08:54:53 PM PDT 24	4371120904 ps
T193	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.302848727			Jul 31 08:14:31 PM PDT 24	Jul 31 08:26:45 PM PDT 24	4733218400 ps
T195	/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.2279361443			Jul 31 08:32:29 PM PDT 24	Jul 31 08:42:57 PM PDT 24	8595831557 ps
T135	/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3251038420			Jul 31 08:38:00 PM PDT 24	Jul 31 08:47:31 PM PDT 24	3882827569 ps
T440	/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.553086638			Jul 31 08:34:40 PM PDT 24	Jul 31 08:40:04 PM PDT 24	3738852878 ps
T386	/workspace/coverage/default/2.rom_e2e_asm_init_prod.4240827979			Jul 31 08:40:50 PM PDT 24	Jul 31 09:31:03 PM PDT 24	15446157249 ps
T441	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.467201741			Jul 31 08:23:19 PM PDT 24	Jul 31 08:27:31 PM PDT 24	2663268882 ps
T713	/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.695767751			Jul 31 08:41:40 PM PDT 24	Jul 31 08:48:07 PM PDT 24	3531371932 ps
T347	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.578931635			Jul 31 08:14:12 PM PDT 24	Jul 31 09:16:01 PM PDT 24	37029883833 ps
T132	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2816234839			Jul 31 08:26:38 PM PDT 24	Jul 31 08:36:41 PM PDT 24	5293898360 ps
T384	/workspace/coverage/default/85.chip_sw_all_escalation_resets.947520207			Jul 31 08:45:17 PM PDT 24	Jul 31 08:55:18 PM PDT 24	4447124918 ps
T357	/workspace/coverage/default/89.chip_sw_all_escalation_resets.515309020			Jul 31 08:45:20 PM PDT 24	Jul 31 08:55:37 PM PDT 24	5348600304 ps
T124	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2531927026			Jul 31 08:36:01 PM PDT 24	Jul 31 09:30:35 PM PDT 24	22325498959 ps
T403	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2093392054			Jul 31 08:23:09 PM PDT 24	Jul 31 09:18:47 PM PDT 24	12109634488 ps
T906	/workspace/coverage/default/1.chip_sw_example_rom.3699977381			Jul 31 08:18:19 PM PDT 24	Jul 31 08:20:44 PM PDT 24	2506410270 ps
T23	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.344491411			Jul 31 08:15:45 PM PDT 24	Jul 31 09:10:03 PM PDT 24	20005976652 ps
T907	/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3438432020			Jul 31 08:19:59 PM PDT 24	Jul 31 08:27:48 PM PDT 24	5182400471 ps
T223	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2743233544			Jul 31 08:39:10 PM PDT 24	Jul 31 09:17:33 PM PDT 24	13104903800 ps
T369	/workspace/coverage/default/4.chip_tap_straps_prod.1976982765			Jul 31 08:37:04 PM PDT 24	Jul 31 08:40:04 PM PDT 24	2934699110 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.4196773509			Jul 31 08:21:47 PM PDT 24	Jul 31 10:01:01 PM PDT 24	23736678350 ps
T309	/workspace/coverage/default/71.chip_sw_all_escalation_resets.3899844883			Jul 31 08:45:08 PM PDT 24	Jul 31 08:53:59 PM PDT 24	4604017032 ps
T908	/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.487232869			Jul 31 08:18:28 PM PDT 24	Jul 31 08:35:13 PM PDT 24	5301554775 ps
T176	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.798478627			Jul 31 08:30:13 PM PDT 24	Jul 31 10:10:19 PM PDT 24	51672778402 ps
T180	/workspace/coverage/default/93.chip_sw_all_escalation_resets.3106195202			Jul 31 08:46:07 PM PDT 24	Jul 31 08:56:12 PM PDT 24	5881136784 ps
T18	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2430908654			Jul 31 08:33:38 PM PDT 24	Jul 31 09:01:09 PM PDT 24	22485228392 ps
T411	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1328511072			Jul 31 08:16:36 PM PDT 24	Jul 31 08:24:18 PM PDT 24	8034770186 ps
T393	/workspace/coverage/default/33.chip_sw_all_escalation_resets.857353669			Jul 31 08:41:50 PM PDT 24	Jul 31 08:50:39 PM PDT 24	5937225512 ps
T88	/workspace/coverage/default/2.chip_sw_alert_handler_entropy.3653325495			Jul 31 08:31:43 PM PDT 24	Jul 31 08:36:07 PM PDT 24	3777182011 ps
T228	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.2926490704			Jul 31 08:13:22 PM PDT 24	Jul 31 09:04:54 PM PDT 24	12781911800 ps
T392	/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1545971089			Jul 31 08:26:23 PM PDT 24	Jul 31 08:31:52 PM PDT 24	2934547052 ps
T177	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2599967122			Jul 31 08:19:23 PM PDT 24	Jul 31 09:04:47 PM PDT 24	10435679288 ps
T275	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.793518008			Jul 31 08:24:33 PM PDT 24	Jul 31 09:29:45 PM PDT 24	15300960375 ps
T28	/workspace/coverage/default/1.chip_sw_gpio_smoketest.412627464			Jul 31 08:28:01 PM PDT 24	Jul 31 08:33:45 PM PDT 24	3594716919 ps
T326	/workspace/coverage/default/51.chip_sw_all_escalation_resets.3280810574			Jul 31 08:42:37 PM PDT 24	Jul 31 08:53:18 PM PDT 24	4723340704 ps
T726	/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3922591306			Jul 31 08:34:15 PM PDT 24	Jul 31 08:50:09 PM PDT 24	7519730468 ps
T262	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.532152206			Jul 31 08:17:38 PM PDT 24	Jul 31 08:27:09 PM PDT 24	5774481504 ps
T823	/workspace/coverage/default/54.chip_sw_all_escalation_resets.2507446875			Jul 31 08:44:42 PM PDT 24	Jul 31 08:53:42 PM PDT 24	4084423928 ps
T687	/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2003931047			Jul 31 08:15:02 PM PDT 24	Jul 31 08:26:44 PM PDT 24	5830112520 ps
T365	/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1980433057			Jul 31 08:19:15 PM PDT 24	Jul 31 08:25:03 PM PDT 24	3615849176 ps
T229	/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2722687715			Jul 31 08:31:31 PM PDT 24	Jul 31 09:30:43 PM PDT 24	12416924492 ps
T909	/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.3171791572			Jul 31 08:24:54 PM PDT 24	Jul 31 08:32:26 PM PDT 24	3869007112 ps
T910	/workspace/coverage/default/0.chip_sw_flash_ctrl_access.620853212			Jul 31 08:14:01 PM PDT 24	Jul 31 08:31:37 PM PDT 24	5389942746 ps
T250	/workspace/coverage/default/88.chip_sw_all_escalation_resets.856580303			Jul 31 08:46:52 PM PDT 24	Jul 31 08:54:02 PM PDT 24	5412450640 ps
T762	/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.223740767			Jul 31 08:44:20 PM PDT 24	Jul 31 08:50:29 PM PDT 24	3709703240 ps
T170	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3528077914			Jul 31 08:32:12 PM PDT 24	Aug 01 12:02:13 AM PDT 24	255332411774 ps
T451	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.457501108			Jul 31 08:13:36 PM PDT 24	Jul 31 08:33:01 PM PDT 24	7064689864 ps
T741	/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3777796749			Jul 31 08:42:37 PM PDT 24	Jul 31 08:51:54 PM PDT 24	3654521480 ps
T911	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.695276411			Jul 31 08:20:09 PM PDT 24	Jul 31 08:27:05 PM PDT 24	5191232000 ps
T912	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.4209334232			Jul 31 08:23:34 PM PDT 24	Jul 31 08:34:35 PM PDT 24	4160886744 ps
T913	/workspace/coverage/default/0.rom_e2e_static_critical.2914073616			Jul 31 08:24:47 PM PDT 24	Jul 31 09:39:09 PM PDT 24	17207835224 ps
T75	/workspace/coverage/default/1.chip_tap_straps_dev.1067200243			Jul 31 08:24:36 PM PDT 24	Jul 31 08:45:24 PM PDT 24	11302774540 ps
T370	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2940109746			Jul 31 08:16:27 PM PDT 24	Jul 31 08:23:33 PM PDT 24	5120338972 ps
T136	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.568468580			Jul 31 08:18:36 PM PDT 24	Jul 31 08:31:15 PM PDT 24	5219983668 ps
T256	/workspace/coverage/default/1.chip_sw_plic_sw_irq.1167026615			Jul 31 08:25:32 PM PDT 24	Jul 31 08:30:08 PM PDT 24	2783009524 ps
T914	/workspace/coverage/default/0.rom_e2e_asm_init_rma.2778155373			Jul 31 08:24:33 PM PDT 24	Jul 31 09:27:45 PM PDT 24	14470582851 ps
T158	/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.466202820			Jul 31 08:29:45 PM PDT 24	Jul 31 08:39:20 PM PDT 24	9672440778 ps
T226	/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2912942393			Jul 31 08:44:24 PM PDT 24	Jul 31 09:06:56 PM PDT 24	8023476816 ps
T225	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4264414519			Jul 31 08:17:02 PM PDT 24	Jul 31 08:31:22 PM PDT 24	4867807620 ps
T915	/workspace/coverage/default/2.rom_e2e_asm_init_rma.2951380815			Jul 31 08:40:27 PM PDT 24	Jul 31 09:28:50 PM PDT 24	15195392963 ps
T230	/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2185346936			Jul 31 08:22:29 PM PDT 24	Jul 31 08:44:12 PM PDT 24	6875944712 ps
T55	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3702048906			Jul 31 08:12:41 PM PDT 24	Jul 31 08:18:28 PM PDT 24	3508109821 ps
T83	/workspace/coverage/default/1.chip_jtag_mem_access.3890376473			Jul 31 08:17:03 PM PDT 24	Jul 31 08:45:06 PM PDT 24	14381869490 ps
T120	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4039014290			Jul 31 08:34:16 PM PDT 24	Jul 31 08:40:38 PM PDT 24	3509429360 ps
T264	/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.477503748			Jul 31 08:38:26 PM PDT 24	Jul 31 09:40:19 PM PDT 24	17457623016 ps
T19	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1753782912			Jul 31 08:16:08 PM PDT 24	Jul 31 08:39:24 PM PDT 24	25403853672 ps
T137	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.864797874			Jul 31 08:24:31 PM PDT 24	Jul 31 08:37:44 PM PDT 24	4838861656 ps
T714	/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4026745099			Jul 31 08:29:30 PM PDT 24	Jul 31 08:47:03 PM PDT 24	5704490221 ps
T288	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3594567242			Jul 31 08:24:37 PM PDT 24	Jul 31 08:33:55 PM PDT 24	5075232026 ps
T715	/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.757492433			Jul 31 08:27:45 PM PDT 24	Jul 31 08:30:58 PM PDT 24	3099592978 ps
T716	/workspace/coverage/default/73.chip_sw_all_escalation_resets.1131086348			Jul 31 08:43:49 PM PDT 24	Jul 31 08:56:08 PM PDT 24	5198330232 ps
T231	/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3614547481			Jul 31 08:22:23 PM PDT 24	Jul 31 08:44:02 PM PDT 24	7394173612 ps
T717	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2782357324			Jul 31 08:46:35 PM PDT 24	Jul 31 08:53:32 PM PDT 24	3855471432 ps
T916	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3662231425			Jul 31 08:17:34 PM PDT 24	Jul 31 08:21:48 PM PDT 24	2833343464 ps
T234	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2966457713			Jul 31 08:14:56 PM PDT 24	Jul 31 08:42:09 PM PDT 24	9033349928 ps
T917	/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.4293556644			Jul 31 08:34:40 PM PDT 24	Jul 31 08:41:48 PM PDT 24	2869594000 ps
T918	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1165566721			Jul 31 08:33:50 PM PDT 24	Jul 31 08:45:07 PM PDT 24	6196564234 ps
T919	/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.674395229			Jul 31 08:16:46 PM PDT 24	Jul 31 08:35:36 PM PDT 24	5969111024 ps
T328	/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1980231882			Jul 31 08:39:31 PM PDT 24	Jul 31 08:49:28 PM PDT 24	3797029604 ps
T239	/workspace/coverage/default/2.chip_sw_flash_init.2431794803			Jul 31 08:28:22 PM PDT 24	Jul 31 08:57:33 PM PDT 24	17510042344 ps
T257	/workspace/coverage/default/0.chip_sw_plic_sw_irq.2004238420			Jul 31 08:14:02 PM PDT 24	Jul 31 08:18:59 PM PDT 24	3155243160 ps
T232	/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.4102839858			Jul 31 08:32:07 PM PDT 24	Jul 31 08:56:36 PM PDT 24	7940903530 ps
T78	/workspace/coverage/default/0.chip_jtag_csr_rw.1897816270			Jul 31 08:06:44 PM PDT 24	Jul 31 08:16:03 PM PDT 24	6609439744 ps
T920	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.273185127			Jul 31 08:15:53 PM PDT 24	Jul 31 08:30:17 PM PDT 24	7368254860 ps
T263	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.2523930537			Jul 31 08:16:12 PM PDT 24	Jul 31 08:56:50 PM PDT 24	11134943925 ps
T310	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2960250423			Jul 31 08:14:09 PM PDT 24	Jul 31 08:28:11 PM PDT 24	10254015024 ps
T92	/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2684740195			Jul 31 08:27:38 PM PDT 24	Jul 31 11:30:30 PM PDT 24	59480544800 ps
T224	/workspace/coverage/default/2.chip_sw_power_sleep_load.413306769			Jul 31 08:39:47 PM PDT 24	Jul 31 08:50:46 PM PDT 24	11238089286 ps
T404	/workspace/coverage/default/12.chip_sw_all_escalation_resets.912216124			Jul 31 08:41:16 PM PDT 24	Jul 31 08:51:31 PM PDT 24	5795470556 ps
T312	/workspace/coverage/default/95.chip_sw_all_escalation_resets.2002082150			Jul 31 08:48:29 PM PDT 24	Jul 31 08:57:59 PM PDT 24	5284180818 ps
T319	/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4272293816			Jul 31 08:16:15 PM PDT 24	Jul 31 09:05:40 PM PDT 24	28558416062 ps
T320	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1863519091			Jul 31 08:38:17 PM PDT 24	Jul 31 08:49:13 PM PDT 24	4740927920 ps
T321	/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2622378219			Jul 31 08:15:59 PM PDT 24	Jul 31 08:20:08 PM PDT 24	3303646920 ps
T322	/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3853885999			Jul 31 08:26:28 PM PDT 24	Jul 31 08:32:15 PM PDT 24	3638148152 ps
T323	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3615138785			Jul 31 08:33:53 PM PDT 24	Jul 31 08:38:15 PM PDT 24	3231399994 ps
T276	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1820644889			Jul 31 08:24:32 PM PDT 24	Jul 31 09:22:48 PM PDT 24	14212045416 ps
T324	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3094369968			Jul 31 08:22:36 PM PDT 24	Jul 31 09:38:04 PM PDT 24	15342579336 ps
T215	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.2104138896			Jul 31 08:32:32 PM PDT 24	Jul 31 08:39:16 PM PDT 24	3755456243 ps
T325	/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1212553968			Jul 31 08:33:37 PM PDT 24	Jul 31 08:45:16 PM PDT 24	6481951768 ps
T394	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1169178261			Jul 31 08:32:20 PM PDT 24	Jul 31 08:54:53 PM PDT 24	7002571208 ps
T712	/workspace/coverage/default/42.chip_sw_all_escalation_resets.3612251616			Jul 31 08:43:31 PM PDT 24	Jul 31 08:52:29 PM PDT 24	4188075192 ps
T186	/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.1008259620			Jul 31 08:18:49 PM PDT 24	Jul 31 08:31:46 PM PDT 24	10060067200 ps
T921	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4219154354			Jul 31 08:26:58 PM PDT 24	Jul 31 08:47:04 PM PDT 24	7232161167 ps
T922	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.669206380			Jul 31 08:28:47 PM PDT 24	Jul 31 08:41:25 PM PDT 24	4787276840 ps
T923	/workspace/coverage/default/2.chip_sw_hmac_smoketest.1470146936			Jul 31 08:36:35 PM PDT 24	Jul 31 08:43:11 PM PDT 24	4180813110 ps
T363	/workspace/coverage/default/56.chip_sw_all_escalation_resets.1132354271			Jul 31 08:44:18 PM PDT 24	Jul 31 08:54:10 PM PDT 24	5227357844 ps
T744	/workspace/coverage/default/83.chip_sw_all_escalation_resets.902426827			Jul 31 08:45:18 PM PDT 24	Jul 31 08:55:40 PM PDT 24	5197969876 ps
T517	/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.4193515472			Jul 31 08:31:52 PM PDT 24	Jul 31 08:46:15 PM PDT 24	4626984056 ps
T699	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1703359705			Jul 31 08:13:44 PM PDT 24	Jul 31 08:20:14 PM PDT 24	2587055680 ps
T385	/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1134911335			Jul 31 08:43:03 PM PDT 24	Jul 31 08:49:29 PM PDT 24	3878218276 ps
T144	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4063283620			Jul 31 08:16:04 PM PDT 24	Jul 31 08:25:25 PM PDT 24	5283317326 ps
T20	/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.2925905924			Jul 31 08:18:54 PM PDT 24	Jul 31 08:28:37 PM PDT 24	5804111120 ps
T89	/workspace/coverage/default/57.chip_sw_all_escalation_resets.3239907579			Jul 31 08:43:57 PM PDT 24	Jul 31 08:54:54 PM PDT 24	6237687338 ps
T100	/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3886416899			Jul 31 08:21:07 PM PDT 24	Jul 31 08:35:27 PM PDT 24	5768531292 ps
T101	/workspace/coverage/default/1.chip_sw_aes_masking_off.685488530			Jul 31 08:22:51 PM PDT 24	Jul 31 08:29:13 PM PDT 24	3484343733 ps
T102	/workspace/coverage/default/86.chip_sw_all_escalation_resets.570483357			Jul 31 08:46:13 PM PDT 24	Jul 31 08:59:05 PM PDT 24	5207252716 ps
T103	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4132587122			Jul 31 08:39:37 PM PDT 24	Jul 31 09:27:41 PM PDT 24	11308979381 ps
T104	/workspace/coverage/default/70.chip_sw_all_escalation_resets.848971623			Jul 31 08:43:40 PM PDT 24	Jul 31 08:51:39 PM PDT 24	5181061260 ps
T105	/workspace/coverage/default/0.rom_e2e_smoke.3613485836			Jul 31 08:19:33 PM PDT 24	Jul 31 09:26:14 PM PDT 24	14364129526 ps
T106	/workspace/coverage/default/68.chip_sw_all_escalation_resets.3553066846			Jul 31 08:43:48 PM PDT 24	Jul 31 08:52:29 PM PDT 24	5112800908 ps
T107	/workspace/coverage/default/49.chip_sw_all_escalation_resets.3369236669			Jul 31 08:44:08 PM PDT 24	Jul 31 08:56:41 PM PDT 24	4312273744 ps
T108	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.990345216			Jul 31 08:23:45 PM PDT 24	Jul 31 08:34:04 PM PDT 24	5269759500 ps
T299	/workspace/coverage/default/11.chip_sw_all_escalation_resets.4163696096			Jul 31 08:40:02 PM PDT 24	Jul 31 08:49:56 PM PDT 24	4865669270 ps
T300	/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2994374485			Jul 31 08:31:58 PM PDT 24	Jul 31 08:36:24 PM PDT 24	2910711956 ps
T301	/workspace/coverage/default/58.chip_sw_all_escalation_resets.1270464150			Jul 31 08:42:28 PM PDT 24	Jul 31 08:51:49 PM PDT 24	5971080760 ps
T360	/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.210239278			Jul 31 08:32:37 PM PDT 24	Jul 31 08:36:48 PM PDT 24	2947695372 ps
T358	/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3446917322			Jul 31 08:21:49 PM PDT 24	Jul 31 08:32:22 PM PDT 24	18119790328 ps
T247	/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.615706036			Jul 31 08:42:31 PM PDT 24	Jul 31 08:48:02 PM PDT 24	3586919980 ps
T924	/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3117900416			Jul 31 08:12:20 PM PDT 24	Jul 31 09:05:05 PM PDT 24	13678947704 ps
T739	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3455834321			Jul 31 08:41:48 PM PDT 24	Jul 31 08:47:41 PM PDT 24	4066726522 ps
T686	/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.679305587			Jul 31 08:20:28 PM PDT 24	Jul 31 08:45:37 PM PDT 24	11364363666 ps
T162	/workspace/coverage/default/0.chip_sw_otbn_smoketest.359482255			Jul 31 08:19:33 PM PDT 24	Jul 31 08:58:59 PM PDT 24	10074797494 ps
T753	/workspace/coverage/default/40.chip_sw_all_escalation_resets.3478128520			Jul 31 08:44:14 PM PDT 24	Jul 31 08:54:42 PM PDT 24	4931702024 ps
T356	/workspace/coverage/default/72.chip_sw_all_escalation_resets.2760559688			Jul 31 08:43:40 PM PDT 24	Jul 31 08:52:46 PM PDT 24	5747233026 ps
T167	/workspace/coverage/default/1.chip_plic_all_irqs_10.1648736813			Jul 31 08:23:22 PM PDT 24	Jul 31 08:31:29 PM PDT 24	3477030934 ps
T821	/workspace/coverage/default/65.chip_sw_all_escalation_resets.3752240179			Jul 31 08:43:22 PM PDT 24	Jul 31 08:53:08 PM PDT 24	5906961340 ps
T138	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1164556158			Jul 31 08:35:50 PM PDT 24	Jul 31 08:46:22 PM PDT 24	3663982416 ps
T925	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1231273623			Jul 31 08:21:25 PM PDT 24	Jul 31 08:55:05 PM PDT 24	9107582520 ps
T332	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1416470227			Jul 31 08:28:37 PM PDT 24	Jul 31 08:44:26 PM PDT 24	5475424332 ps
T340	/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3670088881			Jul 31 08:41:35 PM PDT 24	Jul 31 08:51:26 PM PDT 24	4330458208 ps
T442	/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1766157152			Jul 31 08:14:54 PM PDT 24	Jul 31 08:19:48 PM PDT 24	2824188192 ps
T277	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.978152479			Jul 31 08:25:22 PM PDT 24	Jul 31 09:32:32 PM PDT 24	14549715972 ps
T253	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1207776346			Jul 31 08:45:30 PM PDT 24	Jul 31 08:55:35 PM PDT 24	4735977528 ps
T242	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.500947711			Jul 31 08:12:59 PM PDT 24	Jul 31 10:03:11 PM PDT 24	47295816297 ps
T763	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2927499801			Jul 31 08:43:08 PM PDT 24	Jul 31 08:50:09 PM PDT 24	4186141152 ps
T405	/workspace/coverage/default/2.chip_sw_kmac_app_rom.351012987			Jul 31 08:36:57 PM PDT 24	Jul 31 08:39:58 PM PDT 24	2960934812 ps
T727	/workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.3539367470			Jul 31 08:19:04 PM PDT 24	Jul 31 08:57:55 PM PDT 24	32302042110 ps
T56	/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3624825305			Jul 31 08:29:20 PM PDT 24	Jul 31 08:34:06 PM PDT 24	3396982344 ps
T759	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.863991798			Jul 31 08:43:34 PM PDT 24	Jul 31 08:50:34 PM PDT 24	3874485190 ps
T926	/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2847635712			Jul 31 08:13:39 PM PDT 24	Jul 31 08:21:34 PM PDT 24	6564758078 ps
T927	/workspace/coverage/default/1.chip_sw_aes_smoketest.822789066			Jul 31 08:27:22 PM PDT 24	Jul 31 08:32:31 PM PDT 24	3152322798 ps
T928	/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4278729473			Jul 31 08:24:10 PM PDT 24	Jul 31 08:33:16 PM PDT 24	4070810320 ps
T24	/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1884067119			Jul 31 08:13:45 PM PDT 24	Jul 31 10:06:44 PM PDT 24	31512081720 ps
T929	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2222567339			Jul 31 08:25:47 PM PDT 24	Jul 31 08:37:43 PM PDT 24	7854066020 ps
T826	/workspace/coverage/default/80.chip_sw_all_escalation_resets.1341940106			Jul 31 08:47:33 PM PDT 24	Jul 31 08:55:14 PM PDT 24	4401402520 ps
T930	/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.324280965			Jul 31 08:34:07 PM PDT 24	Jul 31 08:46:06 PM PDT 24	3335834500 ps
T711	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.825946438			Jul 31 08:44:56 PM PDT 24	Jul 31 08:51:24 PM PDT 24	4452658588 ps