Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	486	1			T79	1		T444	3		T522	1
all_values[1]	509	1			T79	1		T80	1		T444	4
all_values[2]	504	1			T84	1		T444	1		T522	1
all_values[3]	501	1			T79	1		T444	3		T446	2
all_values[4]	513	1			T84	1		T444	6		T522	1
all_values[5]	518	1			T80	1		T444	2		T846	1
all_values[6]	517	1			T444	2		T522	2		T413	4
all_values[7]	519	1			T79	1		T84	1		T444	6
all_values[8]	501	1			T444	3		T446	1		T413	1
all_values[9]	482	1			T444	1		T446	1		T413	2
all_values[10]	490	1			T79	1		T444	3		T522	2
all_values[11]	477	1			T444	3		T413	1		T569	1
all_values[12]	485	1			T444	3		T413	3		T835	1
all_values[13]	519	1			T84	2		T444	5		T413	2
all_values[14]	510	1			T444	2		T522	1		T413	4
all_values[15]	513	1			T79	2		T80	1		T84	1
all_values[16]	505	1			T80	1		T444	1		T413	1
all_values[17]	497	1			T79	1		T444	4		T522	3
all_values[18]	537	1			T522	1		T413	1		T846	1
all_values[19]	500	1			T84	1		T444	2		T522	1
all_values[20]	510	1			T869	1		T685	7		T871	1
all_values[21]	512	1			T444	2		T522	1		T446	1
all_values[22]	550	1			T444	3		T413	1		T569	1
all_values[23]	517	1			T84	1		T444	2		T522	1
all_values[24]	476	1			T444	2		T522	1		T413	1
all_values[25]	483	1			T444	4		T522	1		T622	1
all_values[26]	485	1			T79	1		T84	1		T444	4
all_values[27]	523	1			T79	1		T80	1		T84	1
all_values[28]	502	1			T444	2		T522	1		T413	1
all_values[29]	504	1			T84	1		T444	2		T522	1
all_values[30]	492	1			T80	1		T84	1		T444	5
all_values[31]	496	1			T444	3		T569	1		T685	3
all_values[32]	535	1			T84	2		T444	2		T522	1
all_values[33]	498	1			T79	1		T80	1		T444	3
all_values[34]	496	1			T84	1		T444	1		T685	4
all_values[35]	498	1			T79	2		T444	3		T522	1
all_values[36]	479	1			T444	7		T446	1		T622	2
all_values[37]	494	1			T79	1		T84	3		T444	6
all_values[38]	534	1			T84	2		T444	3		T413	2
all_values[39]	516	1			T444	1		T522	1		T413	1
all_values[40]	531	1			T79	1		T84	1		T413	1
all_values[41]	503	1			T444	2		T413	2		T869	1
all_values[42]	486	1			T79	2		T444	5		T569	1
all_values[43]	457	1			T79	1		T444	1		T522	1
all_values[44]	479	1			T444	1		T522	2		T413	3
all_values[45]	539	1			T80	1		T84	1		T444	3
all_values[46]	514	1			T84	2		T444	3		T522	1
all_values[47]	529	1			T444	2		T522	2		T413	2
all_values[48]	507	1			T84	1		T444	3		T522	1
all_values[49]	502	1			T444	3		T413	1		T622	1