Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3652	1			T84	1		T444	22		T522	15
all_values[1]	3590	1			T84	2		T444	21		T522	13
all_values[2]	3704	1			T84	1		T444	24		T522	21
all_values[3]	3665	1			T84	2		T444	12		T522	12
all_values[4]	3763	1			T84	4		T444	23		T522	8
all_values[5]	3638	1			T84	7		T444	22		T522	15
all_values[6]	3574	1			T444	19		T522	14		T434	3
all_values[7]	3624	1			T84	5		T444	21		T522	9
all_values[8]	3717	1			T84	4		T444	27		T522	14
all_values[9]	3599	1			T84	5		T444	28		T522	14
all_values[10]	3699	1			T84	3		T444	26		T522	16
all_values[11]	3615	1			T84	3		T444	29		T522	10
all_values[12]	3662	1			T84	1		T444	26		T522	9
all_values[13]	3713	1			T84	6		T444	17		T522	16
all_values[14]	3683	1			T444	26		T522	8		T434	2
all_values[15]	3703	1			T84	2		T444	13		T522	15
all_values[16]	3618	1			T84	2		T444	16		T522	8
all_values[17]	3576	1			T84	1		T444	22		T522	12
all_values[18]	3616	1			T84	2		T444	25		T522	4
all_values[19]	3701	1			T84	5		T444	29		T522	16
all_values[20]	3710	1			T84	4		T444	19		T522	12
all_values[21]	3661	1			T84	2		T444	18		T522	17
all_values[22]	3606	1			T84	1		T444	29		T522	12
all_values[23]	3611	1			T84	2		T444	19		T522	10
all_values[24]	3571	1			T84	2		T444	20		T522	11
all_values[25]	3710	1			T84	5		T444	23		T522	11
all_values[26]	3757	1			T84	4		T444	21		T522	7
all_values[27]	3689	1			T84	3		T444	16		T522	23
all_values[28]	3711	1			T84	4		T444	21		T522	11
all_values[29]	3637	1			T84	4		T444	23		T522	15
all_values[30]	3656	1			T84	3		T444	22		T522	12
all_values[31]	3774	1			T84	2		T444	11		T522	11
all_values[32]	3630	1			T84	2		T444	19		T522	10
all_values[33]	3628	1			T84	3		T444	12		T522	16
all_values[34]	3591	1			T84	2		T444	24		T522	8
all_values[35]	3720	1			T84	2		T444	14		T522	10
all_values[36]	3608	1			T84	4		T444	23		T522	11
all_values[37]	3809	1			T84	3		T444	31		T522	18
all_values[38]	3558	1			T84	3		T444	17		T522	12
all_values[39]	3702	1			T84	3		T444	25		T522	7
all_values[40]	3661	1			T84	1		T444	18		T522	5
all_values[41]	3675	1			T84	4		T444	20		T522	12
all_values[42]	3548	1			T84	1		T444	22		T522	8
all_values[43]	3698	1			T84	3		T444	24		T522	13
all_values[44]	3650	1			T84	7		T444	21		T522	13
all_values[45]	3611	1			T84	2		T444	25		T522	12
all_values[46]	3708	1			T84	7		T444	22		T522	13
all_values[47]	3687	1			T84	1		T444	23		T522	13
all_values[48]	3535	1			T84	1		T444	10		T522	17
all_values[49]	3659	1			T84	5		T444	17		T522	17
all_values[50]	3571	1			T84	3		T444	27		T522	16
all_values[51]	3728	1			T84	3		T444	17		T522	6
all_values[52]	3552	1			T84	1		T444	32		T522	8
all_values[53]	3563	1			T84	3		T444	23		T522	7
all_values[54]	3570	1			T84	2		T444	25		T522	7
all_values[55]	3667	1			T84	1		T444	31		T522	13
all_values[56]	3599	1			T84	4		T444	31		T522	6
all_values[57]	3576	1			T84	4		T444	23		T522	14
all_values[58]	3774	1			T84	2		T444	19		T522	13
all_values[59]	3731	1			T84	4		T444	18		T522	6
all_values[60]	3651	1			T84	3		T444	29		T522	13
all_values[61]	3625	1			T84	1		T444	19		T522	13
all_values[62]	3662	1			T84	2		T444	19		T522	13
all_values[63]	3592	1			T84	3		T444	18		T522	10