Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.lc_ctrl_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	146643	1			T78	312		T79	6		T80	8
values[2]	11305	1			T78	2		T84	3		T214	4
values[3]	4499	1			T214	11		T450	1		T424	123
values[4]	2701	1			T214	11		T424	91		T436	1
values[5]	1586	1			T214	5		T424	54		T436	1
values[6]	935	1			T214	4		T424	41		T542	1
values[7]	651	1			T214	3		T424	11		T542	1
values[8]	555	1			T214	10		T424	8		T542	1
values[9]	465	1			T214	4		T424	9		T542	1
values[10]	358	1			T214	4		T424	8		T542	1
values[11]	318	1			T214	6		T424	7		T542	1
values[12]	304	1			T214	11		T542	1		T672	2
values[13]	253	1			T214	7		T542	1		T672	2
values[14]	282	1			T214	5		T542	1		T672	2
values[15]	271	1			T214	6		T542	1		T672	2
values[16]	277	1			T214	3		T542	1		T672	2
values[17]	330	1			T214	7		T542	1		T672	2
values[18]	313	1			T214	17		T542	1		T672	2
values[19]	273	1			T214	3		T542	1		T672	2
values[20]	241	1			T214	5		T542	1		T672	2
values[21]	274	1			T214	9		T542	1		T672	2
values[22]	277	1			T214	3		T542	1		T672	2
values[23]	254	1			T214	4		T542	1		T672	2
values[24]	284	1			T214	6		T542	1		T672	2
values[25]	266	1			T214	7		T542	1		T672	2
values[26]	296	1			T214	6		T542	1		T672	2
values[27]	317	1			T214	17		T542	1		T672	2
values[28]	273	1			T214	5		T542	1		T672	2
values[29]	282	1			T214	5		T542	1		T672	2
values[30]	248	1			T214	5		T542	1		T672	2
values[31]	237	1			T214	8		T542	1		T672	2
values[32]	226	1			T214	10		T542	1		T672	2
values[33]	241	1			T214	10		T542	1		T672	2
values[34]	275	1			T214	12		T542	1		T672	2
values[35]	262	1			T214	7		T542	1		T672	2
values[36]	270	1			T214	4		T542	1		T672	2
values[37]	235	1			T214	12		T542	1		T672	2
values[38]	255	1			T214	5		T542	1		T672	2
values[39]	222	1			T214	5		T542	1		T672	2
values[40]	213	1			T214	4		T542	1		T672	3
values[41]	229	1			T214	10		T542	1		T672	2
values[42]	213	1			T214	4		T542	1		T672	2
values[43]	251	1			T214	7		T542	1		T672	2
values[44]	255	1			T214	3		T542	1		T672	2
values[45]	259	1			T214	4		T542	1		T672	2
values[46]	224	1			T214	9		T542	1		T672	2
values[47]	217	1			T214	16		T542	1		T672	2
values[48]	208	1			T214	9		T542	1		T672	2
values[49]	208	1			T214	5		T542	1		T672	2
values[50]	231	1			T214	11		T542	1		T672	2
values[51]	205	1			T214	11		T542	1		T672	2
values[52]	214	1			T214	6		T542	1		T672	2
values[53]	215	1			T214	3		T542	1		T672	2
values[54]	213	1			T214	3		T542	1		T672	2
values[55]	250	1			T214	3		T542	1		T672	2
values[56]	211	1			T214	6		T542	1		T672	2
values[57]	207	1			T214	6		T542	1		T672	2
values[58]	179	1			T214	5		T542	1		T672	2
values[59]	177	1			T214	7		T542	1		T672	2
values[60]	163	1			T214	7		T542	1		T672	2
values[61]	157	1			T214	13		T542	1		T672	2
values[62]	198	1			T214	7		T542	1		T672	2
values[63]	188	1			T214	10		T542	1		T672	2
values[64]	207	1			T214	9		T542	1		T672	2
values[65]	197	1			T214	15		T542	1		T672	2
values[66]	141	1			T214	6		T542	1		T672	2
values[67]	193	1			T214	3		T542	1		T672	2
values[68]	178	1			T214	5		T542	1		T672	2
values[69]	168	1			T214	8		T542	1		T672	2
values[70]	160	1			T214	8		T542	1		T672	2
values[71]	140	1			T214	6		T542	1		T672	2
values[72]	136	1			T214	10		T542	1		T672	2
values[73]	163	1			T542	1		T672	3		T471	20
values[74]	160	1			T542	1		T672	2		T471	16
values[75]	146	1			T542	1		T672	2		T471	7
values[76]	144	1			T542	1		T672	2		T471	5
values[77]	153	1			T542	1		T672	2		T471	3
values[78]	149	1			T542	1		T672	3		T471	8
values[79]	121	1			T542	1		T672	2		T471	3
values[80]	94	1			T542	1		T672	2		T471	3
values[81]	107	1			T542	1		T672	2		T471	3
values[82]	121	1			T542	1		T672	2		T471	8
values[83]	120	1			T542	1		T672	3		T471	9
values[84]	127	1			T542	1		T672	6		T471	7
values[85]	108	1			T542	1		T672	3		T471	11
values[86]	120	1			T542	1		T672	6		T471	4
values[87]	121	1			T542	1		T672	6		T471	4
values[88]	115	1			T542	1		T672	7		T471	3
values[89]	87	1			T542	3		T672	2		T471	2
values[90]	112	1			T542	7		T672	3		T471	2
values[91]	126	1			T542	1		T672	2		T471	12
values[92]	116	1			T542	2		T672	4		T471	4
values[93]	121	1			T542	1		T672	5		T471	2
values[94]	117	1			T542	2		T672	2		T471	8
values[95]	103	1			T542	3		T672	2		T471	4
values[96]	134	1			T542	1		T672	6		T471	5
values[97]	134	1			T542	1		T672	3		T471	3
values[98]	121	1			T542	2		T672	2		T471	3
values[99]	112	1			T542	3		T672	10		T471	5
values[100]	105	1			T542	2		T672	8		T471	7
values[101]	85	1			T542	3		T672	2		T471	3
values[102]	113	1			T542	4		T672	4		T471	1
values[103]	90	1			T542	1		T672	3		T471	2
values[104]	117	1			T542	1		T672	4		T471	4
values[105]	117	1			T542	2		T672	2		T471	9
values[106]	109	1			T542	1		T672	2		T471	5
values[107]	113	1			T542	3		T672	3		T471	1
values[108]	112	1			T542	3		T672	4		T471	6
values[109]	115	1			T542	6		T672	4		T471	2
values[110]	112	1			T542	9		T672	7		T471	3
values[111]	99	1			T542	1		T672	2		T471	3
values[112]	128	1			T542	2		T672	6		T471	1
values[113]	106	1			T542	3		T672	7		T471	4
values[114]	103	1			T542	1		T672	8		T471	4
values[115]	93	1			T542	1		T672	3		T471	7
values[116]	112	1			T542	2		T672	2		T471	13
values[117]	84	1			T542	5		T672	4		T471	3
values[118]	73	1			T542	1		T672	5		T471	4
values[119]	104	1			T542	1		T672	2		T471	2
values[120]	92	1			T542	1		T672	2		T471	2
values[121]	85	1			T542	3		T672	4		T471	2
values[122]	74	1			T542	1		T672	3		T471	3
values[123]	85	1			T542	1		T672	2		T471	3
values[124]	130	1			T542	2		T672	3		T471	4
values[125]	128	1			T542	2		T672	4		T471	1
values[126]	254	1			T542	3		T672	3		T833	39
values[127]	1010	1			T542	30		T672	55		T833	59
values[128]	7350	1			T542	334		T672	577		T833	26