Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.15 95.49 94.05 95.34 94.90 97.53 99.61


Total tests in report: 2935
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
40.59 40.59 45.70 45.70 44.88 44.88 33.01 33.01 58.76 58.76 59.09 59.09 2.09 2.09 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.797200291
49.34 8.75 53.17 7.47 53.82 8.94 35.92 2.90 66.68 7.92 84.27 25.17 2.20 0.11 /workspace/coverage/default/0.chip_jtag_csr_rw.3530239673
56.60 7.26 61.58 8.41 57.13 3.32 41.97 6.06 66.90 0.23 84.27 0.00 27.73 25.53 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.3083420130
61.70 5.10 72.50 10.91 64.54 7.41 44.49 2.52 76.67 9.77 84.27 0.00 27.73 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_0.2201659118
65.24 3.54 72.57 0.07 65.89 1.35 44.49 0.00 76.95 0.28 84.27 0.00 47.30 19.57 /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.2892395440
68.43 3.18 77.74 5.17 69.86 3.97 48.11 3.61 78.76 1.81 88.81 4.55 47.30 0.00 /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.941785898
71.22 2.79 77.74 0.00 69.86 0.00 64.82 16.71 78.76 0.00 88.81 0.00 47.30 0.00 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1493905996
73.84 2.62 77.74 0.00 69.86 0.00 64.82 0.00 78.76 0.00 88.81 0.00 63.04 15.73 /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.4106290997
76.29 2.46 80.26 2.52 76.76 6.90 65.08 0.26 82.90 4.14 88.81 0.00 63.95 0.92 /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.1771505236
78.33 2.04 80.26 0.00 76.86 0.10 65.08 0.00 82.92 0.02 88.81 0.00 76.04 12.09 /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1365121220
80.14 1.81 81.79 1.53 78.17 1.31 71.52 6.43 84.00 1.08 89.34 0.52 76.04 0.00 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1235108854
81.82 1.68 84.64 2.85 79.71 1.54 75.13 3.61 85.03 1.03 90.38 1.05 76.04 0.00 /workspace/coverage/default/0.chip_sw_power_virus.1498785392
83.00 1.18 84.64 0.00 79.88 0.17 75.13 0.00 85.05 0.02 90.38 0.00 82.92 6.87 /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.2182376911
84.08 1.08 84.64 0.00 79.88 0.00 81.64 6.51 85.05 0.00 90.38 0.00 82.92 0.00 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.30818642
85.06 0.98 85.74 1.10 80.69 0.81 83.02 1.38 86.03 0.98 91.96 1.57 82.94 0.02 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.634766290
85.93 0.87 86.99 1.24 81.53 0.84 84.55 1.53 87.23 1.20 92.31 0.35 82.99 0.05 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1255991814
86.79 0.86 88.23 1.24 83.17 1.64 84.67 0.12 89.39 2.16 92.31 0.00 82.99 0.00 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3607072396
87.62 0.83 88.23 0.00 83.32 0.15 84.67 0.00 89.40 0.02 92.31 0.00 87.80 4.82 /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.2793241067
88.39 0.77 89.89 1.66 84.44 1.12 85.18 0.51 90.73 1.33 92.31 0.00 87.80 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_20.2424011125
89.14 0.75 90.29 0.41 84.56 0.13 85.20 0.01 90.86 0.12 96.15 3.85 87.80 0.00 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2019121826
89.82 0.68 90.29 0.00 84.56 0.00 85.20 0.00 90.86 0.00 96.15 0.00 91.88 4.08 /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.296290300
90.39 0.57 91.46 1.17 85.45 0.88 85.64 0.44 91.60 0.75 96.33 0.17 91.88 0.00 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1456077079
90.92 0.52 92.03 0.56 85.85 0.40 87.14 1.50 92.27 0.67 96.33 0.00 91.88 0.00 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.155486314
91.43 0.52 92.06 0.03 86.54 0.69 87.15 0.01 92.29 0.02 96.33 0.00 94.22 2.34 /workspace/coverage/cover_reg_top/28.xbar_stress_all.1547008130
91.82 0.38 92.57 0.51 87.04 0.50 87.96 0.82 92.78 0.49 96.33 0.00 94.22 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_10.1906776335
92.16 0.35 92.69 0.13 87.12 0.08 89.68 1.71 92.95 0.17 96.33 0.00 94.22 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2018066818
92.50 0.34 92.69 0.00 87.16 0.04 89.68 0.00 92.95 0.00 96.33 0.00 96.22 2.00 /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.2720104177
92.83 0.33 93.34 0.65 87.65 0.49 89.72 0.05 93.74 0.79 96.33 0.00 96.22 0.00 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4252127229
93.13 0.29 93.52 0.18 88.87 1.22 89.75 0.03 93.74 0.01 96.33 0.00 96.55 0.33 /workspace/coverage/cover_reg_top/19.chip_csr_rw.1035357555
93.37 0.25 93.52 0.01 90.22 1.35 89.75 0.00 93.74 0.00 96.33 0.00 96.67 0.13 /workspace/coverage/cover_reg_top/10.chip_tl_errors.30148252
93.55 0.18 93.52 0.00 90.22 0.00 90.82 1.07 93.74 0.00 96.33 0.00 96.67 0.00 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1604751627
93.70 0.15 93.73 0.21 90.54 0.32 91.17 0.36 93.74 0.00 96.33 0.00 96.67 0.00 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2254691533
93.82 0.12 93.74 0.01 90.87 0.34 91.19 0.02 94.12 0.37 96.33 0.00 96.67 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.335583917
93.94 0.12 93.74 0.00 90.91 0.04 91.19 0.00 94.13 0.02 96.33 0.00 97.33 0.66 /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.2965306383
94.05 0.11 93.80 0.06 90.92 0.01 91.81 0.62 94.14 0.01 96.33 0.00 97.33 0.00 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.908843515
94.15 0.09 93.99 0.20 91.05 0.13 91.92 0.11 94.27 0.13 96.33 0.00 97.33 0.00 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1481996605
94.24 0.09 94.01 0.01 91.11 0.06 92.21 0.29 94.30 0.02 96.50 0.17 97.33 0.00 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.136157739
94.33 0.09 94.01 0.00 91.64 0.53 92.21 0.00 94.30 0.00 96.50 0.00 97.33 0.00 /workspace/coverage/cover_reg_top/29.chip_tl_errors.313423928
94.42 0.08 94.01 0.00 91.64 0.00 92.68 0.47 94.30 0.00 96.50 0.00 97.37 0.04 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1310635417
94.49 0.08 94.03 0.02 91.68 0.04 92.70 0.03 94.30 0.00 96.50 0.00 97.74 0.38 /workspace/coverage/default/0.chip_sw_alert_test.2899768291
94.56 0.07 94.03 0.00 91.71 0.04 92.70 0.00 94.30 0.00 96.50 0.00 98.11 0.36 /workspace/coverage/cover_reg_top/39.xbar_stress_all.3310036699
94.63 0.07 94.21 0.19 91.76 0.04 92.82 0.12 94.34 0.04 96.50 0.00 98.12 0.01 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3442847406
94.69 0.06 94.25 0.03 91.80 0.04 93.07 0.25 94.38 0.04 96.50 0.00 98.12 0.00 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.220980178
94.74 0.05 94.25 0.00 91.94 0.14 93.07 0.00 94.54 0.16 96.50 0.00 98.12 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2350651472
94.79 0.05 94.25 0.00 91.94 0.00 93.37 0.30 94.54 0.00 96.50 0.00 98.12 0.00 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3341455188
94.83 0.05 94.29 0.04 91.96 0.02 93.39 0.02 94.56 0.02 96.68 0.17 98.13 0.01 /workspace/coverage/default/38.chip_sw_all_escalation_resets.403709171
94.88 0.05 94.29 0.00 91.96 0.00 93.67 0.28 94.56 0.00 96.68 0.00 98.13 0.00 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.3301880131
94.93 0.05 94.29 0.00 92.24 0.28 93.67 0.00 94.56 0.00 96.68 0.00 98.13 0.00 /workspace/coverage/cover_reg_top/11.chip_tl_errors.1885187524
94.97 0.05 94.37 0.09 92.35 0.11 93.67 0.00 94.63 0.07 96.68 0.00 98.13 0.00 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3821553572
95.02 0.04 94.38 0.01 92.36 0.01 93.91 0.24 94.63 0.00 96.68 0.00 98.13 0.00 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3555721265
95.06 0.04 94.43 0.04 92.55 0.19 93.91 0.01 94.65 0.02 96.68 0.00 98.13 0.00 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.1239954010
95.10 0.04 94.44 0.01 92.57 0.02 93.91 0.00 94.67 0.02 96.85 0.17 98.14 0.01 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1731008783
95.14 0.04 94.47 0.03 92.57 0.01 93.92 0.01 94.68 0.01 97.03 0.17 98.16 0.01 /workspace/coverage/default/77.chip_sw_all_escalation_resets.1651214394
95.17 0.04 94.47 0.01 92.58 0.01 93.93 0.02 94.69 0.01 97.20 0.17 98.17 0.01 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329978569
95.21 0.04 94.48 0.01 92.60 0.01 93.93 0.00 94.69 0.01 97.38 0.17 98.18 0.01 /workspace/coverage/default/17.chip_sw_all_escalation_resets.3967442163
95.25 0.04 94.59 0.11 92.61 0.01 94.02 0.09 94.69 0.00 97.38 0.00 98.18 0.00 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3603655851
95.28 0.04 94.59 0.00 92.64 0.02 94.18 0.15 94.72 0.02 97.38 0.00 98.19 0.01 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.713487984
95.32 0.03 94.59 0.00 92.74 0.10 94.18 0.00 94.73 0.02 97.38 0.00 98.28 0.09 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.545664055
95.35 0.03 94.59 0.00 92.74 0.00 94.37 0.19 94.73 0.00 97.38 0.00 98.28 0.00 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.3704499105
95.38 0.03 94.66 0.07 92.74 0.00 94.48 0.11 94.74 0.01 97.38 0.00 98.28 0.00 /workspace/coverage/default/1.chip_tap_straps_rma.1598519976
95.41 0.03 94.66 0.00 92.92 0.18 94.48 0.00 94.74 0.00 97.38 0.00 98.28 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_0.234717568
95.44 0.03 94.66 0.00 92.96 0.04 94.48 0.00 94.74 0.00 97.38 0.00 98.43 0.14 /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.566421714
95.47 0.03 94.66 0.00 92.96 0.00 94.48 0.00 94.74 0.00 97.55 0.17 98.43 0.00 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.640383983
95.50 0.03 94.73 0.07 92.99 0.03 94.49 0.01 94.79 0.05 97.55 0.00 98.43 0.00 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2631672860
95.52 0.02 94.73 0.00 92.99 0.00 94.64 0.14 94.79 0.00 97.55 0.00 98.43 0.00 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4127817740
95.54 0.02 94.78 0.05 93.04 0.05 94.64 0.00 94.81 0.02 97.55 0.00 98.43 0.00 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3668748466
95.56 0.02 94.78 0.00 93.15 0.11 94.64 0.00 94.81 0.00 97.55 0.00 98.43 0.00 /workspace/coverage/cover_reg_top/24.chip_tl_errors.886718333
95.58 0.02 94.79 0.01 93.15 0.00 94.72 0.08 94.82 0.01 97.55 0.00 98.43 0.00 /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.3550531419
95.59 0.02 94.79 0.00 93.15 0.00 94.82 0.10 94.82 0.00 97.55 0.00 98.43 0.00 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1967641036
95.61 0.02 94.79 0.00 93.15 0.01 94.82 0.00 94.82 0.00 97.55 0.00 98.52 0.09 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.2131070826
95.62 0.02 94.83 0.04 93.17 0.01 94.84 0.03 94.83 0.02 97.55 0.00 98.52 0.00 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.939946563
95.64 0.01 94.83 0.01 93.19 0.03 94.89 0.05 94.83 0.00 97.55 0.00 98.52 0.00 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3892706845
95.65 0.01 94.83 0.00 93.28 0.08 94.89 0.00 94.83 0.00 97.55 0.00 98.52 0.00 /workspace/coverage/default/0.chip_plic_all_irqs_20.2969318521
95.66 0.01 94.83 0.00 93.35 0.08 94.89 0.00 94.83 0.00 97.55 0.00 98.52 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_0.1783395660
95.68 0.01 94.83 0.00 93.40 0.05 94.89 0.00 94.85 0.02 97.55 0.00 98.53 0.01 /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.139848662
95.69 0.01 94.83 0.00 93.40 0.00 94.89 0.00 94.85 0.00 97.55 0.00 98.60 0.07 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.2927989581
95.70 0.01 94.87 0.03 93.42 0.02 94.89 0.00 94.86 0.01 97.55 0.00 98.60 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3077468734
95.71 0.01 94.87 0.00 93.46 0.04 94.89 0.00 94.88 0.02 97.55 0.00 98.60 0.00 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.1311764767
95.72 0.01 94.87 0.00 93.51 0.05 94.89 0.00 94.88 0.00 97.55 0.00 98.61 0.01 /workspace/coverage/cover_reg_top/8.chip_tl_errors.2042028781
95.73 0.01 94.87 0.00 93.51 0.00 94.95 0.06 94.88 0.00 97.55 0.00 98.61 0.00 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1084639044
95.74 0.01 94.87 0.00 93.53 0.02 94.95 0.00 94.88 0.00 97.55 0.00 98.65 0.04 /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.3775859339
95.75 0.01 94.87 0.00 93.59 0.05 94.96 0.01 94.88 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.2665365492
95.76 0.01 94.87 0.01 93.61 0.02 94.98 0.02 94.88 0.00 97.55 0.00 98.65 0.00 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2855222476
95.76 0.01 94.87 0.00 93.61 0.00 94.98 0.00 94.88 0.00 97.55 0.00 98.70 0.05 /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.1624314002
95.77 0.01 94.87 0.00 93.61 0.00 95.03 0.05 94.88 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3848842034
95.78 0.01 94.87 0.00 93.61 0.00 95.07 0.04 94.88 0.00 97.55 0.00 98.70 0.00 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3181078885
95.79 0.01 94.87 0.00 93.64 0.03 95.07 0.00 94.88 0.00 97.55 0.00 98.71 0.01 /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.3922185496
95.79 0.01 94.88 0.01 93.65 0.01 95.09 0.02 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.702316512
95.80 0.01 94.88 0.00 93.69 0.04 95.09 0.00 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/1.chip_plic_all_irqs_10.1223073770
95.80 0.01 94.88 0.00 93.69 0.00 95.12 0.03 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2918214097
95.81 0.01 94.88 0.00 93.72 0.03 95.12 0.00 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/cover_reg_top/6.chip_tl_errors.2617828796
95.81 0.01 94.88 0.00 93.75 0.03 95.12 0.00 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/cover_reg_top/68.xbar_stress_all.3110225056
95.82 0.01 94.88 0.00 93.78 0.03 95.12 0.00 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.216471776
95.82 0.01 94.88 0.00 93.81 0.03 95.12 0.00 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/1.chip_sw_gpio.181200019
95.83 0.01 94.88 0.00 93.81 0.00 95.15 0.03 94.88 0.00 97.55 0.00 98.71 0.00 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.76384680
95.83 0.01 94.88 0.00 93.81 0.01 95.15 0.00 94.88 0.00 97.55 0.00 98.73 0.02 /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3645482694
95.84 0.01 94.88 0.00 93.83 0.02 95.15 0.00 94.88 0.00 97.55 0.00 98.73 0.00 /workspace/coverage/default/2.chip_plic_all_irqs_20.640077352
95.84 0.01 94.88 0.00 93.83 0.00 95.15 0.00 94.88 0.00 97.55 0.00 98.75 0.02 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.1790055205
95.84 0.01 94.88 0.00 93.83 0.00 95.15 0.00 94.88 0.00 97.55 0.00 98.78 0.02 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3386905401
95.85 0.01 94.88 0.00 93.84 0.01 95.16 0.01 94.88 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1097720059
95.85 0.01 94.88 0.01 93.86 0.01 95.17 0.01 94.88 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3111402670
95.86 0.01 94.89 0.01 93.87 0.01 95.17 0.00 94.89 0.01 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.640968959
95.86 0.01 94.89 0.00 93.87 0.00 95.19 0.02 94.89 0.00 97.55 0.00 98.78 0.00 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3232615029
95.86 0.01 94.89 0.00 93.87 0.01 95.19 0.00 94.89 0.00 97.55 0.00 98.79 0.01 /workspace/coverage/cover_reg_top/2.chip_tl_errors.2343857104
95.87 0.01 94.89 0.00 93.87 0.00 95.21 0.02 94.89 0.00 97.55 0.00 98.79 0.00 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1785633779
95.87 0.01 94.89 0.00 93.87 0.00 95.21 0.01 94.89 0.00 97.55 0.00 98.80 0.01 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1218584165
95.87 0.01 94.90 0.01 93.87 0.00 95.21 0.01 94.89 0.00 97.55 0.00 98.80 0.00 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1966244081
95.87 0.01 94.90 0.00 93.89 0.01 95.21 0.00 94.89 0.00 97.55 0.00 98.80 0.00 /workspace/coverage/cover_reg_top/17.xbar_stress_all.3602346867
95.88 0.01 94.90 0.00 93.90 0.01 95.21 0.00 94.89 0.00 97.55 0.00 98.80 0.00 /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.33632433
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96.06 0.01 94.91 0.00 94.05 0.01 95.33 0.00 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.4268389232
96.06 0.01 94.91 0.00 94.05 0.01 95.33 0.00 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/1.chip_jtag_csr_rw.3983648974
96.06 0.01 94.91 0.00 94.05 0.01 95.33 0.00 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.459309830
96.06 0.01 94.91 0.00 94.05 0.00 95.34 0.01 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/0.chip_tap_straps_rma.3864744002
96.06 0.01 94.91 0.00 94.05 0.00 95.34 0.01 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/0.chip_sw_aon_timer_irq.3038924642
96.06 0.01 94.91 0.00 94.05 0.00 95.34 0.01 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/0.chip_sw_edn_boot_mode.3762551056
96.06 0.01 94.91 0.00 94.05 0.00 95.34 0.01 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.67746985
96.06 0.01 94.91 0.00 94.05 0.00 95.34 0.01 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.87314733
96.06 0.01 94.91 0.00 94.05 0.00 95.34 0.01 94.90 0.00 97.55 0.00 99.61 0.00 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4008634209


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.162009367
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.325774656
/workspace/coverage/cover_reg_top/0.chip_csr_rw.2830693020
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.808698054
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.2642204538
/workspace/coverage/cover_reg_top/0.chip_tl_errors.1382285838
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.788182522
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.3021605623
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.1825283126
/workspace/coverage/cover_reg_top/0.xbar_error_random.4266987310
/workspace/coverage/cover_reg_top/0.xbar_random.1228085196
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3043471435
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1707959259
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2176464660
/workspace/coverage/cover_reg_top/0.xbar_same_source.4238137445
/workspace/coverage/cover_reg_top/0.xbar_smoke.633304393
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1395697757
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3450089544
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.579889976
/workspace/coverage/cover_reg_top/0.xbar_stress_all.2124435437
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.4060254171
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2441514801
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.1247905418
/workspace/coverage/cover_reg_top/1.chip_csr_aliasing.3646721706
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2252864386
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2853140134
/workspace/coverage/cover_reg_top/1.chip_csr_rw.3597772922
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.2702653188
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.4082210737
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1622447005
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.1498323627
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.1051466924
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2349252365
/workspace/coverage/cover_reg_top/1.xbar_error_random.1903108627
/workspace/coverage/cover_reg_top/1.xbar_random.1761969584
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1050343639
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1730609582
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1191061115
/workspace/coverage/cover_reg_top/1.xbar_same_source.2431197021
/workspace/coverage/cover_reg_top/1.xbar_smoke.492178280
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.2900364443
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.773455875
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.1570019283
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1881155356
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.1539768631
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.2603814203
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.3184280925
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.623679979
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1268149364
/workspace/coverage/cover_reg_top/10.chip_csr_rw.338443691
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.4016743943
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.1718063520
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.3598003256
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.4071290978
/workspace/coverage/cover_reg_top/10.xbar_error_random.2497774645
/workspace/coverage/cover_reg_top/10.xbar_random.2860562748
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1297827924
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.3629783911
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.551295060
/workspace/coverage/cover_reg_top/10.xbar_same_source.2684181720
/workspace/coverage/cover_reg_top/10.xbar_smoke.2530473132
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.359808029
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2916221494
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.718432825
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.1538099315
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.388307873
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.4226089529
/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.2050982513
/workspace/coverage/cover_reg_top/11.chip_csr_rw.3644908215
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2129923096
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2202661513
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.1874226271
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.766276321
/workspace/coverage/cover_reg_top/11.xbar_error_random.3688943441
/workspace/coverage/cover_reg_top/11.xbar_random.168027367
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.44136118
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.1670352033
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.1820330149
/workspace/coverage/cover_reg_top/11.xbar_same_source.3057937644
/workspace/coverage/cover_reg_top/11.xbar_smoke.4195791954
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.829696628
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.2637924714
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.270100870
/workspace/coverage/cover_reg_top/11.xbar_stress_all.4116875532
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.3826575101
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.998480024
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.1266897465
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.2968891367
/workspace/coverage/cover_reg_top/12.chip_csr_rw.145810070
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.539508458
/workspace/coverage/cover_reg_top/12.chip_tl_errors.2039904807
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.743292427
/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1014487935
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1978904756
/workspace/coverage/cover_reg_top/12.xbar_error_random.1476335240
/workspace/coverage/cover_reg_top/12.xbar_random.270508757
/workspace/coverage/cover_reg_top/12.xbar_random_large_delays.2797356637
/workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.2666077637
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3723035291
/workspace/coverage/cover_reg_top/12.xbar_same_source.2656448352
/workspace/coverage/cover_reg_top/12.xbar_smoke.4196316856
/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1338193335
/workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2204447575
/workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.3635215426
/workspace/coverage/cover_reg_top/12.xbar_stress_all.252108312
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.3324288744
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1697058799
/workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3812986785
/workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.4291485994
/workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.573946076
/workspace/coverage/cover_reg_top/13.chip_csr_rw.2713579044
/workspace/coverage/cover_reg_top/13.chip_tl_errors.2204482842
/workspace/coverage/cover_reg_top/13.xbar_access_same_device.2098180519
/workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3902863700
/workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.4028263917
/workspace/coverage/cover_reg_top/13.xbar_error_random.1489467592
/workspace/coverage/cover_reg_top/13.xbar_random.2595655040
/workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1347002878
/workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.516099631
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.842449781
/workspace/coverage/cover_reg_top/13.xbar_same_source.2749542956
/workspace/coverage/cover_reg_top/13.xbar_smoke.1551467859
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.2696024244
/workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1843571054
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.1215384669
/workspace/coverage/cover_reg_top/13.xbar_stress_all.3621588988
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.1901575295
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.2215227355
/workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3755511556
/workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2891099457
/workspace/coverage/cover_reg_top/14.chip_csr_rw.3273351885
/workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.1874534958
/workspace/coverage/cover_reg_top/14.chip_tl_errors.3934540188
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.2789950134
/workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1968378741
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3448209002
/workspace/coverage/cover_reg_top/14.xbar_error_random.29544075
/workspace/coverage/cover_reg_top/14.xbar_random.1818953825
/workspace/coverage/cover_reg_top/14.xbar_random_large_delays.1470955166
/workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.3624399218
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.2601191709
/workspace/coverage/cover_reg_top/14.xbar_same_source.2342131098
/workspace/coverage/cover_reg_top/14.xbar_smoke.1507295716
/workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3402591010
/workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.3489357429
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.828220985
/workspace/coverage/cover_reg_top/14.xbar_stress_all.3520992292
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.3587787984
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1523067910
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.703136888
/workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2462183341
/workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.697724315
/workspace/coverage/cover_reg_top/15.chip_csr_rw.3244806840
/workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.2675877536
/workspace/coverage/cover_reg_top/15.chip_tl_errors.1694704409
/workspace/coverage/cover_reg_top/15.xbar_access_same_device.1060387018
/workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.808606239
/workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.1521340789
/workspace/coverage/cover_reg_top/15.xbar_error_random.1050610565
/workspace/coverage/cover_reg_top/15.xbar_random.3084223615
/workspace/coverage/cover_reg_top/15.xbar_random_large_delays.2833617361
/workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1692231547
/workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.2709301796
/workspace/coverage/cover_reg_top/15.xbar_same_source.2256673489
/workspace/coverage/cover_reg_top/15.xbar_smoke.3322296595
/workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2075373111
/workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.4218544070
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.1606581709
/workspace/coverage/cover_reg_top/15.xbar_stress_all.589897097
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.687492998
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.299631819
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.950680122
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2314306603
/workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.3471561232
/workspace/coverage/cover_reg_top/16.chip_csr_rw.1563501343
/workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.796498973
/workspace/coverage/cover_reg_top/16.chip_tl_errors.2804841243
/workspace/coverage/cover_reg_top/16.xbar_access_same_device.1957173918
/workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2056629837
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2773853000
/workspace/coverage/cover_reg_top/16.xbar_error_random.614517268
/workspace/coverage/cover_reg_top/16.xbar_random.1009719807
/workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1031880962
/workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2625527524
/workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3115906907
/workspace/coverage/cover_reg_top/16.xbar_same_source.3204249330
/workspace/coverage/cover_reg_top/16.xbar_smoke.704239692
/workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.1300546156
/workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1274441015
/workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.3513882972
/workspace/coverage/cover_reg_top/16.xbar_stress_all.216670395
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3928167331
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.1629959383
/workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3107718208
/workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.4096529812
/workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.961569145
/workspace/coverage/cover_reg_top/17.chip_csr_rw.729557463
/workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1404649444
/workspace/coverage/cover_reg_top/17.chip_tl_errors.1411319305
/workspace/coverage/cover_reg_top/17.xbar_access_same_device.2400138409
/workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.1098500731
/workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.3968808846
/workspace/coverage/cover_reg_top/17.xbar_error_random.3314509925
/workspace/coverage/cover_reg_top/17.xbar_random.1565487776
/workspace/coverage/cover_reg_top/17.xbar_random_large_delays.766987828
/workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.432577795
/workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.2525043855
/workspace/coverage/cover_reg_top/17.xbar_same_source.1252075371
/workspace/coverage/cover_reg_top/17.xbar_smoke.148168046
/workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.196765195
/workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.4103339396
/workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1888414352
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.473740346
/workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2059303847
/workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.1524325532
/workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.810395790
/workspace/coverage/cover_reg_top/18.chip_csr_rw.308510536
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.307585997
/workspace/coverage/cover_reg_top/18.chip_tl_errors.400436754
/workspace/coverage/cover_reg_top/18.xbar_access_same_device.3975497604
/workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1382788325
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3874227845
/workspace/coverage/cover_reg_top/18.xbar_error_random.1252285795
/workspace/coverage/cover_reg_top/18.xbar_random_large_delays.3885265047
/workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.4250293904
/workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.1007261490
/workspace/coverage/cover_reg_top/18.xbar_same_source.115493013
/workspace/coverage/cover_reg_top/18.xbar_smoke.1432175748
/workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3398584086
/workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1074761193
/workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1870550863
/workspace/coverage/cover_reg_top/18.xbar_stress_all.3746630803
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1709014980
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1605209014
/workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.1816972861
/workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.285534711
/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.2218923551
/workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.2762232646
/workspace/coverage/cover_reg_top/19.chip_tl_errors.847440880
/workspace/coverage/cover_reg_top/19.xbar_access_same_device.2391526060
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/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1770504272
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1976439704
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.158645075
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.926384660
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1165023329
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.166422820
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2094955187
/workspace/coverage/default/4.chip_sw_uart_tx_rx.863196024
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3123921088
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1055977776
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2008401726
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.3401875374
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1986431913
/workspace/coverage/default/4.chip_tap_straps_dev.852121093
/workspace/coverage/default/4.chip_tap_straps_prod.832291482
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1611327675
/workspace/coverage/default/40.chip_sw_all_escalation_resets.2161663394
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.28233003
/workspace/coverage/default/42.chip_sw_all_escalation_resets.3510441330
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3567434602
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1054263887
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2875276449
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078582268
/workspace/coverage/default/45.chip_sw_all_escalation_resets.83396894
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2806627978
/workspace/coverage/default/47.chip_sw_all_escalation_resets.883994089
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2974887345
/workspace/coverage/default/5.chip_sw_all_escalation_resets.4088214151
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2097200561
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2524070562
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3631608592
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.937059484
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2949912760
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.296426734
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2647799107
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1777604571
/workspace/coverage/default/54.chip_sw_all_escalation_resets.407289663
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173992845
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3267756937
/workspace/coverage/default/56.chip_sw_all_escalation_resets.4294903054
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1487508949
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1052864630
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3588104614
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.3891095799
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2021311905
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2353601015
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2454334441
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3566996932
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3890509535
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.760036044
/workspace/coverage/default/61.chip_sw_all_escalation_resets.513623833
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1877919756
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3550029293
/workspace/coverage/default/64.chip_sw_all_escalation_resets.1164310959
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1033004704
/workspace/coverage/default/65.chip_sw_all_escalation_resets.238475816
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.4126326294
/workspace/coverage/default/67.chip_sw_all_escalation_resets.1311795821
/workspace/coverage/default/68.chip_sw_all_escalation_resets.474742511
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2546303233
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441220205
/workspace/coverage/default/7.chip_sw_all_escalation_resets.4290841393
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.371984937
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2222976139
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1777893716
/workspace/coverage/default/70.chip_sw_all_escalation_resets.920963730
/workspace/coverage/default/71.chip_sw_all_escalation_resets.185833240
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1309646153
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3496412011
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.591956004
/workspace/coverage/default/73.chip_sw_all_escalation_resets.3952117025
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3598679416
/workspace/coverage/default/74.chip_sw_all_escalation_resets.3928117749
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1287136390
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2143879637
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2447054694
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2723820525
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2584772017
/workspace/coverage/default/79.chip_sw_all_escalation_resets.588826502
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1011395456
/workspace/coverage/default/8.chip_sw_all_escalation_resets.340232927
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.2300162048
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1587252811
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.497208546
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.148218700
/workspace/coverage/default/80.chip_sw_all_escalation_resets.256987433
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3553541977
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3325597656
/workspace/coverage/default/82.chip_sw_all_escalation_resets.727524021
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3714819694
/workspace/coverage/default/83.chip_sw_all_escalation_resets.2245403373
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.754396398
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131539211
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1294220605
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138023364
/workspace/coverage/default/86.chip_sw_all_escalation_resets.1933318145
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111572227
/workspace/coverage/default/87.chip_sw_all_escalation_resets.85483949
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.3054292716
/workspace/coverage/default/88.chip_sw_all_escalation_resets.98537592
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.2339779941
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1303843512
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2828591626
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.469747594
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3722235566
/workspace/coverage/default/90.chip_sw_all_escalation_resets.3220320529
/workspace/coverage/default/91.chip_sw_all_escalation_resets.4191030735
/workspace/coverage/default/92.chip_sw_all_escalation_resets.624335967
/workspace/coverage/default/93.chip_sw_all_escalation_resets.54994356
/workspace/coverage/default/94.chip_sw_all_escalation_resets.243916910
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1036277573
/workspace/coverage/default/96.chip_sw_all_escalation_resets.4113792740
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1755074569
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3559106946
/workspace/coverage/default/99.chip_sw_all_escalation_resets.4110766794
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.3539016765
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.1328295925
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1617628549
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2002836620
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2110957542
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3467825930
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.45860482
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.4112286033




Total test records in report: 2935
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3519660997 Aug 01 08:20:11 PM PDT 24 Aug 01 08:25:34 PM PDT 24 2461204792 ps
T2 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.2681529899 Aug 01 08:33:47 PM PDT 24 Aug 01 09:41:41 PM PDT 24 14747414000 ps
T3 /workspace/coverage/default/0.rom_keymgr_functest.505879661 Aug 01 08:17:18 PM PDT 24 Aug 01 08:24:59 PM PDT 24 4306603170 ps
T47 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2877883331 Aug 01 08:21:29 PM PDT 24 Aug 01 09:38:47 PM PDT 24 15732588392 ps
T4 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.797200291 Aug 01 08:17:28 PM PDT 24 Aug 01 08:44:14 PM PDT 24 12794693528 ps
T5 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2329978569 Aug 01 08:49:13 PM PDT 24 Aug 01 08:57:00 PM PDT 24 3385181106 ps
T19 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.220980178 Aug 01 08:12:17 PM PDT 24 Aug 01 10:10:21 PM PDT 24 31283191264 ps
T6 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.3848842034 Aug 01 08:17:13 PM PDT 24 Aug 01 09:14:38 PM PDT 24 19768522220 ps
T35 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3890509535 Aug 01 08:49:33 PM PDT 24 Aug 01 09:00:42 PM PDT 24 4552640572 ps
T88 /workspace/coverage/default/0.chip_sw_kmac_entropy.2232587819 Aug 01 08:14:04 PM PDT 24 Aug 01 08:18:57 PM PDT 24 2355679116 ps
T36 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1255991814 Aug 01 08:47:38 PM PDT 24 Aug 01 08:56:28 PM PDT 24 4647311294 ps
T48 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.1235108854 Aug 01 08:44:58 PM PDT 24 Aug 01 09:38:25 PM PDT 24 15441050382 ps
T116 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3323597193 Aug 01 08:15:40 PM PDT 24 Aug 01 08:20:19 PM PDT 24 3311563734 ps
T121 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3555721265 Aug 01 08:44:00 PM PDT 24 Aug 01 09:47:55 PM PDT 24 16341632328 ps
T20 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.634766290 Aug 01 08:28:14 PM PDT 24 Aug 01 08:34:34 PM PDT 24 7337205856 ps
T7 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2018066818 Aug 01 08:16:32 PM PDT 24 Aug 01 08:30:14 PM PDT 24 10997597164 ps
T105 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.435127982 Aug 01 08:30:29 PM PDT 24 Aug 01 08:35:07 PM PDT 24 2977613202 ps
T106 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2087332267 Aug 01 08:33:23 PM PDT 24 Aug 01 08:38:51 PM PDT 24 3116531368 ps
T50 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.478264687 Aug 01 08:37:36 PM PDT 24 Aug 01 08:48:57 PM PDT 24 4074427800 ps
T107 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3339313594 Aug 01 08:25:33 PM PDT 24 Aug 01 08:30:45 PM PDT 24 3253809156 ps
T13 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3044698153 Aug 01 08:22:51 PM PDT 24 Aug 01 08:39:57 PM PDT 24 8294075973 ps
T8 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.1369369297 Aug 01 08:45:08 PM PDT 24 Aug 01 08:52:28 PM PDT 24 6750370183 ps
T108 /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4267467505 Aug 01 08:44:43 PM PDT 24 Aug 01 08:50:57 PM PDT 24 3247627496 ps
T109 /workspace/coverage/default/0.rom_e2e_self_hash.1256524462 Aug 01 08:21:33 PM PDT 24 Aug 01 09:57:20 PM PDT 24 26409651106 ps
T49 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.713487984 Aug 01 08:38:35 PM PDT 24 Aug 01 08:49:09 PM PDT 24 4778624995 ps
T215 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3554372521 Aug 01 08:31:28 PM PDT 24 Aug 01 08:41:28 PM PDT 24 5085293632 ps
T196 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.581627863 Aug 01 08:21:36 PM PDT 24 Aug 01 08:43:06 PM PDT 24 11990588332 ps
T117 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3478172827 Aug 01 08:15:09 PM PDT 24 Aug 01 08:18:46 PM PDT 24 3539732452 ps
T869 /workspace/coverage/default/1.chip_sw_hmac_smoketest.4234604579 Aug 01 08:30:56 PM PDT 24 Aug 01 08:37:07 PM PDT 24 2672305296 ps
T21 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3997459482 Aug 01 08:38:42 PM PDT 24 Aug 01 08:59:44 PM PDT 24 22666809826 ps
T9 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.1967641036 Aug 01 08:44:59 PM PDT 24 Aug 01 09:33:35 PM PDT 24 14342713036 ps
T114 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3086739157 Aug 01 08:30:24 PM PDT 24 Aug 01 08:59:22 PM PDT 24 9987697899 ps
T441 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3062452118 Aug 01 08:25:12 PM PDT 24 Aug 01 08:30:49 PM PDT 24 2568324290 ps
T148 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.532032437 Aug 01 08:12:26 PM PDT 24 Aug 01 09:35:56 PM PDT 24 26985052328 ps
T133 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3059459703 Aug 01 08:39:10 PM PDT 24 Aug 01 08:48:05 PM PDT 24 5824857402 ps
T372 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3442847406 Aug 01 08:50:27 PM PDT 24 Aug 01 09:03:40 PM PDT 24 5744478416 ps
T68 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.908843515 Aug 01 08:39:24 PM PDT 24 Aug 01 08:51:04 PM PDT 24 4822351530 ps
T263 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.939946563 Aug 01 08:33:09 PM PDT 24 Aug 01 09:13:39 PM PDT 24 22760623650 ps
T85 /workspace/coverage/default/38.chip_sw_all_escalation_resets.403709171 Aug 01 08:48:36 PM PDT 24 Aug 01 08:59:31 PM PDT 24 4916116382 ps
T92 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3461611086 Aug 01 08:35:01 PM PDT 24 Aug 01 08:43:48 PM PDT 24 18936140348 ps
T67 /workspace/coverage/default/1.chip_tap_straps_rma.1598519976 Aug 01 08:28:29 PM PDT 24 Aug 01 08:37:17 PM PDT 24 5290542977 ps
T93 /workspace/coverage/default/1.rom_e2e_smoke.3297235907 Aug 01 08:36:37 PM PDT 24 Aug 01 09:33:44 PM PDT 24 14727562304 ps
T63 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1587252811 Aug 01 08:44:35 PM PDT 24 Aug 01 08:51:41 PM PDT 24 5467261258 ps
T94 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.3133971350 Aug 01 08:34:25 PM PDT 24 Aug 01 08:42:01 PM PDT 24 3630159280 ps
T95 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.1773424586 Aug 01 08:39:41 PM PDT 24 Aug 01 08:45:58 PM PDT 24 3516900392 ps
T96 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2356270248 Aug 01 08:14:14 PM PDT 24 Aug 01 08:37:34 PM PDT 24 6971208120 ps
T97 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1493905996 Aug 01 08:25:13 PM PDT 24 Aug 01 09:07:48 PM PDT 24 11839907620 ps
T98 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1131539211 Aug 01 08:52:20 PM PDT 24 Aug 01 08:58:32 PM PDT 24 4254477288 ps
T368 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3805226596 Aug 01 08:46:31 PM PDT 24 Aug 01 08:54:59 PM PDT 24 6294389062 ps
T227 /workspace/coverage/default/8.chip_sw_all_escalation_resets.340232927 Aug 01 08:43:46 PM PDT 24 Aug 01 08:52:33 PM PDT 24 4130842344 ps
T691 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1687196384 Aug 01 08:28:34 PM PDT 24 Aug 01 08:35:47 PM PDT 24 4858242756 ps
T870 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3087119743 Aug 01 08:18:38 PM PDT 24 Aug 01 08:22:10 PM PDT 24 3572889160 ps
T16 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1456077079 Aug 01 08:40:27 PM PDT 24 Aug 01 08:44:47 PM PDT 24 2887867518 ps
T871 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1881607742 Aug 01 08:19:40 PM PDT 24 Aug 01 08:24:04 PM PDT 24 3081344320 ps
T155 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2441220205 Aug 01 08:45:55 PM PDT 24 Aug 01 08:52:08 PM PDT 24 3272025530 ps
T187 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1153221351 Aug 01 08:37:30 PM PDT 24 Aug 01 08:47:23 PM PDT 24 5274802734 ps
T694 /workspace/coverage/default/14.chip_sw_all_escalation_resets.4203745760 Aug 01 08:45:21 PM PDT 24 Aug 01 08:56:46 PM PDT 24 5200919976 ps
T872 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1918108174 Aug 01 08:16:40 PM PDT 24 Aug 01 08:27:27 PM PDT 24 5074833060 ps
T700 /workspace/coverage/default/46.chip_sw_all_escalation_resets.2473462610 Aug 01 08:47:59 PM PDT 24 Aug 01 08:58:18 PM PDT 24 5289280056 ps
T373 /workspace/coverage/default/93.chip_sw_all_escalation_resets.54994356 Aug 01 08:53:10 PM PDT 24 Aug 01 09:02:00 PM PDT 24 4964477038 ps
T17 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.4252127229 Aug 01 08:43:25 PM PDT 24 Aug 01 08:54:19 PM PDT 24 4109533080 ps
T216 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.288233862 Aug 01 08:18:46 PM PDT 24 Aug 01 08:32:14 PM PDT 24 5379733160 ps
T118 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3973829188 Aug 01 08:27:25 PM PDT 24 Aug 01 08:38:32 PM PDT 24 4855757998 ps
T657 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3002259496 Aug 01 08:50:23 PM PDT 24 Aug 01 08:55:23 PM PDT 24 3544201860 ps
T337 /workspace/coverage/default/0.chip_sw_otbn_randomness.208474114 Aug 01 08:14:25 PM PDT 24 Aug 01 08:31:14 PM PDT 24 5652870416 ps
T692 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.4094632016 Aug 01 08:38:36 PM PDT 24 Aug 01 08:48:37 PM PDT 24 4994330440 ps
T873 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1492765331 Aug 01 08:16:19 PM PDT 24 Aug 01 08:26:19 PM PDT 24 4540126808 ps
T166 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.1604751627 Aug 01 08:31:27 PM PDT 24 Aug 01 09:45:46 PM PDT 24 43460957165 ps
T693 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.2551444719 Aug 01 08:14:43 PM PDT 24 Aug 01 08:21:36 PM PDT 24 4066862360 ps
T115 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.155486314 Aug 01 08:23:41 PM PDT 24 Aug 01 09:37:08 PM PDT 24 24975173904 ps
T669 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.362066748 Aug 01 08:16:30 PM PDT 24 Aug 01 08:22:32 PM PDT 24 5963636960 ps
T120 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3341455188 Aug 01 08:24:13 PM PDT 24 Aug 01 08:35:02 PM PDT 24 6025642906 ps
T69 /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1262216755 Aug 01 08:17:01 PM PDT 24 Aug 01 08:54:28 PM PDT 24 11051649612 ps
T134 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2838277324 Aug 01 08:18:41 PM PDT 24 Aug 01 08:24:10 PM PDT 24 3127440203 ps
T169 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.3038141626 Aug 01 08:33:44 PM PDT 24 Aug 01 08:53:23 PM PDT 24 10869867508 ps
T14 /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1766795604 Aug 01 08:13:19 PM PDT 24 Aug 01 08:22:49 PM PDT 24 6715269755 ps
T154 /workspace/coverage/default/99.chip_sw_all_escalation_resets.4110766794 Aug 01 08:52:11 PM PDT 24 Aug 01 09:03:42 PM PDT 24 6123465208 ps
T395 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1322958628 Aug 01 08:12:53 PM PDT 24 Aug 01 08:15:47 PM PDT 24 3097685960 ps
T217 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2008401726 Aug 01 08:42:55 PM PDT 24 Aug 01 08:54:55 PM PDT 24 4115963650 ps
T874 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4225294318 Aug 01 08:28:01 PM PDT 24 Aug 01 08:35:55 PM PDT 24 3713664062 ps
T208 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3295382857 Aug 01 08:33:46 PM PDT 24 Aug 01 08:45:39 PM PDT 24 4217653010 ps
T690 /workspace/coverage/default/1.chip_sw_aes_entropy.1037997196 Aug 01 08:24:46 PM PDT 24 Aug 01 08:30:00 PM PDT 24 2479464344 ps
T112 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.995944115 Aug 01 08:41:17 PM PDT 24 Aug 01 09:25:17 PM PDT 24 19797965943 ps
T226 /workspace/coverage/default/0.chip_tap_straps_dev.3378221088 Aug 01 08:14:01 PM PDT 24 Aug 01 08:16:51 PM PDT 24 2550754095 ps
T152 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1310635417 Aug 01 08:14:05 PM PDT 24 Aug 01 08:25:57 PM PDT 24 5446316306 ps
T327 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.217643947 Aug 01 08:35:00 PM PDT 24 Aug 01 09:02:18 PM PDT 24 7421830496 ps
T875 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1822177924 Aug 01 08:23:11 PM PDT 24 Aug 01 08:35:14 PM PDT 24 5524343880 ps
T189 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1297685311 Aug 01 08:27:04 PM PDT 24 Aug 01 08:34:11 PM PDT 24 5078105479 ps
T701 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3496412011 Aug 01 08:52:07 PM PDT 24 Aug 01 09:00:57 PM PDT 24 5148960690 ps
T876 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.7423543 Aug 01 08:12:34 PM PDT 24 Aug 01 08:19:40 PM PDT 24 4757423124 ps
T45 /workspace/coverage/default/1.rom_e2e_shutdown_output.427205168 Aug 01 08:37:26 PM PDT 24 Aug 01 09:37:58 PM PDT 24 28733126752 ps
T877 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1386065735 Aug 01 08:34:24 PM PDT 24 Aug 01 08:41:55 PM PDT 24 5757707404 ps
T170 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.371984937 Aug 01 08:44:05 PM PDT 24 Aug 01 09:02:00 PM PDT 24 12227241301 ps
T389 /workspace/coverage/default/1.rom_e2e_self_hash.165922529 Aug 01 08:34:25 PM PDT 24 Aug 01 10:09:20 PM PDT 24 26601601132 ps
T712 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2948546486 Aug 01 08:15:36 PM PDT 24 Aug 01 08:23:10 PM PDT 24 4079581440 ps
T407 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.598825498 Aug 01 08:49:58 PM PDT 24 Aug 01 08:56:27 PM PDT 24 3693162458 ps
T878 /workspace/coverage/default/1.chip_sw_example_flash.1043197291 Aug 01 08:18:25 PM PDT 24 Aug 01 08:22:25 PM PDT 24 2538149842 ps
T143 /workspace/coverage/default/0.chip_sw_power_sleep_load.397430411 Aug 01 08:17:13 PM PDT 24 Aug 01 08:27:43 PM PDT 24 10829038744 ps
T113 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2489483418 Aug 01 08:40:18 PM PDT 24 Aug 01 09:40:56 PM PDT 24 25233793925 ps
T228 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.1214042527 Aug 01 08:26:02 PM PDT 24 Aug 01 08:54:34 PM PDT 24 8493274660 ps
T22 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.796705193 Aug 01 08:40:19 PM PDT 24 Aug 01 08:47:48 PM PDT 24 6754415936 ps
T879 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.27269893 Aug 01 08:23:13 PM PDT 24 Aug 01 08:37:49 PM PDT 24 8182063840 ps
T767 /workspace/coverage/default/73.chip_sw_all_escalation_resets.3952117025 Aug 01 08:52:22 PM PDT 24 Aug 01 09:01:59 PM PDT 24 5693096798 ps
T18 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3307304593 Aug 01 08:11:56 PM PDT 24 Aug 01 08:37:57 PM PDT 24 8497104512 ps
T177 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.3116563510 Aug 01 08:36:20 PM PDT 24 Aug 01 08:47:32 PM PDT 24 5467216840 ps
T301 /workspace/coverage/default/2.chip_sw_hmac_smoketest.25308112 Aug 01 08:40:32 PM PDT 24 Aug 01 08:47:14 PM PDT 24 3169454956 ps
T230 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.157723086 Aug 01 08:31:55 PM PDT 24 Aug 01 08:54:24 PM PDT 24 7063094768 ps
T180 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3473252672 Aug 01 08:36:08 PM PDT 24 Aug 01 08:49:58 PM PDT 24 8964026237 ps
T302 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.800386706 Aug 01 08:13:47 PM PDT 24 Aug 01 08:30:32 PM PDT 24 9515200844 ps
T303 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2466109646 Aug 01 08:20:45 PM PDT 24 Aug 01 08:25:41 PM PDT 24 3724562936 ps
T304 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3157718970 Aug 01 08:36:20 PM PDT 24 Aug 01 08:46:10 PM PDT 24 6040076864 ps
T305 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3896121544 Aug 01 08:34:26 PM PDT 24 Aug 01 08:48:46 PM PDT 24 3588197116 ps
T159 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.89206663 Aug 01 08:19:53 PM PDT 24 Aug 01 08:21:31 PM PDT 24 2135268114 ps
T306 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1757232847 Aug 01 08:45:28 PM PDT 24 Aug 01 08:55:13 PM PDT 24 5582486958 ps
T62 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1053685430 Aug 01 08:38:16 PM PDT 24 Aug 01 09:07:13 PM PDT 24 26913548750 ps
T324 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.760036044 Aug 01 08:49:00 PM PDT 24 Aug 01 08:54:59 PM PDT 24 4024721752 ps
T325 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2554242741 Aug 01 08:29:06 PM PDT 24 Aug 01 08:33:45 PM PDT 24 2724452966 ps
T728 /workspace/coverage/default/2.chip_sw_all_escalation_resets.1218584165 Aug 01 08:32:04 PM PDT 24 Aug 01 08:43:59 PM PDT 24 6163780736 ps
T15 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1714639549 Aug 01 08:15:08 PM PDT 24 Aug 01 08:19:34 PM PDT 24 3260382700 ps
T248 /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3052365770 Aug 01 08:24:40 PM PDT 24 Aug 01 08:33:41 PM PDT 24 3483772582 ps
T119 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1112353165 Aug 01 08:26:29 PM PDT 24 Aug 01 08:38:14 PM PDT 24 3964542830 ps
T361 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1506441708 Aug 01 08:38:08 PM PDT 24 Aug 01 08:43:09 PM PDT 24 2958619687 ps
T697 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.585710330 Aug 01 08:26:49 PM PDT 24 Aug 01 08:39:18 PM PDT 24 8013317978 ps
T229 /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.58426207 Aug 01 08:16:30 PM PDT 24 Aug 01 08:43:54 PM PDT 24 8176790194 ps
T334 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3480018295 Aug 01 08:15:19 PM PDT 24 Aug 01 08:37:39 PM PDT 24 9760861142 ps
T144 /workspace/coverage/default/2.chip_sw_otbn_smoketest.690861734 Aug 01 08:41:50 PM PDT 24 Aug 01 09:11:26 PM PDT 24 8832190550 ps
T221 /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.456418049 Aug 01 08:18:39 PM PDT 24 Aug 01 08:43:21 PM PDT 24 8307337326 ps
T52 /workspace/coverage/default/0.chip_sw_alert_test.2899768291 Aug 01 08:13:09 PM PDT 24 Aug 01 08:17:54 PM PDT 24 3566266240 ps
T188 /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1010849750 Aug 01 08:23:16 PM PDT 24 Aug 01 08:27:57 PM PDT 24 3997656598 ps
T374 /workspace/coverage/default/27.chip_sw_all_escalation_resets.267103342 Aug 01 08:46:12 PM PDT 24 Aug 01 08:56:53 PM PDT 24 5727266440 ps
T720 /workspace/coverage/default/70.chip_sw_all_escalation_resets.920963730 Aug 01 08:49:51 PM PDT 24 Aug 01 08:58:24 PM PDT 24 6129752856 ps
T86 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2861938062 Aug 01 08:39:07 PM PDT 24 Aug 01 09:01:12 PM PDT 24 12458426104 ps
T370 /workspace/coverage/default/1.chip_sw_hmac_enc.2880757773 Aug 01 08:25:53 PM PDT 24 Aug 01 08:30:33 PM PDT 24 3184971064 ps
T249 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4161654196 Aug 01 08:15:18 PM PDT 24 Aug 01 08:22:41 PM PDT 24 3537471400 ps
T347 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1259761644 Aug 01 08:20:09 PM PDT 24 Aug 01 08:34:09 PM PDT 24 5546709676 ps
T880 /workspace/coverage/default/0.chip_sw_csrng_smoketest.3481146426 Aug 01 08:20:52 PM PDT 24 Aug 01 08:25:37 PM PDT 24 2946309300 ps
T881 /workspace/coverage/default/6.chip_sw_all_escalation_resets.2021311905 Aug 01 08:43:39 PM PDT 24 Aug 01 08:51:44 PM PDT 24 4788499540 ps
T141 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1442438851 Aug 01 08:34:37 PM PDT 24 Aug 01 08:45:00 PM PDT 24 4370123976 ps
T882 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1165770724 Aug 01 08:32:20 PM PDT 24 Aug 01 08:55:57 PM PDT 24 8865721000 ps
T883 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1046043146 Aug 01 08:14:58 PM PDT 24 Aug 01 08:19:40 PM PDT 24 2875753218 ps
T262 /workspace/coverage/default/2.chip_sw_rv_timer_irq.3784002810 Aug 01 08:32:53 PM PDT 24 Aug 01 08:36:57 PM PDT 24 3261840400 ps
T367 /workspace/coverage/default/41.chip_sw_all_escalation_resets.1731008783 Aug 01 08:47:01 PM PDT 24 Aug 01 08:58:16 PM PDT 24 5226088488 ps
T23 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1481996605 Aug 01 08:14:49 PM PDT 24 Aug 01 08:42:30 PM PDT 24 23446557970 ps
T386 /workspace/coverage/default/0.chip_sw_hmac_multistream.1669813838 Aug 01 08:17:12 PM PDT 24 Aug 01 08:45:12 PM PDT 24 7066016928 ps
T46 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4070239880 Aug 01 08:23:10 PM PDT 24 Aug 01 09:37:40 PM PDT 24 14745972758 ps
T253 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.484209983 Aug 01 08:15:31 PM PDT 24 Aug 01 08:23:04 PM PDT 24 5063363408 ps
T387 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.160740322 Aug 01 08:15:38 PM PDT 24 Aug 01 08:20:20 PM PDT 24 3035052646 ps
T350 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.4287821870 Aug 01 08:40:35 PM PDT 24 Aug 01 08:44:28 PM PDT 24 3174289882 ps
T362 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3722259980 Aug 01 08:13:31 PM PDT 24 Aug 01 08:24:23 PM PDT 24 4679655456 ps
T375 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3550545508 Aug 01 08:23:26 PM PDT 24 Aug 01 08:46:23 PM PDT 24 10583787954 ps
T388 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3220320529 Aug 01 08:52:42 PM PDT 24 Aug 01 09:05:42 PM PDT 24 5918046194 ps
T535 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3551850187 Aug 01 08:39:20 PM PDT 24 Aug 01 08:49:08 PM PDT 24 6084081312 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pullup.3441656450 Aug 01 08:12:12 PM PDT 24 Aug 01 08:17:04 PM PDT 24 2831332360 ps
T884 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1976439704 Aug 01 08:44:09 PM PDT 24 Aug 01 08:50:13 PM PDT 24 6322224684 ps
T741 /workspace/coverage/default/30.chip_sw_all_escalation_resets.604363172 Aug 01 08:48:46 PM PDT 24 Aug 01 08:58:25 PM PDT 24 5315939950 ps
T235 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.598782391 Aug 01 08:15:32 PM PDT 24 Aug 01 08:49:22 PM PDT 24 11718477384 ps
T885 /workspace/coverage/default/2.chip_sw_hmac_multistream.338145531 Aug 01 08:36:40 PM PDT 24 Aug 01 09:08:41 PM PDT 24 8128444942 ps
T81 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3020872140 Aug 01 08:28:23 PM PDT 24 Aug 01 08:40:19 PM PDT 24 5509845490 ps
T135 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2113361961 Aug 01 08:32:39 PM PDT 24 Aug 01 08:38:43 PM PDT 24 8072958557 ps
T886 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.4042469795 Aug 01 08:38:35 PM PDT 24 Aug 01 08:45:44 PM PDT 24 4113321776 ps
T70 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2999606182 Aug 01 08:38:09 PM PDT 24 Aug 01 08:44:49 PM PDT 24 5541426628 ps
T713 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.3491163617 Aug 01 08:12:24 PM PDT 24 Aug 01 08:21:21 PM PDT 24 3954813294 ps
T887 /workspace/coverage/default/2.chip_sw_hmac_enc.3802727883 Aug 01 08:36:33 PM PDT 24 Aug 01 08:40:30 PM PDT 24 2361345912 ps
T702 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.2563061675 Aug 01 08:34:14 PM PDT 24 Aug 01 09:00:13 PM PDT 24 7760517250 ps
T376 /workspace/coverage/default/1.chip_sw_aon_timer_irq.3041829284 Aug 01 08:26:28 PM PDT 24 Aug 01 08:34:22 PM PDT 24 4540348456 ps
T181 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.237693214 Aug 01 08:25:35 PM PDT 24 Aug 01 08:37:16 PM PDT 24 6816984958 ps
T888 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.3317217492 Aug 01 08:23:24 PM PDT 24 Aug 01 08:47:11 PM PDT 24 8060677876 ps
T889 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.527473320 Aug 01 08:38:15 PM PDT 24 Aug 01 08:48:53 PM PDT 24 4251365724 ps
T383 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078582268 Aug 01 08:48:57 PM PDT 24 Aug 01 08:54:39 PM PDT 24 3169053780 ps
T222 /workspace/coverage/default/0.chip_sw_uart_tx_rx.589084403 Aug 01 08:11:52 PM PDT 24 Aug 01 08:20:29 PM PDT 24 4283554320 ps
T218 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2855222476 Aug 01 08:11:58 PM PDT 24 Aug 01 08:20:58 PM PDT 24 4116532890 ps
T890 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1374138525 Aug 01 08:21:54 PM PDT 24 Aug 01 09:45:05 PM PDT 24 15162169800 ps
T891 /workspace/coverage/default/1.rom_e2e_static_critical.4253428673 Aug 01 08:34:38 PM PDT 24 Aug 01 09:45:58 PM PDT 24 16845345512 ps
T892 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2939460105 Aug 01 08:14:25 PM PDT 24 Aug 01 08:23:00 PM PDT 24 5336898572 ps
T893 /workspace/coverage/default/2.chip_sw_example_manufacturer.2794786375 Aug 01 08:34:41 PM PDT 24 Aug 01 08:39:23 PM PDT 24 2988531136 ps
T795 /workspace/coverage/default/32.chip_sw_all_escalation_resets.2813392285 Aug 01 08:47:22 PM PDT 24 Aug 01 08:55:40 PM PDT 24 4964615000 ps
T182 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3939797506 Aug 01 08:14:00 PM PDT 24 Aug 01 08:26:15 PM PDT 24 9671659477 ps
T236 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3637182767 Aug 01 08:16:27 PM PDT 24 Aug 01 08:51:07 PM PDT 24 9639176490 ps
T894 /workspace/coverage/default/2.chip_sw_aon_timer_irq.1600904488 Aug 01 08:33:42 PM PDT 24 Aug 01 08:41:02 PM PDT 24 3631031000 ps
T655 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2211026359 Aug 01 08:46:46 PM PDT 24 Aug 01 08:54:01 PM PDT 24 3554300800 ps
T895 /workspace/coverage/default/0.chip_sw_example_concurrency.62906632 Aug 01 08:13:04 PM PDT 24 Aug 01 08:18:21 PM PDT 24 3179660776 ps
T742 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.4111572227 Aug 01 08:52:27 PM PDT 24 Aug 01 08:58:49 PM PDT 24 4141050218 ps
T219 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3852150137 Aug 01 08:45:00 PM PDT 24 Aug 01 08:52:24 PM PDT 24 3106712816 ps
T445 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.57395081 Aug 01 08:15:37 PM PDT 24 Aug 02 12:50:35 AM PDT 24 113255752477 ps
T178 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.136157739 Aug 01 08:29:54 PM PDT 24 Aug 01 08:39:03 PM PDT 24 4539915318 ps
T250 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.3489552308 Aug 01 08:21:59 PM PDT 24 Aug 01 08:31:46 PM PDT 24 6362832230 ps
T142 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3892706845 Aug 01 08:41:59 PM PDT 24 Aug 01 09:02:31 PM PDT 24 8939939211 ps
T270 /workspace/coverage/default/0.chip_sw_example_flash.4059944364 Aug 01 08:11:32 PM PDT 24 Aug 01 08:16:40 PM PDT 24 3259232880 ps
T271 /workspace/coverage/default/1.chip_sw_otbn_randomness.3940118195 Aug 01 08:22:40 PM PDT 24 Aug 01 08:39:07 PM PDT 24 5323231144 ps
T272 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.4118120334 Aug 01 08:20:11 PM PDT 24 Aug 01 09:09:00 PM PDT 24 11608543000 ps
T273 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3589518933 Aug 01 08:35:05 PM PDT 24 Aug 01 08:52:32 PM PDT 24 8176935360 ps
T274 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.1448859315 Aug 01 08:41:32 PM PDT 24 Aug 01 08:45:57 PM PDT 24 2873403694 ps
T99 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2522134481 Aug 01 08:20:44 PM PDT 24 Aug 01 08:49:09 PM PDT 24 23745467278 ps
T275 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.1777893716 Aug 01 08:51:54 PM PDT 24 Aug 01 08:58:27 PM PDT 24 3581562292 ps
T276 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.76384680 Aug 01 08:19:18 PM PDT 24 Aug 01 08:29:54 PM PDT 24 4402849106 ps
T369 /workspace/coverage/default/62.chip_sw_all_escalation_resets.247623194 Aug 01 08:50:12 PM PDT 24 Aug 01 08:59:24 PM PDT 24 5446165780 ps
T665 /workspace/coverage/default/2.rom_e2e_self_hash.649029563 Aug 01 08:44:50 PM PDT 24 Aug 01 10:32:54 PM PDT 24 26211886450 ps
T176 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1764950093 Aug 01 08:23:36 PM PDT 24 Aug 01 09:45:48 PM PDT 24 15678915612 ps
T354 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.459309830 Aug 01 08:24:02 PM PDT 24 Aug 01 08:35:23 PM PDT 24 4055606324 ps
T896 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.896278693 Aug 01 08:11:53 PM PDT 24 Aug 01 08:22:42 PM PDT 24 5295670042 ps
T296 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.1692209687 Aug 01 08:31:33 PM PDT 24 Aug 01 08:46:48 PM PDT 24 5421295080 ps
T163 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.304776303 Aug 01 08:14:54 PM PDT 24 Aug 01 08:22:10 PM PDT 24 4407139084 ps
T897 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2581744341 Aug 01 08:30:30 PM PDT 24 Aug 01 08:33:57 PM PDT 24 2929114026 ps
T898 /workspace/coverage/default/1.chip_sw_flash_crash_alert.236514936 Aug 01 08:29:05 PM PDT 24 Aug 01 08:40:21 PM PDT 24 5584480684 ps
T715 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.4140847188 Aug 01 08:14:48 PM PDT 24 Aug 01 08:26:01 PM PDT 24 7873426218 ps
T225 /workspace/coverage/default/4.chip_tap_straps_dev.852121093 Aug 01 08:43:01 PM PDT 24 Aug 01 08:49:43 PM PDT 24 4217695616 ps
T73 /workspace/coverage/default/1.chip_tap_straps_prod.415373851 Aug 01 08:28:34 PM PDT 24 Aug 01 09:04:44 PM PDT 24 17313151845 ps
T899 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3814636258 Aug 01 08:13:34 PM PDT 24 Aug 01 08:32:01 PM PDT 24 6255377986 ps
T900 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.3201886683 Aug 01 08:37:57 PM PDT 24 Aug 01 09:39:27 PM PDT 24 15590138700 ps
T901 /workspace/coverage/default/2.rom_e2e_static_critical.3027076441 Aug 01 08:44:47 PM PDT 24 Aug 01 09:56:40 PM PDT 24 17601203280 ps
T160 /workspace/coverage/default/94.chip_sw_all_escalation_resets.243916910 Aug 01 08:52:47 PM PDT 24 Aug 01 08:59:11 PM PDT 24 4051549648 ps
T902 /workspace/coverage/default/2.chip_sw_edn_sw_mode.4294444788 Aug 01 08:35:20 PM PDT 24 Aug 01 09:15:41 PM PDT 24 11612042108 ps
T100 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.609168464 Aug 01 08:31:25 PM PDT 24 Aug 01 08:37:41 PM PDT 24 2929180788 ps
T410 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1644839575 Aug 01 08:34:37 PM PDT 24 Aug 01 08:44:12 PM PDT 24 5135960560 ps
T328 /workspace/coverage/default/1.chip_plic_all_irqs_20.2424011125 Aug 01 08:26:45 PM PDT 24 Aug 01 08:40:39 PM PDT 24 4696590272 ps
T379 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1290706140 Aug 01 08:40:04 PM PDT 24 Aug 01 08:43:42 PM PDT 24 2627805691 ps
T259 /workspace/coverage/default/1.chip_sw_plic_sw_irq.641707028 Aug 01 08:26:54 PM PDT 24 Aug 01 08:33:09 PM PDT 24 2746058400 ps
T411 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.876331383 Aug 01 08:13:54 PM PDT 24 Aug 01 08:31:53 PM PDT 24 6016240020 ps
T161 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.30818642 Aug 01 08:20:18 PM PDT 24 Aug 01 09:47:38 PM PDT 24 45545766514 ps
T412 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3481823055 Aug 01 08:21:34 PM PDT 24 Aug 01 08:27:24 PM PDT 24 5146749624 ps
T413 /workspace/coverage/default/39.chip_sw_all_escalation_resets.987034527 Aug 01 08:47:36 PM PDT 24 Aug 01 09:00:53 PM PDT 24 6239335360 ps
T414 /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1572253106 Aug 01 08:24:06 PM PDT 24 Aug 01 08:27:00 PM PDT 24 2214607820 ps
T903 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4172245421 Aug 01 08:38:45 PM PDT 24 Aug 01 08:49:24 PM PDT 24 4663427720 ps
T442 /workspace/coverage/default/1.chip_sw_kmac_entropy.387612675 Aug 01 08:19:53 PM PDT 24 Aug 01 08:22:49 PM PDT 24 3629042624 ps
T680 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.825697749 Aug 01 08:22:05 PM PDT 24 Aug 01 08:25:30 PM PDT 24 3231577584 ps
T904 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.228981752 Aug 01 08:38:03 PM PDT 24 Aug 01 08:43:56 PM PDT 24 3662784482 ps
T711 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834032764 Aug 01 08:49:05 PM PDT 24 Aug 01 08:55:41 PM PDT 24 4140677672 ps
T220 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2719079934 Aug 01 08:19:16 PM PDT 24 Aug 01 08:32:18 PM PDT 24 5687828118 ps
T905 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3488200249 Aug 01 08:45:35 PM PDT 24 Aug 01 08:54:23 PM PDT 24 5260040667 ps
T209 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1502737910 Aug 01 08:32:16 PM PDT 24 Aug 01 08:37:06 PM PDT 24 2648610767 ps
T530 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3441644086 Aug 01 08:36:34 PM PDT 24 Aug 01 09:03:09 PM PDT 24 12698728522 ps
T356 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1016307377 Aug 01 08:38:36 PM PDT 24 Aug 01 08:44:44 PM PDT 24 2961290000 ps
T175 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2368633122 Aug 01 08:23:30 PM PDT 24 Aug 01 09:38:03 PM PDT 24 14414075187 ps
T371 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2094955187 Aug 01 08:43:11 PM PDT 24 Aug 01 09:24:48 PM PDT 24 12643030040 ps
T380 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3889185890 Aug 01 08:28:20 PM PDT 24 Aug 01 08:37:33 PM PDT 24 5113925698 ps
T906 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2809787 Aug 01 08:35:43 PM PDT 24 Aug 01 08:40:39 PM PDT 24 3210908040 ps
T907 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1648847632 Aug 01 08:23:15 PM PDT 24 Aug 01 10:12:40 PM PDT 24 22658193761 ps
T329 /workspace/coverage/default/75.chip_sw_all_escalation_resets.2143879637 Aug 01 08:50:59 PM PDT 24 Aug 01 09:00:48 PM PDT 24 5208006818 ps
T149 /workspace/coverage/default/0.chip_plic_all_irqs_10.1906776335 Aug 01 08:18:43 PM PDT 24 Aug 01 08:27:39 PM PDT 24 3516365566 ps
T908 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1066483817 Aug 01 08:20:13 PM PDT 24 Aug 01 08:24:40 PM PDT 24 2828149816 ps
T909 /workspace/coverage/default/0.chip_sw_hmac_enc.3951908349 Aug 01 08:22:55 PM PDT 24 Aug 01 08:28:11 PM PDT 24 3428190236 ps
T910 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2516261482 Aug 01 08:40:37 PM PDT 24 Aug 01 08:48:18 PM PDT 24 3005456548 ps
T911 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2602810556 Aug 01 08:27:12 PM PDT 24 Aug 01 08:37:47 PM PDT 24 3410621546 ps
T277 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3542616137 Aug 01 08:21:53 PM PDT 24 Aug 01 09:20:12 PM PDT 24 10517856004 ps
T912 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.802017233 Aug 01 08:32:41 PM PDT 24 Aug 01 08:54:34 PM PDT 24 14430356684 ps
T167 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.4127817740 Aug 01 08:13:20 PM PDT 24 Aug 01 09:38:38 PM PDT 24 43290038503 ps
T913 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1011186952 Aug 01 08:45:05 PM PDT 24 Aug 01 09:44:30 PM PDT 24 15841130676 ps
T914 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.207672194 Aug 01 08:34:16 PM PDT 24 Aug 01 09:32:49 PM PDT 24 15798087696 ps
T709 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1287136390 Aug 01 08:51:10 PM PDT 24 Aug 01 08:57:35 PM PDT 24 3335096070 ps
T915 /workspace/coverage/default/0.chip_sw_aes_enc.2676861322 Aug 01 08:13:54 PM PDT 24 Aug 01 08:18:16 PM PDT 24 2619959296 ps
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