Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.ast_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	140271	1			T78	320		T79	3		T80	5
values[2]	10122	1			T78	6		T80	1		T84	7
values[3]	4191	1			T84	1		T542	1		T672	1
values[4]	2467	1			T84	2		T542	1		T672	1
values[5]	1545	1			T84	2		T542	1		T672	1
values[6]	1026	1			T84	8		T542	1		T672	1
values[7]	756	1			T84	4		T542	1		T672	1
values[8]	576	1			T84	2		T542	1		T672	1
values[9]	500	1			T84	2		T542	1		T672	1
values[10]	472	1			T84	2		T542	1		T672	1
values[11]	407	1			T84	1		T542	1		T672	1
values[12]	341	1			T84	3		T542	1		T672	1
values[13]	332	1			T84	1		T542	1		T672	1
values[14]	304	1			T84	1		T542	1		T672	1
values[15]	277	1			T84	1		T542	1		T672	1
values[16]	245	1			T84	2		T542	1		T672	1
values[17]	271	1			T84	1		T542	1		T672	1
values[18]	272	1			T84	3		T542	1		T672	1
values[19]	289	1			T84	3		T542	1		T672	1
values[20]	266	1			T84	12		T542	1		T672	1
values[21]	296	1			T84	19		T542	1		T672	1
values[22]	269	1			T84	9		T542	1		T672	1
values[23]	272	1			T84	1		T542	1		T672	1
values[24]	303	1			T84	1		T542	1		T672	1
values[25]	258	1			T84	3		T542	1		T672	1
values[26]	239	1			T84	1		T542	1		T672	1
values[27]	233	1			T84	3		T542	1		T672	1
values[28]	246	1			T84	2		T542	1		T672	1
values[29]	236	1			T84	9		T542	1		T672	1
values[30]	265	1			T84	7		T542	1		T672	1
values[31]	241	1			T84	3		T542	1		T672	1
values[32]	219	1			T84	1		T542	1		T672	1
values[33]	195	1			T84	5		T542	1		T672	1
values[34]	258	1			T84	3		T542	1		T672	1
values[35]	201	1			T84	2		T542	1		T672	1
values[36]	248	1			T84	4		T542	1		T672	1
values[37]	242	1			T84	1		T542	1		T672	1
values[38]	239	1			T84	1		T542	1		T672	1
values[39]	221	1			T84	5		T542	1		T672	1
values[40]	232	1			T84	1		T542	1		T672	1
values[41]	266	1			T84	4		T542	1		T672	1
values[42]	240	1			T84	8		T542	1		T672	1
values[43]	251	1			T84	7		T542	1		T672	1
values[44]	263	1			T84	8		T542	1		T672	1
values[45]	219	1			T84	3		T542	1		T672	1
values[46]	198	1			T84	2		T542	1		T672	1
values[47]	203	1			T84	11		T542	1		T672	1
values[48]	238	1			T84	2		T542	1		T672	2
values[49]	253	1			T84	5		T542	1		T672	1
values[50]	217	1			T84	5		T542	1		T672	1
values[51]	230	1			T84	2		T542	1		T672	1
values[52]	238	1			T84	2		T542	1		T672	1
values[53]	245	1			T84	4		T542	1		T672	1
values[54]	249	1			T84	8		T542	1		T672	1
values[55]	227	1			T84	2		T542	1		T672	1
values[56]	258	1			T84	1		T542	1		T672	1
values[57]	213	1			T84	6		T542	1		T672	1
values[58]	210	1			T84	2		T542	1		T672	1
values[59]	161	1			T84	2		T542	1		T672	1
values[60]	158	1			T84	1		T542	1		T672	1
values[61]	198	1			T84	7		T542	1		T672	1
values[62]	186	1			T84	4		T542	1		T672	1
values[63]	179	1			T84	11		T542	1		T672	1
values[64]	182	1			T84	16		T542	1		T672	1
values[65]	158	1			T84	13		T542	1		T672	1
values[66]	216	1			T84	50		T542	1		T672	1
values[67]	191	1			T84	30		T542	1		T672	1
values[68]	171	1			T84	16		T542	1		T672	1
values[69]	144	1			T84	9		T542	1		T672	1
values[70]	100	1			T84	8		T542	1		T672	1
values[71]	80	1			T84	4		T542	1		T672	1
values[72]	82	1			T84	9		T542	1		T672	1
values[73]	107	1			T84	1		T542	1		T672	1
values[74]	103	1			T84	4		T542	1		T672	1
values[75]	83	1			T84	1		T542	1		T672	1
values[76]	91	1			T84	9		T542	1		T672	1
values[77]	107	1			T84	18		T542	1		T672	1
values[78]	107	1			T84	12		T542	1		T672	1
values[79]	96	1			T84	12		T542	1		T672	1
values[80]	100	1			T84	6		T542	1		T672	1
values[81]	99	1			T84	16		T542	1		T672	1
values[82]	90	1			T84	16		T542	1		T672	1
values[83]	83	1			T84	13		T542	1		T672	1
values[84]	71	1			T84	8		T542	1		T672	1
values[85]	72	1			T84	2		T542	1		T672	1
values[86]	75	1			T542	1		T672	1		T462	1
values[87]	67	1			T542	1		T672	1		T462	2
values[88]	76	1			T542	1		T672	1		T462	2
values[89]	63	1			T542	1		T672	2		T462	2
values[90]	57	1			T542	1		T672	1		T462	3
values[91]	75	1			T542	1		T672	1		T462	4
values[92]	71	1			T542	1		T672	1		T462	5
values[93]	69	1			T542	1		T672	1		T462	3
values[94]	71	1			T542	1		T672	1		T462	2
values[95]	67	1			T542	1		T672	1		T462	8
values[96]	75	1			T542	1		T672	1		T462	5
values[97]	59	1			T542	6		T672	1		T462	2
values[98]	41	1			T542	3		T672	1		T462	1
values[99]	53	1			T542	3		T672	1		T462	1
values[100]	63	1			T542	1		T672	1		T462	1
values[101]	66	1			T542	4		T672	1		T462	1
values[102]	58	1			T542	2		T672	1		T462	3
values[103]	67	1			T542	3		T672	1		T462	1
values[104]	80	1			T542	3		T672	3		T462	3
values[105]	76	1			T542	2		T672	3		T462	2
values[106]	59	1			T542	1		T672	2		T462	1
values[107]	61	1			T542	2		T672	1		T462	2
values[108]	56	1			T542	5		T672	4		T462	1
values[109]	59	1			T542	1		T672	1		T462	2
values[110]	68	1			T542	1		T672	3		T462	2
values[111]	54	1			T542	5		T672	2		T462	2
values[112]	66	1			T542	4		T672	2		T462	2
values[113]	61	1			T542	2		T672	3		T462	2
values[114]	68	1			T542	4		T672	1		T462	2
values[115]	45	1			T542	1		T672	1		T462	1
values[116]	64	1			T542	5		T672	1		T462	3
values[117]	81	1			T542	1		T672	3		T462	2
values[118]	68	1			T542	2		T672	2		T462	9
values[119]	68	1			T542	2		T672	2		T462	1
values[120]	58	1			T542	1		T672	3		T462	2
values[121]	65	1			T542	1		T672	2		T462	1
values[122]	47	1			T542	1		T672	1		T462	1
values[123]	59	1			T542	5		T672	1		T462	1
values[124]	70	1			T542	3		T672	1		T462	2
values[125]	68	1			T542	5		T672	1		T462	4
values[126]	95	1			T542	9		T672	1		T462	2
values[127]	732	1			T542	26		T672	28		T462	25
values[128]	6794	1			T542	309		T672	306		T462	264