Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sensor_ctrl_aon_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	147459	1			T78	339		T79	9		T80	8
values[2]	10137	1			T78	8		T80	1		T446	1
values[3]	3376	1			T539	1		T542	1		T541	22
values[4]	1927	1			T542	1		T541	13		T584	1
values[5]	1092	1			T542	1		T541	14		T625	1
values[6]	723	1			T542	1		T541	26		T460	6
values[7]	513	1			T542	1		T541	35		T460	6
values[8]	471	1			T542	1		T541	32		T460	6
values[9]	331	1			T542	1		T541	4		T456	3
values[10]	292	1			T542	1		T541	11		T456	6
values[11]	252	1			T542	1		T541	1		T456	3
values[12]	273	1			T542	1		T456	10		T824	1
values[13]	253	1			T542	1		T456	7		T824	1
values[14]	292	1			T542	1		T456	11		T824	1
values[15]	250	1			T542	1		T456	9		T824	1
values[16]	260	1			T542	1		T456	5		T824	1
values[17]	247	1			T542	1		T456	4		T824	1
values[18]	231	1			T542	1		T456	7		T824	1
values[19]	230	1			T542	1		T456	2		T824	1
values[20]	338	1			T542	1		T456	24		T824	1
values[21]	233	1			T542	1		T456	3		T824	1
values[22]	188	1			T542	1		T456	8		T824	1
values[23]	183	1			T542	1		T456	7		T824	1
values[24]	211	1			T542	1		T456	14		T824	1
values[25]	214	1			T542	1		T456	7		T824	1
values[26]	197	1			T542	1		T456	5		T824	1
values[27]	217	1			T542	1		T456	5		T824	1
values[28]	218	1			T542	1		T456	6		T824	1
values[29]	228	1			T542	1		T456	3		T824	1
values[30]	211	1			T542	1		T456	5		T824	1
values[31]	183	1			T542	1		T456	3		T824	1
values[32]	195	1			T542	1		T456	7		T824	1
values[33]	234	1			T542	1		T456	6		T824	1
values[34]	174	1			T542	1		T456	6		T824	1
values[35]	210	1			T542	1		T456	7		T824	1
values[36]	192	1			T542	1		T456	14		T824	1
values[37]	221	1			T542	1		T456	4		T824	1
values[38]	260	1			T542	1		T456	21		T824	1
values[39]	232	1			T542	1		T456	11		T824	1
values[40]	230	1			T542	1		T456	17		T824	1
values[41]	185	1			T542	1		T456	5		T824	1
values[42]	205	1			T542	1		T456	8		T824	1
values[43]	212	1			T542	1		T456	4		T824	1
values[44]	227	1			T542	1		T456	2		T824	2
values[45]	167	1			T542	1		T456	4		T824	1
values[46]	148	1			T542	1		T456	6		T824	1
values[47]	152	1			T542	1		T456	4		T824	1
values[48]	166	1			T542	1		T456	3		T824	1
values[49]	192	1			T542	1		T456	5		T824	1
values[50]	207	1			T542	1		T456	12		T824	1
values[51]	163	1			T542	1		T456	6		T824	1
values[52]	151	1			T542	1		T456	5		T824	1
values[53]	170	1			T542	1		T456	15		T824	1
values[54]	171	1			T542	1		T456	14		T824	1
values[55]	165	1			T542	1		T456	21		T824	1
values[56]	151	1			T542	1		T456	7		T824	1
values[57]	148	1			T542	1		T456	8		T824	1
values[58]	177	1			T542	1		T456	5		T824	1
values[59]	125	1			T542	1		T456	4		T824	1
values[60]	116	1			T542	1		T456	4		T824	1
values[61]	116	1			T542	1		T456	7		T824	1
values[62]	108	1			T542	1		T456	5		T824	1
values[63]	107	1			T542	1		T456	5		T824	1
values[64]	115	1			T542	1		T456	4		T824	1
values[65]	116	1			T542	1		T456	4		T824	1
values[66]	125	1			T542	1		T456	10		T824	1
values[67]	133	1			T542	1		T456	3		T824	1
values[68]	104	1			T542	1		T456	6		T824	1
values[69]	83	1			T542	1		T456	3		T824	1
values[70]	55	1			T542	1		T456	5		T824	1
values[71]	52	1			T542	1		T456	5		T824	1
values[72]	49	1			T542	1		T456	9		T824	1
values[73]	59	1			T542	1		T456	13		T824	1
values[74]	63	1			T542	1		T456	9		T824	1
values[75]	59	1			T542	1		T456	13		T824	1
values[76]	47	1			T542	1		T456	12		T824	1
values[77]	47	1			T542	1		T456	7		T824	1
values[78]	46	1			T542	1		T824	1		T490	1
values[79]	36	1			T542	1		T824	1		T490	1
values[80]	41	1			T542	1		T824	1		T490	1
values[81]	40	1			T542	1		T824	1		T490	1
values[82]	33	1			T542	1		T824	1		T490	1
values[83]	49	1			T542	1		T824	1		T490	1
values[84]	40	1			T542	1		T824	1		T490	1
values[85]	48	1			T542	1		T824	1		T490	1
values[86]	53	1			T542	1		T824	1		T490	1
values[87]	53	1			T542	1		T824	1		T490	1
values[88]	50	1			T542	1		T824	6		T490	1
values[89]	45	1			T542	1		T824	1		T490	1
values[90]	50	1			T542	1		T824	2		T490	1
values[91]	58	1			T542	1		T824	2		T490	2
values[92]	50	1			T542	1		T824	1		T490	1
values[93]	54	1			T542	1		T824	4		T490	1
values[94]	50	1			T542	1		T824	4		T490	2
values[95]	53	1			T542	1		T824	7		T490	1
values[96]	51	1			T542	1		T824	12		T490	1
values[97]	54	1			T542	1		T824	4		T490	1
values[98]	61	1			T542	1		T824	4		T490	1
values[99]	51	1			T542	1		T824	5		T490	1
values[100]	53	1			T542	1		T824	2		T490	1
values[101]	40	1			T542	1		T824	1		T490	1
values[102]	54	1			T542	1		T824	1		T490	1
values[103]	46	1			T542	1		T824	3		T490	1
values[104]	45	1			T542	1		T824	2		T490	1
values[105]	58	1			T542	2		T824	5		T490	1
values[106]	55	1			T542	1		T824	1		T490	1
values[107]	52	1			T542	1		T824	2		T490	1
values[108]	51	1			T542	1		T824	1		T490	1
values[109]	48	1			T542	1		T824	2		T490	1
values[110]	50	1			T542	1		T824	1		T490	1
values[111]	56	1			T542	3		T824	1		T490	1
values[112]	44	1			T542	2		T824	1		T490	1
values[113]	48	1			T542	4		T824	3		T490	1
values[114]	32	1			T542	3		T824	1		T490	1
values[115]	57	1			T542	5		T824	4		T490	2
values[116]	39	1			T542	1		T824	1		T490	1
values[117]	50	1			T542	5		T824	1		T490	1
values[118]	52	1			T542	1		T824	3		T490	1
values[119]	36	1			T542	2		T824	1		T490	1
values[120]	52	1			T542	8		T824	1		T490	1
values[121]	47	1			T542	1		T824	5		T490	1
values[122]	48	1			T542	2		T824	4		T490	3
values[123]	44	1			T542	2		T824	1		T490	1
values[124]	43	1			T542	2		T824	2		T490	2
values[125]	66	1			T542	1		T824	5		T490	5
values[126]	62	1			T542	3		T824	4		T490	3
values[127]	682	1			T542	46		T824	16		T490	33
values[128]	6826	1			T542	286		T824	270		T490	367