Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.sram_ctrl_ret_aon__ram_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	143753	1			T78	295		T79	6		T80	9
values[2]	9948	1			T78	4		T84	81		T458	2
values[3]	3575	1			T84	41		T435	1		T436	111
values[4]	2148	1			T84	15		T435	1		T436	65
values[5]	1373	1			T84	4		T435	1		T436	69
values[6]	946	1			T84	8		T435	1		T436	40
values[7]	668	1			T84	9		T435	1		T436	18
values[8]	546	1			T435	1		T436	16		T815	2
values[9]	403	1			T435	1		T436	4		T815	2
values[10]	387	1			T435	1		T542	1		T672	1
values[11]	279	1			T435	1		T542	1		T672	1
values[12]	325	1			T435	1		T542	1		T672	2
values[13]	292	1			T435	1		T542	1		T672	1
values[14]	319	1			T435	1		T542	1		T672	1
values[15]	313	1			T435	1		T542	1		T672	1
values[16]	247	1			T435	1		T542	1		T672	1
values[17]	269	1			T435	1		T542	1		T672	1
values[18]	275	1			T435	1		T542	1		T672	1
values[19]	286	1			T435	1		T542	1		T672	1
values[20]	262	1			T435	1		T542	1		T672	1
values[21]	308	1			T435	1		T542	1		T672	1
values[22]	258	1			T435	1		T542	1		T672	1
values[23]	285	1			T435	1		T542	1		T672	1
values[24]	318	1			T435	1		T542	1		T672	1
values[25]	295	1			T435	1		T542	1		T672	1
values[26]	292	1			T435	1		T542	1		T672	1
values[27]	265	1			T435	1		T542	1		T672	1
values[28]	301	1			T435	1		T542	1		T672	1
values[29]	236	1			T435	1		T542	1		T672	1
values[30]	261	1			T435	1		T542	1		T672	1
values[31]	264	1			T435	1		T542	1		T672	1
values[32]	228	1			T435	1		T542	1		T672	1
values[33]	276	1			T435	1		T542	1		T672	1
values[34]	288	1			T435	1		T542	1		T672	2
values[35]	299	1			T435	1		T542	1		T672	1
values[36]	256	1			T435	1		T542	1		T672	1
values[37]	262	1			T435	1		T542	1		T672	1
values[38]	260	1			T435	1		T542	2		T672	1
values[39]	253	1			T435	1		T542	1		T672	1
values[40]	302	1			T435	1		T542	1		T672	1
values[41]	291	1			T435	1		T542	1		T672	1
values[42]	250	1			T435	1		T542	1		T672	1
values[43]	254	1			T435	1		T542	1		T672	1
values[44]	240	1			T435	1		T542	1		T672	1
values[45]	224	1			T435	1		T542	1		T672	1
values[46]	221	1			T435	1		T542	1		T672	1
values[47]	295	1			T435	1		T542	1		T672	1
values[48]	241	1			T435	1		T542	1		T672	1
values[49]	213	1			T435	1		T542	1		T672	1
values[50]	239	1			T435	1		T542	1		T672	1
values[51]	247	1			T435	1		T542	1		T672	1
values[52]	248	1			T435	1		T542	1		T672	1
values[53]	195	1			T435	1		T542	1		T672	1
values[54]	185	1			T435	1		T542	1		T672	1
values[55]	175	1			T435	1		T542	1		T672	1
values[56]	226	1			T435	1		T542	1		T672	1
values[57]	214	1			T435	1		T542	1		T672	1
values[58]	206	1			T435	2		T542	1		T672	1
values[59]	221	1			T435	1		T542	1		T672	1
values[60]	184	1			T435	1		T542	1		T672	1
values[61]	185	1			T435	1		T542	1		T672	1
values[62]	190	1			T435	1		T542	1		T672	1
values[63]	186	1			T435	1		T542	1		T672	1
values[64]	137	1			T435	1		T542	1		T672	1
values[65]	121	1			T435	1		T542	1		T672	1
values[66]	139	1			T435	1		T542	1		T672	1
values[67]	88	1			T435	1		T542	1		T672	1
values[68]	123	1			T435	1		T542	1		T672	1
values[69]	137	1			T435	1		T542	1		T672	1
values[70]	90	1			T435	1		T542	1		T672	1
values[71]	78	1			T435	1		T542	1		T672	1
values[72]	72	1			T435	1		T542	1		T672	1
values[73]	80	1			T435	1		T542	1		T672	1
values[74]	86	1			T435	1		T542	1		T672	1
values[75]	72	1			T435	1		T542	5		T672	1
values[76]	57	1			T435	1		T542	1		T672	1
values[77]	68	1			T435	1		T542	2		T672	1
values[78]	60	1			T435	1		T542	1		T672	1
values[79]	71	1			T435	8		T542	3		T672	1
values[80]	67	1			T435	4		T542	5		T672	1
values[81]	77	1			T435	12		T542	2		T672	1
values[82]	82	1			T435	3		T542	10		T672	1
values[83]	71	1			T435	7		T542	2		T672	1
values[84]	63	1			T435	1		T542	1		T672	1
values[85]	67	1			T435	1		T542	3		T672	1
values[86]	62	1			T435	3		T542	1		T672	1
values[87]	60	1			T435	1		T542	3		T672	1
values[88]	59	1			T435	1		T542	1		T672	1
values[89]	67	1			T435	2		T542	4		T672	1
values[90]	74	1			T435	2		T542	3		T672	2
values[91]	58	1			T435	2		T542	4		T672	1
values[92]	52	1			T435	2		T542	1		T672	1
values[93]	76	1			T435	4		T542	7		T672	1
values[94]	64	1			T435	1		T542	3		T672	1
values[95]	56	1			T435	1		T542	1		T672	1
values[96]	61	1			T435	1		T542	1		T672	1
values[97]	66	1			T435	3		T542	5		T672	1
values[98]	82	1			T435	7		T542	4		T672	1
values[99]	63	1			T435	2		T542	1		T672	1
values[100]	81	1			T435	2		T542	1		T672	1
values[101]	97	1			T435	5		T542	2		T672	1
values[102]	99	1			T435	2		T542	7		T672	1
values[103]	86	1			T435	3		T542	1		T672	1
values[104]	77	1			T435	1		T542	5		T672	1
values[105]	69	1			T435	1		T542	2		T672	2
values[106]	71	1			T435	6		T542	2		T672	2
values[107]	84	1			T435	1		T542	8		T672	4
values[108]	98	1			T435	1		T542	3		T672	1
values[109]	70	1			T435	4		T542	4		T672	1
values[110]	66	1			T435	3		T542	2		T672	3
values[111]	77	1			T435	1		T542	3		T672	3
values[112]	83	1			T435	2		T542	1		T672	4
values[113]	66	1			T435	1		T542	3		T672	1
values[114]	82	1			T435	3		T542	2		T672	1
values[115]	89	1			T435	2		T542	3		T672	2
values[116]	84	1			T435	3		T542	1		T672	1
values[117]	85	1			T435	2		T542	1		T672	1
values[118]	74	1			T435	1		T542	1		T672	2
values[119]	97	1			T435	2		T542	1		T672	8
values[120]	91	1			T435	2		T542	2		T672	3
values[121]	82	1			T435	3		T542	5		T672	1
values[122]	74	1			T435	1		T542	1		T672	1
values[123]	72	1			T435	2		T542	4		T672	1
values[124]	89	1			T435	1		T542	1		T672	3
values[125]	105	1			T435	2		T542	1		T672	1
values[126]	186	1			T435	2		T542	4		T672	2
values[127]	999	1			T435	27		T542	28		T672	27
values[128]	7724	1			T435	234		T542	260		T672	364