Unified Coverage Report :: Group :: xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

Group : xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	50	0	50	100.00

Variables for Group xbar_env_pkg::same_device_access_cg::SHAPE{(num_dev - 1)=49}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	50	0	50	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	50	0	50	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	489	1			T546	1		T815	1		T835	1
all_values[1]	456	1			T78	1		T84	2		T214	2
all_values[2]	482	1			T84	2		T424	1		T436	1
all_values[3]	469	1			T214	1		T541	6		T817	1
all_values[4]	482	1			T84	1		T436	1		T822	1
all_values[5]	444	1			T435	1		T542	1		T835	1
all_values[6]	496	1			T214	1		T424	1		T436	1
all_values[7]	476	1			T84	1		T435	1		T436	1
all_values[8]	460	1			T78	1		T84	1		T214	1
all_values[9]	466	1			T84	1		T542	1		T822	2
all_values[10]	435	1			T84	1		T424	1		T435	1
all_values[11]	472	1			T435	2		T835	1		T541	4
all_values[12]	460	1			T435	2		T436	2		T815	1
all_values[13]	483	1			T84	1		T214	1		T424	1
all_values[14]	458	1			T84	1		T214	1		T436	1
all_values[15]	461	1			T84	1		T436	1		T541	7
all_values[16]	468	1			T84	1		T424	1		T436	1
all_values[17]	466	1			T84	2		T436	1		T541	5
all_values[18]	470	1			T78	1		T84	1		T214	1
all_values[19]	439	1			T84	2		T436	1		T542	1
all_values[20]	448	1			T84	1		T214	1		T546	1
all_values[21]	498	1			T214	1		T541	3		T817	1
all_values[22]	504	1			T84	1		T214	1		T435	1
all_values[23]	493	1			T84	1		T424	1		T542	2
all_values[24]	495	1			T546	1		T436	1		T541	1
all_values[25]	474	1			T84	1		T546	1		T835	1
all_values[26]	437	1			T84	1		T424	1		T435	1
all_values[27]	471	1			T84	2		T436	1		T541	1
all_values[28]	501	1			T78	2		T214	2		T435	1
all_values[29]	481	1			T214	1		T541	2		T432	1
all_values[30]	477	1			T214	1		T435	1		T668	1
all_values[31]	450	1			T214	1		T546	1		T815	1
all_values[32]	500	1			T815	1		T668	1		T541	6
all_values[33]	470	1			T541	4		T432	1		T817	1
all_values[34]	436	1			T424	1		T546	1		T436	3
all_values[35]	504	1			T84	1		T214	1		T435	1
all_values[36]	442	1			T78	1		T214	1		T546	1
all_values[37]	506	1			T84	1		T542	1		T541	3
all_values[38]	505	1			T214	1		T424	1		T435	1
all_values[39]	493	1			T214	1		T435	1		T542	1
all_values[40]	534	1			T214	1		T435	1		T541	6
all_values[41]	493	1			T214	1		T424	1		T436	1
all_values[42]	464	1			T546	1		T542	1		T541	4
all_values[43]	463	1			T424	1		T436	2		T542	1
all_values[44]	456	1			T84	1		T214	1		T424	1
all_values[45]	479	1			T84	1		T435	1		T436	2
all_values[46]	482	1			T84	1		T214	1		T546	1
all_values[47]	472	1			T78	2		T84	1		T214	1
all_values[48]	501	1			T214	1		T436	1		T815	1
all_values[49]	471	1			T84	1		T542	1		T541	5