Unified Coverage Report :: Group :: xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

Group : xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_xbar_env_0.1/xbar_env_cov.sv

---

Summary for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group xbar_env_pkg::same_source_access_cg::SHAPE{(num_source - 1)=63}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dev	64	0	64	100.00	100	1	1	0

Summary for Variable cp_dev

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_dev

Excluded/Illegal bins

NAME	COUNT	STATUS
bin_others	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	3712	1			T78	1		T84	1		T214	1
all_values[1]	3600	1			T78	2		T84	2		T214	4
all_values[2]	3681	1			T78	8		T84	2		T214	5
all_values[3]	3539	1			T78	3		T84	3		T214	4
all_values[4]	3674	1			T78	4		T84	1		T214	3
all_values[5]	3550	1			T78	4		T84	1		T214	2
all_values[6]	3693	1			T78	1		T84	4		T214	4
all_values[7]	3582	1			T78	4		T84	1		T214	1
all_values[8]	3608	1			T78	3		T84	1		T214	1
all_values[9]	3560	1			T78	2		T84	1		T214	1
all_values[10]	3576	1			T78	2		T84	2		T214	6
all_values[11]	3602	1			T78	3		T84	2		T214	3
all_values[12]	3636	1			T84	3		T214	4		T258	2
all_values[13]	3693	1			T78	4		T258	3		T536	1
all_values[14]	3665	1			T78	4		T84	1		T214	5
all_values[15]	3651	1			T78	4		T84	4		T214	2
all_values[16]	3669	1			T78	1		T84	4		T214	5
all_values[17]	3691	1			T78	5		T84	2		T214	3
all_values[18]	3602	1			T84	1		T214	5		T495	4
all_values[19]	3729	1			T78	5		T84	1		T214	5
all_values[20]	3600	1			T78	3		T84	8		T214	4
all_values[21]	3568	1			T84	2		T214	5		T258	2
all_values[22]	3592	1			T78	1		T84	1		T214	5
all_values[23]	3679	1			T78	1		T84	4		T214	3
all_values[24]	3534	1			T78	3		T84	1		T214	7
all_values[25]	3659	1			T78	2		T84	2		T214	4
all_values[26]	3616	1			T78	3		T84	3		T214	2
all_values[27]	3626	1			T78	2		T84	4		T214	2
all_values[28]	3632	1			T78	9		T84	2		T214	1
all_values[29]	3678	1			T78	1		T214	4		T258	3
all_values[30]	3677	1			T78	4		T84	1		T214	7
all_values[31]	3578	1			T78	5		T84	4		T214	3
all_values[32]	3674	1			T78	1		T84	4		T214	4
all_values[33]	3548	1			T78	2		T84	1		T214	3
all_values[34]	3543	1			T78	1		T84	4		T214	3
all_values[35]	3582	1			T78	1		T84	2		T214	6
all_values[36]	3627	1			T78	4		T84	2		T214	2
all_values[37]	3717	1			T78	3		T84	2		T214	3
all_values[38]	3703	1			T78	3		T84	3		T214	5
all_values[39]	3607	1			T78	4		T84	4		T214	2
all_values[40]	3606	1			T78	7		T84	5		T214	6
all_values[41]	3654	1			T78	2		T84	1		T214	2
all_values[42]	3682	1			T78	3		T84	2		T214	6
all_values[43]	3619	1			T78	3		T84	4		T258	7
all_values[44]	3672	1			T78	2		T84	2		T214	2
all_values[45]	3678	1			T78	3		T84	1		T214	6
all_values[46]	3579	1			T78	2		T214	6		T536	1
all_values[47]	3489	1			T78	4		T214	2		T258	1
all_values[48]	3643	1			T78	6		T84	1		T214	3
all_values[49]	3649	1			T78	3		T84	4		T214	3
all_values[50]	3608	1			T78	2		T84	3		T214	4
all_values[51]	3683	1			T78	7		T84	2		T214	3
all_values[52]	3604	1			T78	1		T84	2		T214	4
all_values[53]	3499	1			T78	1		T84	1		T214	2
all_values[54]	3598	1			T78	1		T84	7		T214	5
all_values[55]	3591	1			T78	2		T84	3		T214	4
all_values[56]	3632	1			T78	4		T84	5		T214	5
all_values[57]	3541	1			T84	2		T214	4		T258	2
all_values[58]	3542	1			T78	5		T84	3		T214	6
all_values[59]	3671	1			T78	1		T84	2		T214	3
all_values[60]	3530	1			T78	2		T84	2		T214	2
all_values[61]	3696	1			T78	1		T84	2		T214	6
all_values[62]	3698	1			T78	2		T84	1		T214	6
all_values[63]	3742	1			T78	2		T84	1		T214	7