Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.hmac_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	151780	1			T77	2		T78	29		T79	11
values[2]	4288	1			T77	1		T553	1		T490	4
values[3]	2152	1			T571	1		T700	49		T610	2
values[4]	1636	1			T700	41		T528	1		T854	18
values[5]	1297	1			T700	52		T528	3		T854	11
values[6]	1163	1			T700	38		T528	4		T854	12
values[7]	900	1			T700	25		T528	3		T854	16
values[8]	757	1			T700	19		T528	1		T854	19
values[9]	626	1			T700	10		T528	1		T854	6
values[10]	596	1			T700	10		T528	3		T855	2
values[11]	596	1			T700	8		T528	1		T855	1
values[12]	629	1			T700	8		T528	5		T855	1
values[13]	540	1			T700	4		T528	2		T855	2
values[14]	417	1			T700	3		T528	1		T855	2
values[15]	303	1			T700	2		T528	1		T855	2
values[16]	260	1			T700	15		T528	4		T855	3
values[17]	281	1			T700	6		T528	2		T855	4
values[18]	345	1			T700	7		T528	3		T855	2
values[19]	368	1			T700	7		T528	3		T855	2
values[20]	384	1			T700	15		T528	2		T855	1
values[21]	353	1			T700	23		T528	5		T855	3
values[22]	317	1			T700	29		T528	4		T855	2
values[23]	256	1			T700	17		T528	3		T855	1
values[24]	258	1			T700	7		T528	6		T855	3
values[25]	249	1			T700	4		T528	5		T855	1
values[26]	176	1			T700	3		T528	2		T855	2
values[27]	128	1			T700	10		T528	2		T855	5
values[28]	117	1			T700	3		T528	1		T855	4
values[29]	99	1			T700	1		T528	1		T855	4
values[30]	110	1			T700	4		T528	3		T855	1
values[31]	114	1			T700	4		T528	4		T855	1
values[32]	108	1			T700	4		T528	5		T855	1
values[33]	85	1			T700	2		T528	4		T855	2
values[34]	87	1			T700	3		T528	6		T855	1
values[35]	122	1			T700	3		T528	7		T855	3
values[36]	114	1			T700	3		T528	4		T855	1
values[37]	114	1			T700	4		T528	6		T855	2
values[38]	106	1			T700	3		T528	7		T855	1
values[39]	96	1			T700	2		T528	4		T855	4
values[40]	121	1			T700	4		T528	3		T855	3
values[41]	109	1			T700	2		T528	3		T855	2
values[42]	87	1			T700	1		T528	2		T855	1
values[43]	76	1			T700	2		T528	4		T855	3
values[44]	81	1			T700	10		T528	8		T855	4
values[45]	77	1			T700	13		T528	3		T855	4
values[46]	66	1			T700	8		T528	3		T855	1
values[47]	80	1			T700	8		T528	1		T855	3
values[48]	86	1			T700	18		T528	2		T855	6
values[49]	89	1			T700	27		T528	1		T855	1
values[50]	97	1			T700	26		T528	5		T855	1
values[51]	99	1			T700	34		T528	4		T855	1
values[52]	97	1			T700	36		T528	2		T855	4
values[53]	92	1			T700	31		T528	3		T855	3
values[54]	82	1			T700	8		T528	3		T855	3
values[55]	76	1			T700	10		T528	1		T855	3
values[56]	83	1			T700	12		T528	5		T855	6
values[57]	76	1			T700	10		T528	1		T855	1
values[58]	66	1			T700	7		T528	4		T855	1
values[59]	75	1			T700	7		T528	5		T855	2
values[60]	68	1			T700	1		T528	2		T855	4
values[61]	70	1			T528	1		T855	4		T856	1
values[62]	64	1			T528	4		T855	3		T856	2
values[63]	60	1			T528	2		T855	3		T856	1
values[64]	67	1			T528	1		T855	1		T856	1
values[65]	79	1			T528	1		T855	3		T856	1
values[66]	62	1			T528	2		T855	1		T856	1
values[67]	65	1			T528	3		T855	1		T856	1
values[68]	59	1			T528	2		T855	1		T856	1
values[69]	81	1			T528	2		T855	6		T856	1
values[70]	88	1			T528	3		T855	7		T856	1
values[71]	84	1			T528	6		T855	5		T856	1
values[72]	71	1			T528	1		T855	1		T856	1
values[73]	84	1			T528	3		T855	2		T856	1
values[74]	80	1			T528	2		T855	2		T856	1
values[75]	81	1			T528	2		T855	2		T856	1
values[76]	83	1			T528	3		T855	2		T856	1
values[77]	90	1			T528	2		T855	2		T856	1
values[78]	100	1			T528	5		T855	2		T856	1
values[79]	91	1			T528	4		T855	1		T856	1
values[80]	73	1			T528	3		T855	1		T856	1
values[81]	86	1			T528	5		T855	2		T856	1
values[82]	86	1			T528	5		T855	1		T856	1
values[83]	92	1			T528	1		T855	1		T856	1
values[84]	94	1			T528	2		T855	2		T856	1
values[85]	111	1			T528	2		T855	2		T856	1
values[86]	91	1			T528	3		T855	3		T856	1
values[87]	86	1			T528	1		T855	3		T856	1
values[88]	99	1			T528	5		T855	1		T856	1
values[89]	117	1			T528	3		T855	1		T856	1
values[90]	125	1			T528	6		T855	4		T856	1
values[91]	89	1			T528	1		T855	3		T856	1
values[92]	111	1			T528	1		T855	3		T856	1
values[93]	98	1			T528	3		T855	2		T856	1
values[94]	105	1			T528	1		T855	3		T856	1
values[95]	119	1			T528	1		T855	3		T856	1
values[96]	100	1			T528	2		T855	2		T856	1
values[97]	96	1			T528	5		T855	2		T856	1
values[98]	97	1			T528	1		T855	2		T856	1
values[99]	96	1			T528	2		T855	4		T856	1
values[100]	103	1			T528	2		T855	4		T856	1
values[101]	130	1			T528	1		T855	4		T856	1
values[102]	112	1			T528	2		T855	1		T856	1
values[103]	95	1			T528	3		T855	2		T856	1
values[104]	100	1			T528	2		T855	6		T856	1
values[105]	95	1			T528	2		T855	1		T856	1
values[106]	97	1			T528	3		T855	1		T856	1
values[107]	117	1			T528	1		T855	3		T856	1
values[108]	122	1			T528	1		T855	5		T856	1
values[109]	135	1			T528	4		T855	6		T856	1
values[110]	117	1			T528	4		T855	5		T856	1
values[111]	112	1			T528	4		T855	2		T856	1
values[112]	117	1			T528	2		T855	1		T856	1
values[113]	123	1			T528	3		T855	4		T856	1
values[114]	110	1			T528	1		T855	1		T856	4
values[115]	135	1			T528	6		T855	3		T856	1
values[116]	125	1			T528	6		T855	4		T856	1
values[117]	111	1			T528	6		T855	6		T856	2
values[118]	117	1			T528	6		T855	6		T856	2
values[119]	108	1			T528	3		T855	3		T856	2
values[120]	144	1			T528	4		T855	2		T856	6
values[121]	130	1			T528	5		T855	6		T856	3
values[122]	125	1			T528	2		T855	10		T856	2
values[123]	139	1			T528	4		T855	6		T856	2
values[124]	218	1			T528	8		T855	17		T856	1
values[125]	408	1			T528	24		T855	45		T856	2
values[126]	918	1			T528	31		T855	78		T856	9
values[127]	3532	1			T528	21		T855	57		T856	98
values[128]	6285	1			T528	2		T855	6		T856	207