Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.14	95.47	94.02	95.38		94.92	97.53	99.52

Total tests in report: 2935

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
41.35	41.35	47.47	47.47	44.65	44.65	34.81	34.81			58.43	58.43	62.59	62.59	0.13	0.13	/workspace/coverage/default/2.chip_sw_power_virus.4005570263
50.92	9.57	53.21	5.75	60.79	16.14	35.17	0.36			69.28	10.86	85.66	23.08	1.37	1.25	/workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.26735090
56.21	5.30	65.22	12.00	68.89	8.10	36.01	0.83			80.13	10.85	85.66	0.00	1.37	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_0.3825285193
60.87	4.65	72.78	7.56	69.94	1.04	42.26	6.26			80.41	0.28	85.66	0.00	14.15	12.77	/workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2452701167
64.41	3.55	72.78	0.00	70.03	0.10	42.26	0.00			80.41	0.00	85.66	0.00	35.34	21.20	/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4102258687
67.87	3.45	75.49	2.71	72.01	1.97	51.61	9.35			82.82	2.42	89.86	4.20	35.40	0.06	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1562532191
70.39	2.52	80.44	4.95	75.86	3.85	54.89	3.28			84.47	1.65	91.26	1.40	35.40	0.00	/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.290175009
72.83	2.45	80.44	0.00	76.08	0.22	54.90	0.01			84.50	0.03	91.26	0.00	49.83	14.43	/workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2123788845
75.19	2.36	80.44	0.00	76.08	0.00	54.90	0.00			84.50	0.00	91.26	0.00	63.99	14.16	/workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.4065306851
77.33	2.13	80.44	0.00	76.08	0.00	67.70	12.80			84.50	0.00	91.26	0.00	63.99	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.869654124
79.20	1.87	82.24	1.80	78.01	1.93	73.59	5.89			85.74	1.23	91.61	0.35	63.99	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3020778275
80.84	1.65	86.13	3.89	80.89	2.88	73.84	0.25			88.60	2.86	91.61	0.00	63.99	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3551979010
82.23	1.39	86.13	0.00	81.05	0.17	73.84	0.00			88.63	0.03	91.61	0.00	72.13	8.14	/workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.1345116707
83.35	1.12	86.13	0.00	81.05	0.00	73.84	0.00			88.63	0.00	91.61	0.00	78.86	6.73	/workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.1113716050
84.45	1.09	86.34	0.21	81.16	0.11	79.54	5.70			88.81	0.18	91.96	0.35	78.86	0.00	/workspace/coverage/default/0.rom_raw_unlock.3659405056
85.34	0.90	87.60	1.26	81.90	0.74	81.27	1.73			89.88	1.07	92.31	0.35	79.10	0.23	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2828918834
86.23	0.89	88.52	0.92	82.14	0.24	81.29	0.01			90.17	0.29	96.15	3.85	79.10	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2608084843
87.06	0.83	88.52	0.00	82.93	0.79	81.29	0.00			90.22	0.04	96.15	0.00	83.27	4.17	/workspace/coverage/cover_reg_top/77.xbar_stress_all.3259766813
87.73	0.66	89.79	1.27	83.96	1.03	81.74	0.45			91.46	1.24	96.15	0.00	83.27	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_20.2909810243
88.36	0.64	89.79	0.00	84.02	0.06	81.74	0.00			91.46	0.00	96.15	0.00	87.03	3.76	/workspace/coverage/cover_reg_top/3.xbar_stress_all.2550451599
88.94	0.57	89.85	0.07	84.08	0.06	82.81	1.08			91.46	0.00	96.15	0.00	89.27	2.24	/workspace/coverage/default/0.chip_sw_alert_test.2244740157
89.43	0.49	90.18	0.33	84.87	0.79	83.95	1.14			92.15	0.70	96.15	0.00	89.27	0.00	/workspace/coverage/default/1.chip_jtag_csr_rw.2982757671
89.88	0.44	90.18	0.00	84.87	0.00	83.95	0.00			92.15	0.00	96.15	0.00	91.94	2.67	/workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.849413236
90.29	0.42	90.96	0.78	85.61	0.73	84.44	0.48			92.65	0.49	96.15	0.00	91.95	0.01	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382730917
90.69	0.40	90.96	0.00	85.65	0.04	84.44	0.00			92.65	0.00	96.15	0.00	94.30	2.35	/workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3608019666
91.02	0.33	90.97	0.01	87.53	1.89	84.44	0.00			92.65	0.00	96.15	0.00	94.36	0.06	/workspace/coverage/cover_reg_top/26.chip_tl_errors.3876944931
91.34	0.32	92.34	1.37	87.53	0.00	85.02	0.58			92.65	0.00	96.15	0.00	94.36	0.00	/workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.794150666
91.66	0.31	92.72	0.39	88.87	1.34	85.13	0.10			92.70	0.05	96.15	0.00	94.36	0.00	/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1835268691
91.95	0.30	93.25	0.52	89.31	0.44	85.48	0.36			93.16	0.46	96.15	0.00	94.36	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_10.722480689
92.24	0.29	93.25	0.00	89.32	0.01	87.19	1.71			93.16	0.00	96.15	0.00	94.36	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3602600753
92.49	0.25	93.25	0.00	89.32	0.00	87.19	0.00			93.16	0.00	96.15	0.00	95.89	1.53	/workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.1334011776
92.74	0.25	93.25	0.00	89.32	0.00	88.67	1.47			93.16	0.00	96.15	0.00	95.89	0.00	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3935443298
92.97	0.23	93.69	0.44	89.67	0.35	88.99	0.32			93.41	0.25	96.15	0.00	95.89	0.00	/workspace/coverage/default/0.chip_sw_gpio.1488586750
93.19	0.22	93.99	0.31	89.87	0.20	89.52	0.53			93.70	0.29	96.15	0.00	95.90	0.01	/workspace/coverage/default/0.rom_e2e_shutdown_output.4066706333
93.37	0.18	94.00	0.01	89.87	0.01	90.57	1.05			93.70	0.00	96.15	0.00	95.90	0.00	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1326929456
93.51	0.15	94.21	0.21	90.20	0.32	90.93	0.35			93.70	0.00	96.15	0.00	95.90	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2157312214
93.66	0.14	94.24	0.03	90.57	0.37	90.96	0.03			94.12	0.41	96.15	0.00	95.90	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1349352014
93.79	0.13	94.24	0.00	90.63	0.06	90.96	0.00			94.12	0.00	96.15	0.00	96.63	0.73	/workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.3230437220
93.92	0.13	94.24	0.00	90.75	0.12	90.96	0.00			94.13	0.02	96.15	0.00	97.27	0.65	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.107422174
94.04	0.12	94.24	0.00	90.75	0.00	91.65	0.69			94.13	0.00	96.15	0.00	97.31	0.04	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2812436424
94.16	0.12	94.24	0.00	90.75	0.00	91.73	0.08			94.13	0.00	96.15	0.00	97.93	0.62	/workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.3054503073
94.26	0.11	94.24	0.00	91.35	0.60	91.73	0.00			94.13	0.00	96.15	0.00	97.97	0.04	/workspace/coverage/cover_reg_top/16.chip_tl_errors.1619480350
94.36	0.10	94.24	0.00	91.35	0.01	92.31	0.58			94.13	0.00	96.15	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1204544923
94.44	0.08	94.39	0.15	91.46	0.11	92.40	0.08			94.26	0.12	96.15	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.985938773
94.51	0.08	94.39	0.00	91.47	0.01	92.85	0.45			94.26	0.00	96.15	0.00	97.97	0.00	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3323729601
94.58	0.07	94.39	0.00	91.47	0.00	93.27	0.42			94.26	0.00	96.15	0.00	97.97	0.00	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1864672827
94.65	0.07	94.47	0.07	91.47	0.00	93.59	0.32			94.26	0.01	96.15	0.00	97.97	0.00	/workspace/coverage/default/1.chip_tap_straps_testunlock0.842467600
94.72	0.07	94.47	0.00	91.65	0.19	93.59	0.00			94.47	0.21	96.15	0.00	97.97	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.4091393357
94.78	0.06	94.51	0.04	91.73	0.07	93.67	0.07			94.49	0.02	96.33	0.17	97.97	0.00	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3955988987
94.84	0.05	94.57	0.06	91.87	0.14	93.72	0.05			94.56	0.06	96.33	0.00	97.97	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.4165642272
94.88	0.04	94.61	0.04	91.89	0.01	93.73	0.01			94.56	0.01	96.50	0.17	97.98	0.01	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3852043525
94.92	0.04	94.61	0.00	92.15	0.26	93.73	0.00			94.56	0.00	96.50	0.00	97.98	0.00	/workspace/coverage/cover_reg_top/7.chip_tl_errors.3071515592
94.96	0.04	94.61	0.00	92.15	0.00	93.98	0.24			94.56	0.00	96.50	0.00	97.98	0.00	/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.121149921
95.00	0.04	94.62	0.01	92.16	0.01	93.98	0.00			94.59	0.02	96.68	0.17	97.99	0.01	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1288626798
95.04	0.04	94.62	0.00	92.17	0.01	93.98	0.00			94.59	0.00	96.68	0.00	98.21	0.22	/workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1652759759
95.08	0.04	94.62	0.00	92.21	0.04	93.98	0.00			94.60	0.01	96.85	0.17	98.21	0.00	/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2781313757
95.11	0.04	94.62	0.01	92.22	0.01	93.98	0.01			94.60	0.01	97.03	0.17	98.23	0.01	/workspace/coverage/default/36.chip_sw_all_escalation_resets.299744037
95.15	0.04	94.62	0.01	92.23	0.01	93.99	0.01			94.61	0.01	97.20	0.17	98.24	0.01	/workspace/coverage/default/52.chip_sw_all_escalation_resets.3941522794
95.19	0.04	94.63	0.01	92.24	0.01	93.99	0.00			94.62	0.01	97.38	0.17	98.25	0.01	/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3657474207
95.22	0.03	94.63	0.00	92.24	0.00	94.20	0.21			94.62	0.00	97.38	0.00	98.25	0.00	/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.781519201
95.25	0.03	94.64	0.01	92.25	0.01	94.35	0.16			94.63	0.01	97.38	0.00	98.25	0.00	/workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2408719672
95.28	0.03	94.64	0.00	92.38	0.12	94.35	0.00			94.66	0.03	97.38	0.00	98.27	0.02	/workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.908997973
95.31	0.03	94.64	0.00	92.38	0.00	94.36	0.01			94.66	0.00	97.55	0.17	98.27	0.00	/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1258522588
95.34	0.03	94.65	0.01	92.54	0.16	94.36	0.00			94.66	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.526733151
95.37	0.03	94.65	0.00	92.54	0.00	94.53	0.17			94.66	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3214692192
95.39	0.03	94.72	0.07	92.57	0.03	94.53	0.01			94.71	0.05	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3858407014
95.42	0.02	94.74	0.02	92.62	0.05	94.57	0.04			94.73	0.02	97.55	0.00	98.27	0.00	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3253210456
95.44	0.02	94.74	0.00	92.76	0.14	94.57	0.00			94.73	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_0.3819137786
95.46	0.02	94.74	0.00	92.89	0.13	94.57	0.00			94.73	0.00	97.55	0.00	98.27	0.00	/workspace/coverage/cover_reg_top/22.chip_tl_errors.1925252867
95.48	0.02	94.75	0.01	92.94	0.06	94.57	0.00			94.79	0.06	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.3649471914
95.50	0.02	94.80	0.05	92.99	0.05	94.58	0.01			94.81	0.02	97.55	0.00	98.27	0.00	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3945699647
95.52	0.02	94.82	0.01	93.04	0.05	94.59	0.01			94.84	0.03	97.55	0.00	98.27	0.00	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.263282964
95.54	0.02	94.82	0.00	93.10	0.06	94.59	0.00			94.87	0.03	97.55	0.00	98.30	0.02	/workspace/coverage/cover_reg_top/18.xbar_stress_all.398869002
95.56	0.02	94.82	0.00	93.21	0.11	94.59	0.00			94.87	0.00	97.55	0.00	98.30	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_20.2761233053
95.57	0.02	94.82	0.00	93.24	0.03	94.65	0.06			94.89	0.02	97.55	0.00	98.30	0.00	/workspace/coverage/default/0.chip_sw_spi_device_tpm.2443372186
95.59	0.02	94.82	0.00	93.25	0.01	94.65	0.00			94.89	0.00	97.55	0.00	98.38	0.08	/workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1166361615
95.60	0.02	94.82	0.00	93.25	0.00	94.75	0.09			94.89	0.00	97.55	0.00	98.38	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1809512424
95.62	0.01	94.82	0.00	93.25	0.00	94.75	0.00			94.89	0.00	97.55	0.00	98.46	0.08	/workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.563656938
95.63	0.01	94.82	0.00	93.33	0.08	94.75	0.00			94.89	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_plic_all_irqs_0.4031907559
95.64	0.01	94.82	0.00	93.33	0.00	94.82	0.07			94.89	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.500870249
95.66	0.01	94.82	0.00	93.40	0.07	94.82	0.00			94.89	0.00	97.55	0.00	98.46	0.00	/workspace/coverage/cover_reg_top/12.chip_tl_errors.670191127
95.67	0.01	94.82	0.00	93.40	0.00	94.82	0.00			94.89	0.00	97.55	0.00	98.53	0.07	/workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.3123080882
95.68	0.01	94.82	0.00	93.40	0.01	94.87	0.05			94.89	0.00	97.55	0.00	98.54	0.01	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1516600304
95.69	0.01	94.85	0.03	93.42	0.02	94.87	0.00			94.90	0.01	97.55	0.00	98.54	0.00	/workspace/coverage/default/1.chip_sw_sleep_pin_wake.692303723
95.70	0.01	94.85	0.00	93.47	0.05	94.87	0.00			94.90	0.00	97.55	0.00	98.54	0.00	/workspace/coverage/default/2.chip_plic_all_irqs_10.4060344544
95.71	0.01	94.85	0.00	93.49	0.02	94.87	0.00			94.90	0.00	97.55	0.00	98.58	0.04	/workspace/coverage/cover_reg_top/43.xbar_random.619015520
95.72	0.01	94.85	0.00	93.49	0.00	94.92	0.05			94.90	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.2987112239
95.72	0.01	94.85	0.00	93.49	0.00	94.97	0.05			94.90	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.1620319875
95.73	0.01	94.85	0.00	93.49	0.00	95.01	0.04			94.90	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.726908788
95.74	0.01	94.85	0.00	93.53	0.04	95.01	0.00			94.90	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/cover_reg_top/3.chip_tl_errors.3625339436
95.74	0.01	94.85	0.00	93.55	0.02	95.03	0.02			94.90	0.00	97.55	0.00	98.58	0.00	/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3046186303
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95.99	0.01	94.88	0.00	93.86	0.00	95.28	0.00			94.90	0.00	97.55	0.00	99.46	0.01	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2182751006
95.99	0.01	94.88	0.00	93.86	0.00	95.28	0.00			94.90	0.00	97.55	0.00	99.47	0.01	/workspace/coverage/default/81.chip_sw_all_escalation_resets.3901795348
95.99	0.01	94.88	0.00	93.86	0.00	95.28	0.00			94.90	0.00	97.55	0.00	99.48	0.01	/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.1190150323
96.00	0.01	94.88	0.00	93.86	0.00	95.28	0.00			94.90	0.00	97.55	0.00	99.49	0.01	/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1685553995
96.00	0.01	94.88	0.00	93.86	0.00	95.28	0.00			94.90	0.00	97.55	0.00	99.51	0.01	/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.755405162
96.00	0.01	94.88	0.00	93.86	0.00	95.28	0.00			94.90	0.00	97.55	0.00	99.52	0.01	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1812011381
96.00	0.01	94.88	0.00	93.87	0.01	95.28	0.00			94.91	0.01	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_sleep_pin_wake.3439226336
96.00	0.01	94.88	0.00	93.88	0.01	95.28	0.00			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/23.xbar_stress_all.214614757
96.01	0.01	94.88	0.00	93.89	0.01	95.28	0.00			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2548536299
96.01	0.01	94.88	0.00	93.90	0.01	95.28	0.00			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_plic_all_irqs_10.969047435
96.01	0.01	94.88	0.00	93.91	0.01	95.28	0.00			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.3424711367
96.01	0.01	94.89	0.01	93.91	0.00	95.29	0.01			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3656044467
96.01	0.01	94.89	0.00	93.91	0.00	95.29	0.01			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.2148253012
96.01	0.01	94.89	0.00	93.91	0.00	95.30	0.01			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2814743111
96.02	0.01	94.89	0.00	93.91	0.00	95.31	0.01			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1438934343
96.02	0.01	94.89	0.00	93.91	0.00	95.32	0.01			94.91	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.591990282
96.02	0.01	94.89	0.00	93.91	0.00	95.32	0.00			94.92	0.01	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_tap_straps_dev.1621858747
96.02	0.01	94.89	0.00	93.92	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1863082977
96.02	0.01	94.89	0.00	93.92	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.chip_tl_errors.1448672495
96.02	0.01	94.89	0.00	93.93	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2167349613
96.02	0.01	94.89	0.00	93.94	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.1200139949
96.02	0.01	94.89	0.00	93.94	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/8.chip_tl_errors.1500305220
96.03	0.01	94.89	0.00	93.95	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1482731946
96.03	0.01	94.89	0.00	93.96	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pattgen_ios.3171708004
96.03	0.01	94.89	0.00	93.96	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1301143683
96.03	0.01	94.89	0.00	93.97	0.01	95.32	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3515962630
96.03	0.01	94.89	0.00	93.97	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.501991608
96.03	0.01	94.89	0.00	93.98	0.01	95.33	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_power_idle_load.3958930235
96.03	0.01	94.89	0.01	93.98	0.00	95.33	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3903316019
96.03	0.01	94.89	0.00	93.98	0.00	95.34	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2910708501
96.03	0.01	94.89	0.00	93.98	0.00	95.34	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.854186742
96.03	0.01	94.89	0.00	93.98	0.00	95.35	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.2061496238
96.03	0.01	94.89	0.00	93.98	0.00	95.35	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2727572327
96.04	0.01	94.89	0.00	93.98	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.3714750373
96.04	0.01	94.89	0.00	93.98	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.118264877
96.04	0.01	94.89	0.00	93.99	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.3873586453
96.04	0.01	94.89	0.00	93.99	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.2782952630
96.04	0.01	94.89	0.00	93.99	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.2634591455
96.04	0.01	94.89	0.00	94.00	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2227135851
96.04	0.01	94.89	0.00	94.00	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.1976054283
96.04	0.01	94.89	0.00	94.00	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2868668536
96.04	0.01	94.89	0.00	94.01	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.3045486506
96.04	0.01	94.89	0.00	94.01	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.856206380
96.04	0.01	94.89	0.00	94.01	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.213747915
96.04	0.01	94.89	0.00	94.02	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4197483939
96.04	0.01	94.89	0.00	94.02	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1767049758
96.04	0.01	94.89	0.00	94.02	0.01	95.35	0.00			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_gpio.833843169
96.04	0.01	94.89	0.00	94.02	0.00	95.36	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/3.chip_tap_straps_rma.1789483276
96.04	0.01	94.89	0.00	94.02	0.00	95.36	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.541042068
96.04	0.01	94.89	0.00	94.02	0.00	95.36	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3832277558
96.04	0.01	94.89	0.00	94.02	0.00	95.36	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/cover_reg_top/58.xbar_random.3561237250
96.05	0.01	94.89	0.00	94.02	0.00	95.37	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3897020736
96.05	0.01	94.89	0.00	94.02	0.00	95.37	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_edn_boot_mode.1911663591
96.05	0.01	94.89	0.00	94.02	0.00	95.37	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.4252536399
96.05	0.01	94.89	0.00	94.02	0.00	95.37	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.817793748
96.05	0.01	94.89	0.00	94.02	0.00	95.38	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2838386377
96.05	0.01	94.89	0.00	94.02	0.00	95.38	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1724355444
96.05	0.01	94.89	0.00	94.02	0.00	95.38	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3624973593
96.05	0.01	94.89	0.00	94.02	0.00	95.38	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3547810879
96.05	0.01	94.89	0.00	94.02	0.00	95.38	0.01			94.92	0.00	97.55	0.00	99.52	0.00	/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1470472564

---

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3390300472
/workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.4176299918
/workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.804627162
/workspace/coverage/cover_reg_top/0.chip_csr_rw.3447882184
/workspace/coverage/cover_reg_top/0.chip_prim_tl_access.965177069
/workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1180084011
/workspace/coverage/cover_reg_top/0.xbar_access_same_device.2615058378
/workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.4006055486
/workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.405367348
/workspace/coverage/cover_reg_top/0.xbar_error_random.2818581831
/workspace/coverage/cover_reg_top/0.xbar_random.3462921636
/workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2664766740
/workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.3811125433
/workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2325156331
/workspace/coverage/cover_reg_top/0.xbar_same_source.804274347
/workspace/coverage/cover_reg_top/0.xbar_smoke.1207192045
/workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.1742923726
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3656950001
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.650833371
/workspace/coverage/cover_reg_top/0.xbar_stress_all.4207412036
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3772582177
/workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.1330288650
/workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2808155973
/workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.1031724758
/workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.1762009302
/workspace/coverage/cover_reg_top/1.chip_csr_rw.813892530
/workspace/coverage/cover_reg_top/1.chip_prim_tl_access.324374042
/workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.1445438410
/workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.3987969466
/workspace/coverage/cover_reg_top/1.chip_tl_errors.1624219871
/workspace/coverage/cover_reg_top/1.xbar_access_same_device.751995905
/workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.3196897086
/workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.3656073195
/workspace/coverage/cover_reg_top/1.xbar_error_random.23719293
/workspace/coverage/cover_reg_top/1.xbar_random.128219342
/workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2472339224
/workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1283313313
/workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.2536812195
/workspace/coverage/cover_reg_top/1.xbar_same_source.2553518552
/workspace/coverage/cover_reg_top/1.xbar_smoke.440297728
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.1774278742
/workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.2187279479
/workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.2482162671
/workspace/coverage/cover_reg_top/1.xbar_stress_all.1571093652
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.341740263
/workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.1594954737
/workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.1376559211
/workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4201256888
/workspace/coverage/cover_reg_top/10.chip_csr_rw.1038399309
/workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1182440837
/workspace/coverage/cover_reg_top/10.chip_tl_errors.3619109305
/workspace/coverage/cover_reg_top/10.xbar_access_same_device.2816080794
/workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.2370207508
/workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.3337937504
/workspace/coverage/cover_reg_top/10.xbar_error_random.4209638384
/workspace/coverage/cover_reg_top/10.xbar_random.1573254387
/workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3623712832
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.495392024
/workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1030857195
/workspace/coverage/cover_reg_top/10.xbar_same_source.1270128730
/workspace/coverage/cover_reg_top/10.xbar_smoke.3628241251
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.1610489673
/workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.2692321129
/workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.318082996
/workspace/coverage/cover_reg_top/10.xbar_stress_all.2246618944
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.609341095
/workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.4200124825
/workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.294971649
/workspace/coverage/cover_reg_top/11.chip_csr_rw.1490077140
/workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.81391643
/workspace/coverage/cover_reg_top/11.xbar_access_same_device.2145467360
/workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.18350911
/workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.2232273680
/workspace/coverage/cover_reg_top/11.xbar_error_random.513698031
/workspace/coverage/cover_reg_top/11.xbar_random.3854354628
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.4291860372
/workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.4115325912
/workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.3835470282
/workspace/coverage/cover_reg_top/11.xbar_same_source.63967501
/workspace/coverage/cover_reg_top/11.xbar_smoke.1260086480
/workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.288161178
/workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1662552639
/workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.3144749165
/workspace/coverage/cover_reg_top/11.xbar_stress_all.2013409842
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.3252626143
/workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2349749310
/workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.200669345
/workspace/coverage/cover_reg_top/12.chip_csr_rw.655020284
/workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2873640267
/workspace/coverage/cover_reg_top/12.xbar_access_same_device.567259941
/workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.2001602396
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/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.865620902
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.876909283
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/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.1533965936
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.4010066729
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/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762287904
/workspace/coverage/default/31.chip_sw_all_escalation_resets.3286399245
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2980990978
/workspace/coverage/default/34.chip_sw_all_escalation_resets.2513405468
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3255992678
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3480837715
/workspace/coverage/default/37.chip_sw_all_escalation_resets.2956582523
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3847116329
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3431782875
/workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.4271497850
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/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1704474562
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.685269052
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2821232339
/workspace/coverage/default/4.chip_sw_uart_tx_rx.903692274
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.510383877
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/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2011093136
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.478791899
/workspace/coverage/default/4.chip_tap_straps_dev.3637491610
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/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3486716199
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2949709363
/workspace/coverage/default/42.chip_sw_all_escalation_resets.363177597
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031822419
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1714702196
/workspace/coverage/default/44.chip_sw_all_escalation_resets.3431636492
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469881181
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.207294885
/workspace/coverage/default/47.chip_sw_all_escalation_resets.579025291
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2912315943
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.556219642
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.1902063945
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2687422801
/workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.836346039
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.80351070
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.1877562602
/workspace/coverage/default/50.chip_sw_all_escalation_resets.230725976
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.4273933943
/workspace/coverage/default/51.chip_sw_all_escalation_resets.3273040574
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2338223713
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2964878924
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.3346536421
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.3728163735
/workspace/coverage/default/55.chip_sw_all_escalation_resets.3578056554
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2816460748
/workspace/coverage/default/56.chip_sw_all_escalation_resets.457495679
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1458739796
/workspace/coverage/default/57.chip_sw_all_escalation_resets.3036237975
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1273604074
/workspace/coverage/default/58.chip_sw_all_escalation_resets.1608834074
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.60101872
/workspace/coverage/default/59.chip_sw_all_escalation_resets.917728186
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363014200
/workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1581562409
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2136993702
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2807298361
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.670337611
/workspace/coverage/default/60.chip_sw_all_escalation_resets.2099730730
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2467325627
/workspace/coverage/default/61.chip_sw_all_escalation_resets.162550773
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2276043282
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2812955369
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1837850472
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3739036120
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2046786312
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2963400256
/workspace/coverage/default/65.chip_sw_all_escalation_resets.2774274498
/workspace/coverage/default/66.chip_sw_all_escalation_resets.259092073
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.4192918384
/workspace/coverage/default/67.chip_sw_all_escalation_resets.269073357
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1449277360
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2759182770
/workspace/coverage/default/69.chip_sw_all_escalation_resets.1893418006
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1104621374
/workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.2306622910
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.790806304
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2295906847
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2134153293
/workspace/coverage/default/71.chip_sw_all_escalation_resets.2611145596
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3768126746
/workspace/coverage/default/72.chip_sw_all_escalation_resets.43905456
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1809524935
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1953428363
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.3960461121
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2243283309
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.311118844
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1329030868
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2055723196
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.952434023
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1501210434
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233436387
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.2235610722
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2342994411
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3435834534
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.2216687476
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.4283902533
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3357931521
/workspace/coverage/default/82.chip_sw_all_escalation_resets.467648704
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120288406
/workspace/coverage/default/83.chip_sw_all_escalation_resets.1156392503
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1801976293
/workspace/coverage/default/84.chip_sw_all_escalation_resets.1307222841
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4100955564
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1630745083
/workspace/coverage/default/86.chip_sw_all_escalation_resets.4084573545
/workspace/coverage/default/87.chip_sw_all_escalation_resets.388748259
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.1108859869
/workspace/coverage/default/88.chip_sw_all_escalation_resets.3073007986
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3648096183
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1782675918
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.4030246334
/workspace/coverage/default/9.chip_sw_all_escalation_resets.1883692529
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.234807088
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.525930656
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.370119368
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2213302663
/workspace/coverage/default/91.chip_sw_all_escalation_resets.2463686265
/workspace/coverage/default/92.chip_sw_all_escalation_resets.627741631
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2094192629
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2542057638
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1225771143
/workspace/coverage/default/97.chip_sw_all_escalation_resets.1966230265
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3106896735
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1477251174
/workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1961797458
/workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.3750462931
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.3640869915
/workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1122613393
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2845217819
/workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3641456681
/workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.4106650320
/workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.729425815

---

Total test records in report: 2935

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2828918834			Aug 02 08:37:41 PM PDT 24	Aug 02 08:48:53 PM PDT 24	5174264656 ps
T2	/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.723582272			Aug 02 08:37:49 PM PDT 24	Aug 02 08:44:07 PM PDT 24	3627184248 ps
T3	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.3020778275			Aug 02 08:27:53 PM PDT 24	Aug 02 09:19:25 PM PDT 24	12196272130 ps
T35	/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2405186539			Aug 02 08:21:45 PM PDT 24	Aug 02 08:33:13 PM PDT 24	5189270488 ps
T4	/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2105462387			Aug 02 08:35:17 PM PDT 24	Aug 02 08:51:01 PM PDT 24	5238455772 ps
T11	/workspace/coverage/default/2.chip_sw_power_virus.4005570263			Aug 02 08:46:55 PM PDT 24	Aug 02 09:09:16 PM PDT 24	6065749886 ps
T88	/workspace/coverage/default/0.chip_sw_kmac_app_rom.877987690			Aug 02 08:19:46 PM PDT 24	Aug 02 08:23:57 PM PDT 24	3382224440 ps
T89	/workspace/coverage/default/2.chip_sw_otbn_smoketest.3258261136			Aug 02 08:42:25 PM PDT 24	Aug 02 09:03:19 PM PDT 24	6729439744 ps
T63	/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382730917			Aug 02 08:46:00 PM PDT 24	Aug 02 08:51:36 PM PDT 24	3160422584 ps
T5	/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1204544923			Aug 02 08:19:09 PM PDT 24	Aug 02 08:36:06 PM PDT 24	10195001738 ps
T62	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2727572327			Aug 02 08:18:44 PM PDT 24	Aug 02 08:27:40 PM PDT 24	7707110320 ps
T317	/workspace/coverage/default/2.chip_sw_kmac_idle.2625783285			Aug 02 08:38:54 PM PDT 24	Aug 02 08:42:34 PM PDT 24	2921764632 ps
T116	/workspace/coverage/default/2.chip_sw_clkmgr_jitter.547500642			Aug 02 08:39:51 PM PDT 24	Aug 02 08:42:43 PM PDT 24	2738904079 ps
T212	/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3253210456			Aug 02 08:45:47 PM PDT 24	Aug 02 09:08:57 PM PDT 24	8280963470 ps
T85	/workspace/coverage/default/1.chip_sw_alert_handler_entropy.2812436424			Aug 02 08:29:03 PM PDT 24	Aug 02 08:34:55 PM PDT 24	3344384982 ps
T17	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1562532191			Aug 02 08:40:04 PM PDT 24	Aug 02 09:03:15 PM PDT 24	22944783602 ps
T105	/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.838163385			Aug 02 08:21:15 PM PDT 24	Aug 02 08:28:44 PM PDT 24	3867406560 ps
T106	/workspace/coverage/default/0.chip_sw_pattgen_ios.3171708004			Aug 02 08:17:19 PM PDT 24	Aug 02 08:21:27 PM PDT 24	2835565216 ps
T39	/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1472190369			Aug 02 08:37:44 PM PDT 24	Aug 02 08:45:20 PM PDT 24	5149559772 ps
T51	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2428001824			Aug 02 08:19:26 PM PDT 24	Aug 02 08:29:53 PM PDT 24	4289918190 ps
T6	/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3602600753			Aug 02 08:28:36 PM PDT 24	Aug 02 08:37:10 PM PDT 24	4161644025 ps
T7	/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3634392734			Aug 02 08:34:24 PM PDT 24	Aug 02 11:45:44 PM PDT 24	65244550559 ps
T64	/workspace/coverage/default/1.chip_sw_all_escalation_resets.3472994534			Aug 02 08:25:39 PM PDT 24	Aug 02 08:37:38 PM PDT 24	6211970046 ps
T107	/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2903579201			Aug 02 08:30:31 PM PDT 24	Aug 02 08:43:44 PM PDT 24	7550463400 ps
T108	/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3692554385			Aug 02 08:30:13 PM PDT 24	Aug 02 08:39:46 PM PDT 24	4036574584 ps
T65	/workspace/coverage/default/31.chip_sw_all_escalation_resets.3286399245			Aug 02 08:49:38 PM PDT 24	Aug 02 08:59:58 PM PDT 24	5467350430 ps
T117	/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.118170360			Aug 02 08:20:06 PM PDT 24	Aug 02 08:23:50 PM PDT 24	2892517906 ps
T70	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.774778520			Aug 02 08:20:48 PM PDT 24	Aug 02 08:30:37 PM PDT 24	4433746144 ps
T49	/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.4187657437			Aug 02 08:48:55 PM PDT 24	Aug 02 08:57:51 PM PDT 24	6748020041 ps
T298	/workspace/coverage/default/2.chip_sw_hmac_oneshot.2474645656			Aug 02 08:38:23 PM PDT 24	Aug 02 08:45:39 PM PDT 24	3145590816 ps
T299	/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3233436387			Aug 02 08:54:29 PM PDT 24	Aug 02 08:59:06 PM PDT 24	3717122136 ps
T46	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2804170712			Aug 02 08:27:35 PM PDT 24	Aug 02 09:29:39 PM PDT 24	15007783616 ps
T60	/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3945699647			Aug 02 08:34:42 PM PDT 24	Aug 02 08:39:23 PM PDT 24	3862576710 ps
T47	/workspace/coverage/default/0.rom_e2e_shutdown_output.4066706333			Aug 02 08:26:10 PM PDT 24	Aug 02 09:19:38 PM PDT 24	24205279108 ps
T178	/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.1700617716			Aug 02 08:21:05 PM PDT 24	Aug 02 08:34:49 PM PDT 24	7917498316 ps
T429	/workspace/coverage/default/2.chip_sw_example_rom.3273325894			Aug 02 08:33:37 PM PDT 24	Aug 02 08:36:13 PM PDT 24	2613514280 ps
T179	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2346265925			Aug 02 08:39:46 PM PDT 24	Aug 02 08:55:11 PM PDT 24	8786031644 ps
T69	/workspace/coverage/default/1.chip_tap_straps_testunlock0.842467600			Aug 02 08:30:35 PM PDT 24	Aug 02 08:34:33 PM PDT 24	3437383914 ps
T430	/workspace/coverage/default/2.chip_sw_aes_entropy.1641505135			Aug 02 08:37:22 PM PDT 24	Aug 02 08:41:10 PM PDT 24	2544571464 ps
T122	/workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3144428911			Aug 02 08:42:57 PM PDT 24	Aug 02 09:13:57 PM PDT 24	8816174330 ps
T431	/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3082208571			Aug 02 08:23:00 PM PDT 24	Aug 02 08:25:39 PM PDT 24	2807142572 ps
T432	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2492747619			Aug 02 08:18:51 PM PDT 24	Aug 02 08:27:27 PM PDT 24	8735544540 ps
T365	/workspace/coverage/default/78.chip_sw_all_escalation_resets.1516600304			Aug 02 08:54:14 PM PDT 24	Aug 02 09:02:33 PM PDT 24	5615314926 ps
T257	/workspace/coverage/default/2.chip_sw_plic_sw_irq.3681610594			Aug 02 08:41:02 PM PDT 24	Aug 02 08:46:55 PM PDT 24	2491470008 ps
T361	/workspace/coverage/default/48.chip_sw_all_escalation_resets.2912315943			Aug 02 08:51:24 PM PDT 24	Aug 02 09:01:50 PM PDT 24	4643271876 ps
T155	/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2518520771			Aug 02 08:18:41 PM PDT 24	Aug 02 08:20:18 PM PDT 24	2271180013 ps
T216	/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1896502622			Aug 02 08:47:51 PM PDT 24	Aug 02 08:56:53 PM PDT 24	3927652870 ps
T914	/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3997749102			Aug 02 08:44:33 PM PDT 24	Aug 02 08:53:01 PM PDT 24	6405327720 ps
T362	/workspace/coverage/default/75.chip_sw_all_escalation_resets.4021629462			Aug 02 08:55:45 PM PDT 24	Aug 02 09:06:36 PM PDT 24	5578501200 ps
T915	/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1373352890			Aug 02 08:32:55 PM PDT 24	Aug 02 08:38:45 PM PDT 24	5233762676 ps
T545	/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.723525722			Aug 02 08:51:36 PM PDT 24	Aug 02 08:58:31 PM PDT 24	3845924168 ps
T71	/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2991543041			Aug 02 08:30:36 PM PDT 24	Aug 02 08:36:38 PM PDT 24	3179055000 ps
T166	/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3935443298			Aug 02 08:41:43 PM PDT 24	Aug 02 09:10:38 PM PDT 24	17939584927 ps
T162	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.906237149			Aug 02 08:40:54 PM PDT 24	Aug 02 09:03:00 PM PDT 24	6878074760 ps
T333	/workspace/coverage/default/46.chip_sw_all_escalation_resets.1571313604			Aug 02 08:50:00 PM PDT 24	Aug 02 09:00:56 PM PDT 24	5399071862 ps
T363	/workspace/coverage/default/25.chip_sw_all_escalation_resets.4122659123			Aug 02 08:48:24 PM PDT 24	Aug 02 08:58:25 PM PDT 24	5915814558 ps
T169	/workspace/coverage/default/2.rom_e2e_smoke.2732619103			Aug 02 08:47:25 PM PDT 24	Aug 02 09:38:32 PM PDT 24	14630812456 ps
T220	/workspace/coverage/default/1.rom_keymgr_functest.4132183832			Aug 02 08:32:56 PM PDT 24	Aug 02 08:42:18 PM PDT 24	4602149592 ps
T436	/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.602031363			Aug 02 08:26:53 PM PDT 24	Aug 02 08:31:55 PM PDT 24	3845563016 ps
T111	/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1635792655			Aug 02 08:40:29 PM PDT 24	Aug 02 08:52:38 PM PDT 24	19900460320 ps
T118	/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2002514183			Aug 02 08:31:17 PM PDT 24	Aug 02 08:35:19 PM PDT 24	2884592307 ps
T153	/workspace/coverage/default/7.chip_sw_all_escalation_resets.1104621374			Aug 02 08:45:15 PM PDT 24	Aug 02 08:56:17 PM PDT 24	4838915744 ps
T247	/workspace/coverage/default/29.chip_sw_all_escalation_resets.3852043525			Aug 02 08:50:13 PM PDT 24	Aug 02 09:02:23 PM PDT 24	6727991382 ps
T50	/workspace/coverage/default/0.rom_raw_unlock.3659405056			Aug 02 08:23:16 PM PDT 24	Aug 02 08:27:53 PM PDT 24	6683287521 ps
T274	/workspace/coverage/default/2.chip_sw_aes_masking_off.2146769625			Aug 02 08:38:52 PM PDT 24	Aug 02 08:45:10 PM PDT 24	3131523371 ps
T206	/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.954387310			Aug 02 08:19:43 PM PDT 24	Aug 02 08:24:11 PM PDT 24	2785901344 ps
T275	/workspace/coverage/default/1.chip_sw_flash_crash_alert.3241921418			Aug 02 08:32:30 PM PDT 24	Aug 02 08:43:32 PM PDT 24	5115007676 ps
T276	/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4013729665			Aug 02 08:17:57 PM PDT 24	Aug 02 08:30:04 PM PDT 24	4175299084 ps
T18	/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1335327803			Aug 02 08:22:04 PM PDT 24	Aug 02 08:48:46 PM PDT 24	21749891426 ps
T277	/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.79694806			Aug 02 08:47:09 PM PDT 24	Aug 02 08:54:22 PM PDT 24	3982533828 ps
T278	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3328166716			Aug 02 08:20:29 PM PDT 24	Aug 02 08:32:44 PM PDT 24	3703493013 ps
T48	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.1363141490			Aug 02 08:26:30 PM PDT 24	Aug 02 09:42:27 PM PDT 24	14706487570 ps
T764	/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3486716199			Aug 02 08:50:36 PM PDT 24	Aug 02 08:56:57 PM PDT 24	4187094522 ps
T398	/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120288406			Aug 02 08:54:26 PM PDT 24	Aug 02 09:00:43 PM PDT 24	3352561550 ps
T916	/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.2708856438			Aug 02 08:40:19 PM PDT 24	Aug 02 08:51:05 PM PDT 24	7400786122 ps
T119	/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1422648333			Aug 02 08:18:40 PM PDT 24	Aug 02 08:29:39 PM PDT 24	4917496818 ps
T352	/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.3469168590			Aug 02 08:31:12 PM PDT 24	Aug 02 08:39:24 PM PDT 24	4029631220 ps
T19	/workspace/coverage/default/0.chip_sw_usbdev_pullup.379913651			Aug 02 08:17:33 PM PDT 24	Aug 02 08:22:08 PM PDT 24	3075971092 ps
T262	/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.311851415			Aug 02 08:27:46 PM PDT 24	Aug 02 08:35:00 PM PDT 24	5333429180 ps
T373	/workspace/coverage/default/12.chip_sw_all_escalation_resets.2766554001			Aug 02 08:47:09 PM PDT 24	Aug 02 09:00:08 PM PDT 24	4962196724 ps
T692	/workspace/coverage/default/9.chip_sw_all_escalation_resets.1883692529			Aug 02 08:48:07 PM PDT 24	Aug 02 09:00:37 PM PDT 24	5394662200 ps
T145	/workspace/coverage/default/1.chip_sw_otbn_smoketest.1577453034			Aug 02 08:32:50 PM PDT 24	Aug 02 09:08:47 PM PDT 24	9244961960 ps
T267	/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1016146220			Aug 02 08:27:47 PM PDT 24	Aug 02 09:22:50 PM PDT 24	15007587142 ps
T268	/workspace/coverage/default/54.chip_sw_all_escalation_resets.3656044467			Aug 02 08:51:27 PM PDT 24	Aug 02 08:59:23 PM PDT 24	5417267544 ps
T917	/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.503902570			Aug 02 08:25:21 PM PDT 24	Aug 02 08:30:54 PM PDT 24	4107024800 ps
T918	/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1083460881			Aug 02 08:23:33 PM PDT 24	Aug 02 08:27:26 PM PDT 24	2601335000 ps
T370	/workspace/coverage/default/34.chip_sw_all_escalation_resets.2513405468			Aug 02 08:49:22 PM PDT 24	Aug 02 09:01:22 PM PDT 24	4682726080 ps
T410	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.3336279513			Aug 02 08:29:30 PM PDT 24	Aug 02 09:30:40 PM PDT 24	13992381667 ps
T414	/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909042288			Aug 02 08:51:04 PM PDT 24	Aug 02 08:57:27 PM PDT 24	4035602566 ps
T158	/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3339148685			Aug 02 08:41:21 PM PDT 24	Aug 02 08:43:18 PM PDT 24	2439356211 ps
T20	/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2001590745			Aug 02 08:21:41 PM PDT 24	Aug 02 08:46:46 PM PDT 24	22534616760 ps
T704	/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1786782450			Aug 02 08:26:18 PM PDT 24	Aug 02 08:32:56 PM PDT 24	6060727939 ps
T729	/workspace/coverage/default/94.chip_sw_all_escalation_resets.2094192629			Aug 02 08:54:38 PM PDT 24	Aug 02 09:04:56 PM PDT 24	5795000520 ps
T196	/workspace/coverage/default/2.chip_tap_straps_prod.227289029			Aug 02 08:40:53 PM PDT 24	Aug 02 08:43:34 PM PDT 24	3065686261 ps
T75	/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.263282964			Aug 02 08:18:37 PM PDT 24	Aug 02 08:25:11 PM PDT 24	3836582184 ps
T919	/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.447033899			Aug 02 08:23:41 PM PDT 24	Aug 02 08:29:49 PM PDT 24	3088997704 ps
T210	/workspace/coverage/default/45.chip_sw_all_escalation_resets.2912944854			Aug 02 08:49:51 PM PDT 24	Aug 02 09:00:26 PM PDT 24	4968375018 ps
T120	/workspace/coverage/default/0.chip_sw_edn_auto_mode.367824456			Aug 02 08:21:08 PM PDT 24	Aug 02 08:38:29 PM PDT 24	4533535300 ps
T728	/workspace/coverage/default/39.chip_sw_all_escalation_resets.2247808316			Aug 02 08:50:55 PM PDT 24	Aug 02 08:59:45 PM PDT 24	5155904852 ps
T404	/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.4216091807			Aug 02 08:19:34 PM PDT 24	Aug 02 08:28:36 PM PDT 24	4502802920 ps
T920	/workspace/coverage/default/1.chip_sw_uart_smoketest.441366610			Aug 02 08:32:56 PM PDT 24	Aug 02 08:37:45 PM PDT 24	3533687724 ps
T221	/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.155261479			Aug 02 08:38:45 PM PDT 24	Aug 02 08:52:59 PM PDT 24	6843117944 ps
T154	/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3768126746			Aug 02 08:53:07 PM PDT 24	Aug 02 08:58:43 PM PDT 24	3811385498 ps
T217	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1604493097			Aug 02 08:17:55 PM PDT 24	Aug 02 08:26:02 PM PDT 24	3991406659 ps
T411	/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3435834534			Aug 02 08:47:15 PM PDT 24	Aug 02 10:18:39 PM PDT 24	22083168544 ps
T446	/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3049104428			Aug 02 08:30:03 PM PDT 24	Aug 02 08:36:00 PM PDT 24	3352267508 ps
T921	/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2941930821			Aug 02 08:19:57 PM PDT 24	Aug 02 08:28:02 PM PDT 24	4969646528 ps
T86	/workspace/coverage/default/0.chip_sw_alert_handler_entropy.60313388			Aug 02 08:18:54 PM PDT 24	Aug 02 08:24:57 PM PDT 24	4025300531 ps
T735	/workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1304188381			Aug 02 08:18:53 PM PDT 24	Aug 02 08:40:20 PM PDT 24	8376358220 ps
T263	/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1957265984			Aug 02 08:36:13 PM PDT 24	Aug 02 08:56:00 PM PDT 24	7515858260 ps
T14	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3168536604			Aug 02 08:43:44 PM PDT 24	Aug 02 09:11:18 PM PDT 24	8575047979 ps
T747	/workspace/coverage/default/16.chip_sw_all_escalation_resets.2839141301			Aug 02 08:47:46 PM PDT 24	Aug 02 08:57:53 PM PDT 24	4134541526 ps
T754	/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3847116329			Aug 02 08:51:15 PM PDT 24	Aug 02 08:57:52 PM PDT 24	3890274954 ps
T922	/workspace/coverage/default/2.chip_sw_example_flash.2504141116			Aug 02 08:33:45 PM PDT 24	Aug 02 08:38:02 PM PDT 24	3143170650 ps
T121	/workspace/coverage/default/0.chip_sw_edn_kat.1827995665			Aug 02 08:18:50 PM PDT 24	Aug 02 08:27:05 PM PDT 24	3573386052 ps
T264	/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1767049758			Aug 02 08:19:54 PM PDT 24	Aug 02 08:35:40 PM PDT 24	4611663320 ps
T371	/workspace/coverage/default/6.chip_sw_all_escalation_resets.1374048956			Aug 02 08:46:54 PM PDT 24	Aug 02 08:57:24 PM PDT 24	5470310478 ps
T115	/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1809512424			Aug 02 08:21:54 PM PDT 24	Aug 02 08:56:06 PM PDT 24	11175925229 ps
T755	/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1762287904			Aug 02 08:49:13 PM PDT 24	Aug 02 08:54:57 PM PDT 24	3685750368 ps
T353	/workspace/coverage/default/2.chip_sw_aon_timer_irq.3988452988			Aug 02 08:36:29 PM PDT 24	Aug 02 08:46:23 PM PDT 24	4726127488 ps
T320	/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.556219642			Aug 02 08:51:44 PM PDT 24	Aug 02 09:00:31 PM PDT 24	3972473192 ps
T327	/workspace/coverage/default/2.chip_sw_flash_crash_alert.2288265389			Aug 02 08:40:59 PM PDT 24	Aug 02 08:54:51 PM PDT 24	6103342086 ps
T223	/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3507680051			Aug 02 08:28:24 PM PDT 24	Aug 02 08:39:27 PM PDT 24	5227571052 ps
T328	/workspace/coverage/default/2.chip_plic_all_irqs_0.3825285193			Aug 02 08:41:28 PM PDT 24	Aug 02 09:02:45 PM PDT 24	6030372840 ps
T329	/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.875511970			Aug 02 08:27:37 PM PDT 24	Aug 02 08:36:45 PM PDT 24	4271875020 ps
T319	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2910708501			Aug 02 08:19:55 PM PDT 24	Aug 02 08:48:28 PM PDT 24	7691331290 ps
T330	/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.663705444			Aug 02 08:18:32 PM PDT 24	Aug 02 08:29:48 PM PDT 24	5681741720 ps
T87	/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4014372249			Aug 02 08:30:34 PM PDT 24	Aug 02 08:53:59 PM PDT 24	10936561792 ps
T215	/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2708192456			Aug 02 08:19:06 PM PDT 24	Aug 02 08:27:58 PM PDT 24	4313089928 ps
T112	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1326929456			Aug 02 08:25:43 PM PDT 24	Aug 02 09:55:15 PM PDT 24	27487259430 ps
T923	/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.4043442446			Aug 02 08:51:49 PM PDT 24	Aug 02 09:50:06 PM PDT 24	11358245909 ps
T218	/workspace/coverage/default/2.chip_sw_uart_tx_rx.3731269738			Aug 02 08:33:56 PM PDT 24	Aug 02 08:44:14 PM PDT 24	3944770624 ps
T749	/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2683361732			Aug 02 08:48:51 PM PDT 24	Aug 02 08:55:30 PM PDT 24	4127444750 ps
T42	/workspace/coverage/default/1.chip_sw_spi_device_tpm.1401752406			Aug 02 08:27:02 PM PDT 24	Aug 02 08:32:05 PM PDT 24	3087125529 ps
T80	/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3927129276			Aug 02 08:23:57 PM PDT 24	Aug 02 09:03:06 PM PDT 24	12106629589 ps
T15	/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1582153908			Aug 02 08:17:20 PM PDT 24	Aug 02 08:24:09 PM PDT 24	4262741958 ps
T334	/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1833643414			Aug 02 08:23:20 PM PDT 24	Aug 02 08:37:04 PM PDT 24	4716975342 ps
T924	/workspace/coverage/default/0.rom_e2e_static_critical.3231771422			Aug 02 08:31:22 PM PDT 24	Aug 02 09:50:35 PM PDT 24	17427178648 ps
T765	/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1655713764			Aug 02 08:28:25 PM PDT 24	Aug 02 08:48:59 PM PDT 24	6082901374 ps
T73	/workspace/coverage/default/3.chip_tap_straps_testunlock0.1186918142			Aug 02 08:45:10 PM PDT 24	Aug 02 08:54:51 PM PDT 24	5909879098 ps
T16	/workspace/coverage/default/1.chip_sw_sleep_pin_retention.4165642272			Aug 02 08:26:11 PM PDT 24	Aug 02 08:32:21 PM PDT 24	4758477500 ps
T418	/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3916687957			Aug 02 08:43:05 PM PDT 24	Aug 02 08:48:24 PM PDT 24	3529494640 ps
T419	/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.952434023			Aug 02 08:53:41 PM PDT 24	Aug 02 08:58:48 PM PDT 24	3329311640 ps
T152	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.17320799			Aug 02 08:38:18 PM PDT 24	Aug 02 09:00:40 PM PDT 24	12034580084 ps
T420	/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3108911507			Aug 02 08:21:59 PM PDT 24	Aug 02 08:25:29 PM PDT 24	2143707487 ps
T205	/workspace/coverage/default/0.chip_sw_inject_scramble_seed.4043239832			Aug 02 08:18:57 PM PDT 24	Aug 02 11:55:19 PM PDT 24	65223598285 ps
T421	/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2775418714			Aug 02 08:22:10 PM PDT 24	Aug 02 08:32:16 PM PDT 24	5135311800 ps
T245	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.3955988987			Aug 02 08:20:39 PM PDT 24	Aug 02 08:29:37 PM PDT 24	4879691902 ps
T72	/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.583341976			Aug 02 08:43:10 PM PDT 24	Aug 02 08:50:56 PM PDT 24	5319023668 ps
T188	/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2136993702			Aug 02 08:45:29 PM PDT 24	Aug 02 08:55:41 PM PDT 24	6554740405 ps
T113	/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.726908788			Aug 02 08:36:36 PM PDT 24	Aug 02 09:27:49 PM PDT 24	23208770053 ps
T925	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3114825911			Aug 02 08:38:56 PM PDT 24	Aug 02 09:02:04 PM PDT 24	6805497350 ps
T926	/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.731757242			Aug 02 08:40:02 PM PDT 24	Aug 02 08:57:43 PM PDT 24	5447845450 ps
T927	/workspace/coverage/default/0.chip_sw_hmac_smoketest.533809335			Aug 02 08:23:11 PM PDT 24	Aug 02 08:31:46 PM PDT 24	3214934536 ps
T260	/workspace/coverage/default/0.chip_sw_rv_timer_irq.226202024			Aug 02 08:17:37 PM PDT 24	Aug 02 08:22:35 PM PDT 24	3536888860 ps
T90	/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.207294885			Aug 02 08:50:04 PM PDT 24	Aug 02 08:55:32 PM PDT 24	4195848720 ps
T52	/workspace/coverage/default/0.chip_sw_alert_test.2244740157			Aug 02 08:18:35 PM PDT 24	Aug 02 08:24:00 PM PDT 24	3549847040 ps
T95	/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.1166533418			Aug 02 08:17:10 PM PDT 24	Aug 02 08:33:02 PM PDT 24	5683292336 ps
T96	/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.60101872			Aug 02 08:52:32 PM PDT 24	Aug 02 08:58:16 PM PDT 24	3761184082 ps
T97	/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.865348525			Aug 02 08:48:15 PM PDT 24	Aug 02 09:47:41 PM PDT 24	14279518810 ps
T98	/workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1301143683			Aug 02 08:23:33 PM PDT 24	Aug 02 08:28:40 PM PDT 24	3301782360 ps
T99	/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.10970142			Aug 02 08:47:41 PM PDT 24	Aug 02 09:09:01 PM PDT 24	13832281010 ps
T100	/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3381190483			Aug 02 08:21:48 PM PDT 24	Aug 02 08:25:49 PM PDT 24	2221515660 ps
T101	/workspace/coverage/default/91.chip_sw_all_escalation_resets.2463686265			Aug 02 08:56:07 PM PDT 24	Aug 02 09:04:19 PM PDT 24	5121734964 ps
T102	/workspace/coverage/default/2.chip_sw_kmac_smoketest.3753044566			Aug 02 08:44:56 PM PDT 24	Aug 02 08:50:02 PM PDT 24	3309482440 ps
T928	/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3897020736			Aug 02 08:22:10 PM PDT 24	Aug 02 08:25:51 PM PDT 24	3251531048 ps
T357	/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1410714520			Aug 02 08:25:15 PM PDT 24	Aug 02 08:51:37 PM PDT 24	8327806822 ps
T375	/workspace/coverage/default/0.chip_sival_flash_info_access.745976497			Aug 02 08:17:46 PM PDT 24	Aug 02 08:22:22 PM PDT 24	3683668992 ps
T929	/workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3183441023			Aug 02 08:35:42 PM PDT 24	Aug 02 08:40:07 PM PDT 24	2958292750 ps
T930	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1585992918			Aug 02 08:31:19 PM PDT 24	Aug 02 08:41:29 PM PDT 24	4154480808 ps
T705	/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2159995190			Aug 02 08:26:47 PM PDT 24	Aug 02 08:51:31 PM PDT 24	15605264904 ps
T8	/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3551979010			Aug 02 08:20:42 PM PDT 24	Aug 02 08:27:14 PM PDT 24	3377723840 ps
T809	/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2816460748			Aug 02 08:53:40 PM PDT 24	Aug 02 09:00:42 PM PDT 24	4016882856 ps
T355	/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.419817203			Aug 02 08:36:24 PM PDT 24	Aug 02 08:47:36 PM PDT 24	4979329115 ps
T768	/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2469881181			Aug 02 08:50:38 PM PDT 24	Aug 02 08:57:29 PM PDT 24	3507501988 ps
T831	/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2182751006			Aug 02 08:54:03 PM PDT 24	Aug 02 09:00:14 PM PDT 24	3892864616 ps
T143	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2011093136			Aug 02 08:46:48 PM PDT 24	Aug 02 08:55:50 PM PDT 24	4629991016 ps
T931	/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.61201462			Aug 02 08:38:37 PM PDT 24	Aug 02 09:45:22 PM PDT 24	14610664180 ps
T780	/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2324189550			Aug 02 08:39:05 PM PDT 24	Aug 02 08:47:00 PM PDT 24	4079266148 ps
T932	/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.1926791008			Aug 02 08:19:54 PM PDT 24	Aug 02 08:25:31 PM PDT 24	3956454764 ps
T177	/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2859907739			Aug 02 08:50:05 PM PDT 24	Aug 02 09:58:23 PM PDT 24	14996741194 ps
T933	/workspace/coverage/default/1.chip_sw_example_rom.1405880539			Aug 02 08:22:39 PM PDT 24	Aug 02 08:24:34 PM PDT 24	2123725704 ps
T265	/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3687382565			Aug 02 08:40:14 PM PDT 24	Aug 02 08:50:08 PM PDT 24	5679593100 ps
T280	/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.1965151606			Aug 02 08:30:04 PM PDT 24	Aug 02 08:42:23 PM PDT 24	8795731734 ps
T761	/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1363014200			Aug 02 08:46:50 PM PDT 24	Aug 02 08:54:01 PM PDT 24	3419180914 ps
T27	/workspace/coverage/default/2.chip_sw_gpio_smoketest.3394088557			Aug 02 08:43:39 PM PDT 24	Aug 02 08:48:46 PM PDT 24	2934374347 ps
T934	/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3109308563			Aug 02 08:21:15 PM PDT 24	Aug 02 08:28:49 PM PDT 24	4278102320 ps
T401	/workspace/coverage/default/0.rom_e2e_jtag_debug_dev.1980217019			Aug 02 08:25:39 PM PDT 24	Aug 02 09:00:58 PM PDT 24	10659868507 ps
T149	/workspace/coverage/default/0.chip_plic_all_irqs_10.722480689			Aug 02 08:19:45 PM PDT 24	Aug 02 08:31:53 PM PDT 24	3529502962 ps
T775	/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.4034803016			Aug 02 08:49:36 PM PDT 24	Aug 02 08:56:00 PM PDT 24	3811096000 ps
T935	/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1161914117			Aug 02 08:41:55 PM PDT 24	Aug 02 08:45:25 PM PDT 24	2866410860 ps
T936	/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.570748476			Aug 02 08:33:47 PM PDT 24	Aug 02 08:45:06 PM PDT 24	5073744358 ps
T394	/workspace/coverage/default/1.rom_e2e_asm_init_prod.2992804014			Aug 02 08:37:49 PM PDT 24	Aug 02 09:46:40 PM PDT 24	15408904985 ps
T372	/workspace/coverage/default/93.chip_sw_all_escalation_resets.1812011381			Aug 02 08:54:42 PM PDT 24	Aug 02 09:01:33 PM PDT 24	4951503240 ps
T144	/workspace/coverage/default/1.chip_sw_power_idle_load.3770107343			Aug 02 08:31:24 PM PDT 24	Aug 02 08:39:32 PM PDT 24	3911657260 ps
T103	/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1090904802			Aug 02 08:31:07 PM PDT 24	Aug 02 08:56:36 PM PDT 24	22169739990 ps
T758	/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2299985374			Aug 02 08:48:29 PM PDT 24	Aug 02 08:54:20 PM PDT 24	3329867368 ps
T189	/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3260560745			Aug 02 08:17:36 PM PDT 24	Aug 02 08:25:06 PM PDT 24	5684079541 ps
T279	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1923023316			Aug 02 08:32:18 PM PDT 24	Aug 02 10:10:49 PM PDT 24	23343815970 ps
T937	/workspace/coverage/default/0.chip_sw_flash_crash_alert.2877159688			Aug 02 08:21:27 PM PDT 24	Aug 02 08:32:40 PM PDT 24	5035726712 ps
T114	/workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.2979298128			Aug 02 08:42:09 PM PDT 24	Aug 02 09:52:47 PM PDT 24	20793944557 ps
T332	/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1878051550			Aug 02 08:50:38 PM PDT 24	Aug 02 09:32:24 PM PDT 24	12854902020 ps
T938	/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.488902991			Aug 02 08:29:20 PM PDT 24	Aug 02 08:33:27 PM PDT 24	2900768006 ps
T939	/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.730663949			Aug 02 08:32:43 PM PDT 24	Aug 02 08:35:33 PM PDT 24	2191360856 ps
T213	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1271381732			Aug 02 08:46:18 PM PDT 24	Aug 02 08:58:26 PM PDT 24	4193733336 ps
T369	/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.478791899			Aug 02 08:44:34 PM PDT 24	Aug 02 08:55:24 PM PDT 24	4197198696 ps
T28	/workspace/coverage/default/2.chip_sw_sleep_pin_retention.2761042644			Aug 02 08:37:53 PM PDT 24	Aug 02 08:42:26 PM PDT 24	3644767490 ps
T746	/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3787772664			Aug 02 08:46:08 PM PDT 24	Aug 02 08:52:06 PM PDT 24	3579282568 ps
T940	/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3123442003			Aug 02 08:25:52 PM PDT 24	Aug 02 08:34:40 PM PDT 24	5801511780 ps
T941	/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3053142619			Aug 02 08:18:29 PM PDT 24	Aug 02 08:44:02 PM PDT 24	8572173762 ps
T172	/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1864672827			Aug 02 08:46:27 PM PDT 24	Aug 02 09:02:42 PM PDT 24	10180168611 ps
T942	/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.501991608			Aug 02 08:18:08 PM PDT 24	Aug 02 08:28:13 PM PDT 24	19490508060 ps
T756	/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2421037061			Aug 02 08:31:19 PM PDT 24	Aug 02 08:48:25 PM PDT 24	7906857786 ps
T943	/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.2359086798			Aug 02 08:47:22 PM PDT 24	Aug 02 08:57:09 PM PDT 24	7373082382 ps
T399	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.327782517			Aug 02 08:26:28 PM PDT 24	Aug 02 09:39:25 PM PDT 24	18312724086 ps
T222	/workspace/coverage/default/86.chip_sw_all_escalation_resets.4084573545			Aug 02 08:54:46 PM PDT 24	Aug 02 09:05:24 PM PDT 24	5784333648 ps
T744	/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3648096183			Aug 02 08:54:54 PM PDT 24	Aug 02 08:58:58 PM PDT 24	3790640630 ps
T944	/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.714293261			Aug 02 08:36:45 PM PDT 24	Aug 02 08:48:05 PM PDT 24	4230640098 ps
T214	/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1264412263			Aug 02 08:44:02 PM PDT 24	Aug 02 09:02:13 PM PDT 24	9245951245 ps
T945	/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4177382301			Aug 02 08:37:17 PM PDT 24	Aug 02 08:40:57 PM PDT 24	3172673261 ps
T146	/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2994795607			Aug 02 08:47:11 PM PDT 24	Aug 02 10:15:40 PM PDT 24	24575537315 ps
T269	/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.4276206006			Aug 02 08:39:58 PM PDT 24	Aug 03 12:20:48 AM PDT 24	254733475100 ps
T437	/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2062696566			Aug 02 08:22:06 PM PDT 24	Aug 02 09:07:36 PM PDT 24	34690193633 ps
T760	/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031822419			Aug 02 08:49:44 PM PDT 24	Aug 02 08:56:53 PM PDT 24	4133182720 ps
T338	/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3138250209			Aug 02 08:26:37 PM PDT 24	Aug 02 08:43:36 PM PDT 24	4624720742 ps
T244	/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2506946028			Aug 02 08:20:46 PM PDT 24	Aug 02 08:34:34 PM PDT 24	5666988649 ps
T946	/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.589978167			Aug 02 08:20:28 PM PDT 24	Aug 02 09:37:14 PM PDT 24	18095768290 ps
T400	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1537044553			Aug 02 08:27:58 PM PDT 24	Aug 02 10:03:07 PM PDT 24	24123843710 ps
T763	/workspace/coverage/default/50.chip_sw_all_escalation_resets.230725976			Aug 02 08:50:38 PM PDT 24	Aug 02 09:03:18 PM PDT 24	5782081600 ps
T248	/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.775894550			Aug 02 08:35:44 PM PDT 24	Aug 02 08:44:36 PM PDT 24	4662739372 ps
T381	/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.37515448			Aug 02 08:47:53 PM PDT 24	Aug 02 08:54:31 PM PDT 24	3587282260 ps
T388	/workspace/coverage/default/88.chip_sw_all_escalation_resets.3073007986			Aug 02 08:57:44 PM PDT 24	Aug 02 09:05:07 PM PDT 24	4881890992 ps
T219	/workspace/coverage/default/0.chip_sw_power_idle_load.3958930235			Aug 02 08:21:24 PM PDT 24	Aug 02 08:32:01 PM PDT 24	4393426230 ps
T389	/workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.1436713999			Aug 02 08:40:32 PM PDT 24	Aug 02 09:03:24 PM PDT 24	7940907516 ps
T109	/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.622693127			Aug 02 08:41:06 PM PDT 24	Aug 02 08:49:00 PM PDT 24	3464800478 ps
T390	/workspace/coverage/default/2.chip_sw_flash_ctrl_access.447206575			Aug 02 08:35:50 PM PDT 24	Aug 02 08:56:22 PM PDT 24	5236616852 ps
T12	/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.1582486214			Aug 02 08:35:02 PM PDT 24	Aug 02 08:45:07 PM PDT 24	4111431260 ps
T391	/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2179560184			Aug 02 08:36:41 PM PDT 24	Aug 02 08:49:07 PM PDT 24	8483625556 ps
T392	/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.4100955564			Aug 02 08:54:27 PM PDT 24	Aug 02 09:00:40 PM PDT 24	3170080376 ps
T393	/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.3547810879			Aug 02 08:30:41 PM PDT 24	Aug 02 10:55:43 PM PDT 24	24257740298 ps
T730	/workspace/coverage/default/1.chip_sw_hmac_oneshot.2007125362			Aug 02 08:29:38 PM PDT 24	Aug 02 08:36:21 PM PDT 24	2670167464 ps
T368	/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1726650794			Aug 02 08:38:43 PM PDT 24	Aug 02 08:45:01 PM PDT 24	3100968267 ps
T731	/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.623535567			Aug 02 08:48:18 PM PDT 24	Aug 02 08:54:08 PM PDT 24	3878267000 ps
T382	/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1288626798			Aug 02 08:20:57 PM PDT 24	Aug 02 08:27:30 PM PDT 24	4085578620 ps
T225	/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2852912723			Aug 02 08:40:29 PM PDT 24	Aug 02 09:02:39 PM PDT 24	6120766904 ps
T161	/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1612693623			Aug 02 08:32:05 PM PDT 24	Aug 02 09:19:58 PM PDT 24	11328925845 ps
T159	/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.623219690			Aug 02 08:26:13 PM PDT 24	Aug 02 08:28:05 PM PDT 24	2270815427 ps
T246	/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2938402939			Aug 02 08:20:07 PM PDT 24	Aug 02 08:27:56 PM PDT 24	4483529766 ps
T160	/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3323729601			Aug 02 08:20:53 PM PDT 24	Aug 02 08:29:40 PM PDT 24	4954066952 ps
T947	/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.686831991			Aug 02 08:30:11 PM PDT 24	Aug 02 08:41:17 PM PDT 24	3480681184 ps