Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.i2c2_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	139195	1			T77	2		T78	16		T79	16
values[2]	10138	1			T79	1		T123	1		T547	120
values[3]	3865	1			T547	85		T490	14		T556	21
values[4]	2288	1			T547	73		T556	30		T700	40
values[5]	1457	1			T547	49		T556	20		T700	48
values[6]	970	1			T547	31		T556	28		T700	33
values[7]	818	1			T547	32		T556	24		T700	27
values[8]	626	1			T547	12		T556	24		T700	16
values[9]	473	1			T547	5		T556	37		T700	11
values[10]	409	1			T556	13		T700	13		T859	9
values[11]	418	1			T556	28		T700	3		T859	12
values[12]	344	1			T556	16		T859	13		T860	1
values[13]	334	1			T556	20		T859	4		T860	1
values[14]	317	1			T556	39		T859	4		T860	1
values[15]	304	1			T556	33		T859	12		T860	1
values[16]	366	1			T556	20		T859	8		T860	1
values[17]	315	1			T556	20		T859	5		T860	1
values[18]	318	1			T556	13		T859	4		T860	1
values[19]	256	1			T556	12		T859	5		T860	1
values[20]	319	1			T556	24		T859	6		T860	1
values[21]	294	1			T556	25		T859	3		T860	1
values[22]	358	1			T556	21		T859	13		T860	1
values[23]	291	1			T556	17		T859	9		T860	1
values[24]	280	1			T556	13		T859	14		T860	1
values[25]	273	1			T556	30		T859	10		T860	1
values[26]	310	1			T556	25		T859	3		T860	1
values[27]	367	1			T556	22		T859	6		T860	1
values[28]	329	1			T556	25		T859	2		T860	1
values[29]	347	1			T556	21		T859	4		T860	1
values[30]	308	1			T556	31		T859	6		T860	1
values[31]	295	1			T556	11		T859	8		T860	1
values[32]	297	1			T556	14		T859	6		T860	1
values[33]	300	1			T556	21		T859	17		T860	1
values[34]	343	1			T556	20		T859	4		T860	1
values[35]	368	1			T556	20		T859	7		T860	1
values[36]	349	1			T556	19		T859	9		T860	1
values[37]	326	1			T556	50		T859	3		T860	1
values[38]	301	1			T556	11		T859	5		T860	1
values[39]	280	1			T556	21		T859	5		T860	1
values[40]	304	1			T556	12		T859	6		T860	1
values[41]	296	1			T556	25		T859	5		T860	1
values[42]	284	1			T556	27		T859	6		T860	1
values[43]	300	1			T556	34		T859	4		T860	1
values[44]	294	1			T556	34		T859	6		T860	1
values[45]	253	1			T556	26		T859	3		T860	1
values[46]	278	1			T556	21		T859	3		T860	1
values[47]	285	1			T556	21		T859	13		T860	1
values[48]	261	1			T556	15		T859	7		T860	1
values[49]	271	1			T556	18		T859	8		T860	1
values[50]	273	1			T556	12		T859	8		T860	1
values[51]	275	1			T556	16		T859	16		T860	1
values[52]	275	1			T556	15		T859	10		T860	1
values[53]	278	1			T556	15		T860	1		T528	4
values[54]	229	1			T556	11		T860	1		T528	4
values[55]	214	1			T556	12		T860	1		T528	2
values[56]	227	1			T556	12		T860	1		T528	6
values[57]	227	1			T556	18		T860	1		T528	8
values[58]	180	1			T556	7		T860	1		T528	8
values[59]	191	1			T556	11		T860	1		T528	2
values[60]	218	1			T556	14		T860	1		T528	4
values[61]	197	1			T556	23		T860	1		T528	2
values[62]	157	1			T556	9		T860	1		T528	2
values[63]	204	1			T556	15		T860	1		T528	4
values[64]	187	1			T556	19		T860	1		T528	2
values[65]	201	1			T556	29		T860	1		T528	1
values[66]	217	1			T556	11		T860	1		T528	4
values[67]	162	1			T556	17		T860	1		T528	2
values[68]	200	1			T556	12		T860	1		T528	5
values[69]	157	1			T556	13		T860	1		T528	4
values[70]	172	1			T556	10		T860	1		T528	5
values[71]	130	1			T556	2		T860	1		T528	8
values[72]	126	1			T860	1		T528	10		T856	2
values[73]	117	1			T860	1		T528	9		T856	2
values[74]	125	1			T860	1		T528	3		T856	2
values[75]	112	1			T860	1		T528	6		T856	2
values[76]	109	1			T860	1		T528	6		T856	2
values[77]	93	1			T860	1		T528	2		T856	2
values[78]	110	1			T860	1		T528	6		T856	2
values[79]	79	1			T860	1		T528	1		T856	2
values[80]	72	1			T860	1		T528	1		T856	2
values[81]	89	1			T860	1		T528	9		T856	2
values[82]	88	1			T860	1		T528	8		T856	2
values[83]	74	1			T860	1		T528	2		T856	2
values[84]	68	1			T860	1		T528	1		T856	2
values[85]	82	1			T860	1		T528	8		T856	2
values[86]	79	1			T860	1		T528	6		T856	2
values[87]	95	1			T860	1		T528	6		T856	2
values[88]	89	1			T860	1		T528	4		T856	2
values[89]	93	1			T860	1		T528	8		T856	2
values[90]	95	1			T860	1		T528	5		T856	2
values[91]	96	1			T860	1		T528	5		T856	2
values[92]	78	1			T860	1		T528	1		T856	2
values[93]	95	1			T860	1		T528	2		T856	2
values[94]	84	1			T860	1		T528	5		T856	2
values[95]	79	1			T860	1		T528	9		T856	2
values[96]	96	1			T860	1		T528	7		T856	2
values[97]	98	1			T860	1		T528	4		T856	2
values[98]	113	1			T860	1		T528	11		T856	2
values[99]	78	1			T860	1		T528	8		T856	2
values[100]	103	1			T860	1		T528	5		T856	2
values[101]	120	1			T860	1		T528	6		T856	2
values[102]	113	1			T860	1		T528	9		T856	2
values[103]	99	1			T860	1		T528	2		T856	3
values[104]	84	1			T860	1		T528	3		T856	2
values[105]	69	1			T860	1		T528	2		T856	2
values[106]	82	1			T860	1		T528	1		T856	2
values[107]	87	1			T860	1		T528	2		T856	2
values[108]	98	1			T860	1		T528	2		T856	2
values[109]	69	1			T860	1		T528	2		T856	2
values[110]	72	1			T860	1		T528	4		T856	2
values[111]	79	1			T860	1		T528	2		T856	2
values[112]	115	1			T860	2		T528	1		T856	2
values[113]	89	1			T860	1		T528	1		T856	2
values[114]	87	1			T860	1		T528	3		T856	2
values[115]	83	1			T860	1		T528	4		T856	2
values[116]	93	1			T860	1		T528	6		T856	2
values[117]	85	1			T860	1		T528	6		T856	2
values[118]	96	1			T860	1		T528	7		T856	2
values[119]	81	1			T860	1		T528	6		T856	2
values[120]	71	1			T860	1		T528	4		T856	3
values[121]	60	1			T860	1		T528	5		T856	2
values[122]	91	1			T860	1		T528	7		T856	3
values[123]	75	1			T860	2		T528	2		T856	6
values[124]	75	1			T860	1		T528	3		T856	2
values[125]	73	1			T860	3		T528	5		T856	2
values[126]	97	1			T860	1		T528	9		T856	4
values[127]	875	1			T860	39		T528	8		T856	51
values[128]	7968	1			T860	366		T528	4		T856	650