Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cfg_agent.cov::m_max_outstanding_cg

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	128	0	128	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	154915	1			T77	2		T78	29		T79	12
values[2]	4189	1			T553	1		T547	7		T490	3
values[3]	2203	1			T547	4		T555	1		T571	2
values[4]	1703	1			T547	8		T555	1		T528	3
values[5]	1455	1			T547	7		T555	1		T528	7
values[6]	1194	1			T547	2		T555	1		T528	6
values[7]	976	1			T547	9		T555	1		T528	3
values[8]	834	1			T547	25		T555	1		T528	8
values[9]	760	1			T547	39		T555	1		T528	7
values[10]	669	1			T547	36		T555	1		T528	9
values[11]	637	1			T547	35		T555	1		T528	6
values[12]	648	1			T547	36		T555	1		T528	6
values[13]	557	1			T547	26		T555	1		T528	10
values[14]	531	1			T547	20		T555	1		T528	3
values[15]	452	1			T547	23		T555	1		T528	5
values[16]	459	1			T547	42		T555	1		T528	5
values[17]	383	1			T547	17		T555	1		T528	9
values[18]	290	1			T547	25		T555	1		T528	10
values[19]	260	1			T547	12		T555	1		T528	2
values[20]	229	1			T547	5		T555	1		T528	4
values[21]	148	1			T547	2		T555	1		T528	4
values[22]	126	1			T547	12		T555	1		T528	4
values[23]	132	1			T547	10		T555	1		T528	4
values[24]	156	1			T547	2		T555	1		T528	2
values[25]	227	1			T555	1		T528	3		T872	1
values[26]	214	1			T555	1		T528	5		T872	1
values[27]	182	1			T555	1		T528	13		T872	1
values[28]	168	1			T555	1		T528	9		T872	1
values[29]	161	1			T555	1		T528	7		T872	1
values[30]	122	1			T555	1		T528	6		T872	1
values[31]	121	1			T555	1		T528	6		T872	1
values[32]	110	1			T555	1		T528	3		T872	1
values[33]	126	1			T555	1		T528	3		T872	1
values[34]	109	1			T555	1		T528	4		T872	1
values[35]	107	1			T555	1		T528	8		T872	1
values[36]	99	1			T555	1		T528	7		T872	1
values[37]	77	1			T555	1		T528	3		T872	1
values[38]	72	1			T555	1		T528	7		T872	1
values[39]	57	1			T555	1		T528	2		T872	1
values[40]	56	1			T555	1		T528	2		T872	1
values[41]	64	1			T555	1		T528	5		T872	1
values[42]	65	1			T555	1		T528	5		T872	1
values[43]	58	1			T555	1		T528	4		T872	1
values[44]	60	1			T555	1		T528	8		T872	1
values[45]	48	1			T555	1		T528	5		T872	1
values[46]	43	1			T555	1		T528	4		T872	1
values[47]	45	1			T555	1		T528	5		T872	1
values[48]	43	1			T555	1		T528	6		T872	1
values[49]	42	1			T555	1		T528	4		T872	1
values[50]	41	1			T555	1		T528	2		T872	1
values[51]	47	1			T555	1		T528	5		T872	1
values[52]	50	1			T555	1		T528	5		T872	1
values[53]	49	1			T555	2		T528	7		T872	1
values[54]	50	1			T555	1		T528	5		T872	1
values[55]	42	1			T555	1		T528	4		T872	1
values[56]	46	1			T555	1		T528	5		T872	1
values[57]	45	1			T555	1		T528	6		T872	1
values[58]	47	1			T555	1		T528	9		T872	1
values[59]	40	1			T555	1		T528	4		T872	1
values[60]	43	1			T555	1		T528	5		T872	1
values[61]	50	1			T555	1		T528	12		T872	1
values[62]	43	1			T555	1		T528	2		T872	1
values[63]	46	1			T555	1		T528	7		T872	1
values[64]	40	1			T555	1		T528	3		T872	1
values[65]	43	1			T555	1		T528	4		T872	1
values[66]	41	1			T555	1		T528	3		T872	1
values[67]	42	1			T555	1		T528	3		T872	1
values[68]	45	1			T555	1		T528	7		T872	1
values[69]	44	1			T555	1		T528	6		T872	2
values[70]	48	1			T555	1		T528	9		T872	1
values[71]	44	1			T555	1		T528	5		T872	1
values[72]	42	1			T555	1		T528	4		T872	1
values[73]	41	1			T555	1		T528	4		T872	1
values[74]	43	1			T555	1		T528	3		T872	1
values[75]	48	1			T555	1		T528	8		T872	1
values[76]	53	1			T555	1		T528	7		T872	1
values[77]	53	1			T555	1		T528	7		T872	1
values[78]	51	1			T555	1		T528	6		T872	1
values[79]	48	1			T555	1		T528	5		T872	1
values[80]	55	1			T555	1		T528	7		T872	1
values[81]	55	1			T555	2		T528	9		T872	1
values[82]	56	1			T555	1		T528	7		T872	1
values[83]	60	1			T555	1		T528	8		T872	1
values[84]	68	1			T555	1		T528	10		T872	2
values[85]	74	1			T555	1		T528	9		T872	8
values[86]	60	1			T555	1		T528	5		T872	5
values[87]	62	1			T555	1		T528	12		T872	2
values[88]	59	1			T555	1		T528	3		T872	3
values[89]	64	1			T555	1		T528	7		T872	4
values[90]	66	1			T555	1		T528	10		T872	1
values[91]	75	1			T555	1		T528	8		T872	1
values[92]	74	1			T555	1		T528	10		T872	3
values[93]	68	1			T555	1		T528	10		T872	3
values[94]	74	1			T555	1		T528	10		T872	5
values[95]	70	1			T555	1		T528	7		T872	3
values[96]	79	1			T555	1		T528	8		T872	1
values[97]	64	1			T555	1		T528	9		T872	2
values[98]	58	1			T555	1		T528	6		T872	3
values[99]	67	1			T555	1		T528	11		T872	1
values[100]	77	1			T555	1		T528	10		T872	4
values[101]	75	1			T555	1		T528	12		T872	2
values[102]	71	1			T555	1		T528	13		T872	2
values[103]	80	1			T555	1		T528	10		T872	2
values[104]	83	1			T555	1		T528	11		T872	2
values[105]	62	1			T555	1		T528	7		T872	4
values[106]	69	1			T555	1		T528	4		T872	4
values[107]	80	1			T555	1		T528	5		T872	2
values[108]	85	1			T555	1		T528	7		T872	5
values[109]	72	1			T555	1		T528	4		T872	3
values[110]	90	1			T555	1		T528	8		T872	6
values[111]	89	1			T555	1		T528	5		T872	2
values[112]	81	1			T555	1		T528	5		T872	2
values[113]	91	1			T555	2		T528	7		T872	3
values[114]	74	1			T555	2		T528	8		T872	1
values[115]	83	1			T555	1		T528	14		T872	1
values[116]	78	1			T555	1		T528	6		T872	3
values[117]	93	1			T555	4		T528	10		T872	2
values[118]	107	1			T555	2		T528	10		T872	4
values[119]	91	1			T555	4		T528	7		T872	5
values[120]	85	1			T555	3		T528	7		T872	3
values[121]	78	1			T555	3		T528	9		T872	2
values[122]	87	1			T555	1		T528	17		T872	1
values[123]	95	1			T555	2		T528	18		T872	3
values[124]	116	1			T555	3		T528	28		T872	2
values[125]	157	1			T555	5		T528	46		T872	5
values[126]	652	1			T555	10		T528	57		T872	17
values[127]	4082	1			T555	113		T528	56		T872	108
values[128]	7233	1			T555	253		T528	4		T872	188